Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	30595	1			T1	184		T2	8		T4	6
auto[SpiFlashAddrCfg]	6167	1			T1	18		T2	4		T5	6
auto[SpiFlashAddr3b]	7474	1			T1	32		T7	46		T9	2
auto[SpiFlashAddr4b]	6521	1			T1	8		T2	6		T5	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28704

1

T1

181

T2

18

T4

6

auto[1]

22053

1

T1

61

T7

300

T15

143

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27803

1

T1

166

T2

8

T4

2

auto[1]

22954

1

T1

76

T2

10

T4

4

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	34425	1			T1	203		T2	10		T4	6
values[1]	910	1			T1	1		T7	4		T15	7
values[2]	1244	1			T1	5		T15	1		T29	8
values[3]	1132	1			T2	2		T7	10		T15	2
values[4]	1177	1			T1	1		T5	2		T7	5
values[5]	1186	1			T1	1		T2	2		T7	2
values[6]	1231	1			T1	4		T2	2		T7	14
values[7]	1219	1			T1	1		T2	2		T7	8
values[8]	8233	1			T1	26		T5	4		T7	57

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26050

1

T2

18

T4

6

T5

187

auto[1]

24707

1

T1

242

T29

256

T18

448

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

48213

1

T1

225

T2

18

T4

6

write

2544

1

T1

17

T5

4

T7

26

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

15974

1

T1

41

T2

6

T5

4

valids[0x1]

34783

1

T1

201

T2

12

T4

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1318	1			T1	5		T2	2		T4	2
internal_process_ops[0x5a]	1260	1			T1	2		T7	6		T9	2
internal_process_ops[0x05]	19216	1			T1	145		T5	169		T7	283
internal_process_ops[0x35]	1270	1			T1	8		T2	4		T4	4
internal_process_ops[0x15]	1280	1			T1	6		T5	2		T7	6
internal_process_ops[0x03]	864	1			T1	2		T2	2		T5	2
internal_process_ops[0x0b]	947	1			T1	1		T2	2		T5	2
internal_process_ops[0x3b]	913	1			T1	1		T2	2		T5	2
internal_process_ops[0x6b]	907	1			T1	1		T7	6		T15	4
internal_process_ops[0xbb]	871	1			T1	2		T7	5		T15	8
internal_process_ops[0xeb]	880	1			T5	2		T7	6		T15	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49546

1

T1

235

T2

18

T4

6

auto[1]

1211

1

T1

7

T7

14

T15

5

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48913

1

T1

224

T2

18

T4

6

auto[1]

1844

1

T1

18

T5

4

T7

17

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8651

1

T2

8

T4

6

T5

175

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5524

1

T7

230

T15

80

T51

8

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1738

1

T2

4

T5

4

T7

31

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1526

1

T7

15

T15

17

T51

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2192

1

T7

26

T9

2

T15

14

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1705

1

T7

16

T15

14

T25

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1804

1

T2

6

T5

4

T7

14

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1598

1

T7

19

T15

25

T25

10

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

89

1

T20

1

T156

2

T66

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

71

1

T19

2

T54

4

T21

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

80

1

T7

5

T15

1

T46

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

90

1

T7

6

T19

1

T20

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

86

1

T5

2

T46

1

T162

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

64

1

T7

3

T19

1

T46

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

82

1

T7

3

T19

1

T46

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

80

1

T7

1

T20

2

T53

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

91

1

T35

2

T46

1

T20

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

74

1

T7

2

T19

1

T20

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

63

1

T15

1

T20

1

T21

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

94

1

T7

2

T15

2

T51

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

97

1

T5

2

T7

1

T47

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

83

1

T46

3

T20

1

T21

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

84

1

T7

3

T19

2

T162

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

84

1

T15

3

T20

3

T53

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9154

1

T1

146

T29

71

T18

182

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6644

1

T1

33

T29

65

T18

98

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1145

1

T1

8

T29

17

T18

14

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1148

1

T1

6

T29

8

T18

19

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1521

1

T1

13

T29

20

T18

24

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1440

1

T1

12

T29

18

T18

35

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1227

1

T1

4

T29

26

T18

19

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1196

1

T1

3

T29

15

T18

30

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

85

1

T1

1

T18

3

T19

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

72

1

T1

1

T29

1

T19

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

77

1

T1

1

T29

2

T126

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

58

1

T1

2

T29

1

T19

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

92

1

T1

2

T29

3

T18

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

58

1

T1

2

T18

3

T19

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

84

1

T18

5

T56

3

T126

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

64

1

T19

3

T126

1

T40

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

70

1

T1

1

T29

1

T18

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

72

1

T1

2

T126

2

T155

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

88

1

T1

4

T29

2

T18

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

64

1

T29

3

T18

2

T126

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

96

1

T1

1

T29

1

T126

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

72

1

T19

2

T56

3

T58

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

69

1

T29

2

T18

2

T126

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

111

1

T18

2

T19

1

T126

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3270	1			T2	2		T7	43		T15	26
auto[0]	values[0]	valids[0x1]	13346	1			T2	8		T4	6		T5	181
auto[0]	values[1]	valids[0x1]	457	1			T7	4		T15	7		T19	9
auto[0]	values[2]	valids[0x0]	496	1			T15	1		T50	4		T47	2
auto[0]	values[2]	valids[0x1]	242	1			T19	1		T46	10		T127	2
auto[0]	values[3]	valids[0x0]	416	1			T2	2		T7	7		T15	2
auto[0]	values[3]	valids[0x1]	224	1			T7	3		T90	2		T26	2
auto[0]	values[4]	valids[0x0]	421	1			T5	2		T7	2		T15	3
auto[0]	values[4]	valids[0x1]	226	1			T7	3		T15	1		T27	4
auto[0]	values[5]	valids[0x0]	414	1			T7	2		T15	3		T49	2
auto[0]	values[5]	valids[0x1]	278	1			T2	2		T15	5		T19	8
auto[0]	values[6]	valids[0x0]	491	1			T2	2		T7	11		T15	3
auto[0]	values[6]	valids[0x1]	256	1			T7	3		T15	2		T49	2
auto[0]	values[7]	valids[0x0]	474	1			T7	7		T15	5		T19	11
auto[0]	values[7]	valids[0x1]	259	1			T2	2		T7	1		T26	2
auto[0]	values[8]	valids[0x0]	2999	1			T5	2		T7	40		T15	34
auto[0]	values[8]	valids[0x1]	1781	1			T5	2		T7	17		T9	2
auto[1]	values[0]	valids[0x0]	3117	1			T1	21		T29	50		T18	46
auto[1]	values[0]	valids[0x1]	14692	1			T1	182		T29	106		T18	286
auto[1]	values[1]	valids[0x1]	453	1			T1	1		T18	8		T19	17
auto[1]	values[2]	valids[0x0]	320	1			T1	2		T29	7		T18	7
auto[1]	values[2]	valids[0x1]	186	1			T1	3		T29	1		T18	2
auto[1]	values[3]	valids[0x0]	290	1			T29	3		T18	9		T19	11
auto[1]	values[3]	valids[0x1]	202	1			T29	1		T19	4		T126	8
auto[1]	values[4]	valids[0x0]	314	1			T1	1		T29	7		T18	4
auto[1]	values[4]	valids[0x1]	216	1			T29	15		T18	7		T56	3
auto[1]	values[5]	valids[0x0]	289	1			T1	1		T18	5		T19	1
auto[1]	values[5]	valids[0x1]	205	1			T29	5		T18	2		T19	3
auto[1]	values[6]	valids[0x0]	287	1			T1	2		T29	4		T19	4
auto[1]	values[6]	valids[0x1]	197	1			T1	2		T29	4		T18	4
auto[1]	values[7]	valids[0x0]	285	1			T1	1		T29	1		T18	6
auto[1]	values[7]	valids[0x1]	201	1			T19	2		T126	6		T155	1
auto[1]	values[8]	valids[0x0]	2091	1			T1	13		T29	34		T18	41
auto[1]	values[8]	valids[0x1]	1362	1			T1	13		T29	18		T18	21