Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2753708

1

T1

3526

T2

1

T4

13561

auto[1]

17913

1

T1

142

T5

169

T7

276

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

810065

1

T1

55

T2

1

T4

9297

auto[1]

1961556

1

T1

3613

T4

4264

T5

177

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	564204	1			T1	678		T2	1		T4	2909
auto[524288:1048575]	307001	1			T1	6		T7	62		T9	11
auto[1048576:1572863]	334469	1			T1	1		T7	4977		T9	2
auto[1572864:2097151]	269217	1			T1	263		T4	732		T7	1059
auto[2097152:2621439]	336835	1			T1	951		T4	256		T7	3
auto[2621440:3145727]	357918	1			T1	1419		T4	7663		T7	5449
auto[3145728:3670015]	305862	1			T1	350		T7	593		T15	2044
auto[3670016:4194303]	296115	1			T4	2001		T7	258		T9	1552

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1978947

1

T1

3662

T2

1

T4

4274

auto[1]

792674

1

T1

6

T4

9287

T5

3

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2394881

1

T1

1216

T2

1

T4

13561

auto[1]

376740

1

T1

2452

T7

5110

T15

4875

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	196165	1			T1	8		T2	1		T4	778
auto[0]	auto[0]	auto[0:524287]	auto[1]	324112	1			T1	648		T4	2131		T5	12
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	93661	1			T7	5		T9	11		T15	1
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	181704	1			T7	2		T15	256		T29	748
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	94824	1			T1	1		T7	6		T9	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	182597	1			T7	1450		T29	644		T18	2737
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	65330	1			T1	2		T4	732		T7	6
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	152696	1			T1	5		T7	513		T9	3
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	105333	1			T1	8		T4	1		T7	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	190760	1			T1	140		T4	255		T7	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	71170	1			T1	1		T4	5787		T7	5
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	215870	1			T1	1		T4	1876		T7	4879
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	93576	1			T1	10		T7	11		T15	4
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	160023	1			T1	323		T7	515		T15	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	78043	1			T4	1999		T7	2		T9	1295
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	174554	1			T4	2		T9	257		T15	514
auto[0]	auto[1]	auto[0:524287]	auto[0]	1514	1			T7	2		T15	3		T52	5
auto[0]	auto[1]	auto[0:524287]	auto[1]	39135	1			T7	257		T15	2		T18	769
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1638	1			T1	2		T7	2		T29	5
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	28131	1			T1	1		T29	514		T19	1922
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	2640	1			T7	11		T19	2		T46	4
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	52379	1			T7	3466		T19	258		T56	1509
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1837	1			T15	2		T18	5		T19	4
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	46989	1			T1	256		T7	512		T15	2828
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	962	1			T1	2		T52	694		T18	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	37825	1			T1	763		T18	1		T56	128
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	542	1			T1	3		T7	2		T29	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	68270	1			T1	1352		T7	514		T18	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	199	1			T7	1		T15	9		T18	5
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	50320	1			T7	1		T15	2027		T18	599
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	786	1			T18	1		T19	2		T126	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	40123	1			T7	256		T18	256		T19	2610
auto[1]	auto[0]	auto[0:524287]	auto[0]	283	1			T1	2		T5	4		T7	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	2622	1			T1	20		T5	165		T7	11
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	170	1			T7	2		T29	2		T18	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1280	1			T7	51		T29	6		T18	25
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	168	1			T7	2		T29	4		T18	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1362	1			T7	26		T29	36		T18	9
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	186	1			T7	1		T15	4		T18	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1821	1			T7	27		T15	55		T18	5
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	164	1			T1	4		T18	3		T19	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1355	1			T1	26		T18	38		T19	26
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	175	1			T7	1		T29	1		T46	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1355	1			T7	11		T29	3		T46	5
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	188	1			T1	7		T7	3		T18	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1287	1			T1	10		T7	53		T18	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	175	1			T18	1		T56	1		T155	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1872	1			T18	9		T56	2		T155	17
auto[1]	auto[1]	auto[0:524287]	auto[0]	42	1			T7	1		T15	2		T18	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	331	1			T7	23		T15	1		T18	17
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	45	1			T1	1		T29	1		T177	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	372	1			T1	2		T29	3		T177	6
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	44	1			T7	2		T19	2		T46	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	455	1			T7	14		T19	36		T46	16
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	34	1			T18	2		T19	2		T34	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	324	1			T18	27		T19	2		T34	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	43	1			T1	1		T18	1		T126	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	393	1			T1	7		T126	45		T155	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	41	1			T1	3		T7	2		T19	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	495	1			T1	59		T7	35		T19	78
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	31	1			T7	1		T15	1		T18	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	238	1			T7	8		T18	33		T22	16
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	56	1			T126	1		T54	1		T21	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	506	1			T126	1		T54	4		T162	4

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1596074	1			T1	1147		T2	1		T4	4274
auto[0]	auto[0]	auto[1]	784344	1			T4	9287		T5	3		T7	6
auto[0]	auto[1]	auto[0]	365335	1			T1	2377		T7	5022		T15	4871
auto[0]	auto[1]	auto[1]	7955	1			T1	2		T7	2		T52	699
auto[1]	auto[0]	auto[0]	14157	1			T1	67		T5	169		T7	188
auto[1]	auto[0]	auto[1]	306	1			T1	2		T7	2		T15	2
auto[1]	auto[1]	auto[0]	3381	1			T1	71		T7	84		T15	4
auto[1]	auto[1]	auto[1]	69	1			T1	2		T7	2		T18	2