Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15040

1

T2

18

T4

6

T5

187

auto[1]

11010

1

T7

300

T15

143

T51

12

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3197	1			T15	20		T19	20		T205	6
values[1]	3010	1			T70	4		T19	61		T185	20
values[2]	3576	1			T2	18		T7	41		T15	58
values[3]	3370	1			T4	6		T5	187		T7	104
values[4]	3306	1			T7	122		T39	6		T20	44
values[5]	3164	1			T50	20		T27	14		T37	16
values[6]	3077	1			T7	60		T15	23		T49	18
values[7]	3350	1			T7	149		T9	4		T15	102

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3439	1			T19	20		T46	20		T20	20
values[1]	3043	1			T2	18		T7	121		T9	4
values[2]	2833	1			T52	14		T27	14		T38	2
values[3]	3524	1			T7	45		T15	63		T90	10
values[4]	2782	1			T7	254		T26	12		T215	4
values[5]	3684	1			T5	187		T16	8		T51	12
values[6]	3757	1			T7	56		T15	20		T50	20
values[7]	2988	1			T4	6		T15	100		T70	4

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	299	1			T19	12		T21	13		T66	12
auto[0]	values[0]	values[1]	118	1			T199	12		T190	12		T216	2
auto[0]	values[0]	values[2]	348	1			T21	12		T178	17		T66	142
auto[0]	values[0]	values[3]	181	1			T15	8		T173	14		T175	10
auto[0]	values[0]	values[4]	323	1			T22	17		T41	13		T217	12
auto[0]	values[0]	values[5]	231	1			T205	6		T156	18		T62	14
auto[0]	values[0]	values[6]	253	1			T46	14		T162	14		T195	14
auto[0]	values[0]	values[7]	260	1			T21	18		T197	13		T173	17
auto[0]	values[1]	values[0]	306	1			T22	10		T218	10		T217	12
auto[0]	values[1]	values[1]	248	1			T66	6		T174	14		T210	12
auto[0]	values[1]	values[2]	180	1			T19	27		T127	8		T178	8
auto[0]	values[1]	values[3]	164	1			T195	13		T173	14		T199	11
auto[0]	values[1]	values[4]	192	1			T162	8		T219	16		T179	64
auto[0]	values[1]	values[5]	300	1			T23	6		T213	10		T199	11
auto[0]	values[1]	values[6]	172	1			T185	20		T46	11		T54	27
auto[0]	values[1]	values[7]	187	1			T19	12		T46	13		T184	14
auto[0]	values[2]	values[0]	237	1			T22	13		T64	20		T220	8
auto[0]	values[2]	values[1]	267	1			T2	18		T19	20		T23	18
auto[0]	values[2]	values[2]	204	1			T46	11		T174	70		T184	11
auto[0]	values[2]	values[3]	213	1			T23	9		T221	2		T89	2
auto[0]	values[2]	values[4]	223	1			T7	36		T26	12		T215	4
auto[0]	values[2]	values[5]	325	1			T162	45		T222	6		T190	14
auto[0]	values[2]	values[6]	337	1			T15	6		T46	17		T22	9
auto[0]	values[2]	values[7]	183	1			T15	10		T21	13		T178	9
auto[0]	values[3]	values[0]	425	1			T46	9		T54	22		T21	13
auto[0]	values[3]	values[1]	193	1			T7	14		T20	14		T23	12
auto[0]	values[3]	values[2]	201	1			T46	54		T21	12		T174	9
auto[0]	values[3]	values[3]	307	1			T15	10		T46	14		T20	7
auto[0]	values[3]	values[4]	193	1			T22	12		T174	22		T223	10
auto[0]	values[3]	values[5]	277	1			T5	187		T16	8		T172	24
auto[0]	values[3]	values[6]	106	1			T7	7		T20	16		T224	2
auto[0]	values[3]	values[7]	232	1			T4	6		T20	24		T128	10
auto[0]	values[4]	values[0]	271	1			T20	12		T21	13		T178	10
auto[0]	values[4]	values[1]	219	1			T172	13		T199	9		T225	2
auto[0]	values[4]	values[2]	127	1			T173	18		T226	14		T201	9
auto[0]	values[4]	values[3]	204	1			T7	9		T192	14		T175	10
auto[0]	values[4]	values[4]	214	1			T7	9		T20	21		T54	17
auto[0]	values[4]	values[5]	192	1			T39	6		T162	14		T23	32
auto[0]	values[4]	values[6]	387	1			T7	21		T174	9		T175	8
auto[0]	values[4]	values[7]	178	1			T227	10		T128	27		T228	40
auto[0]	values[5]	values[0]	199	1			T23	17		T66	34		T41	33
auto[0]	values[5]	values[1]	179	1			T37	16		T20	12		T229	6
auto[0]	values[5]	values[2]	363	1			T27	14		T54	15		T21	9
auto[0]	values[5]	values[3]	308	1			T19	13		T20	13		T162	8
auto[0]	values[5]	values[4]	151	1			T22	19		T217	19		T190	18
auto[0]	values[5]	values[5]	244	1			T20	10		T162	8		T66	9
auto[0]	values[5]	values[6]	298	1			T50	20		T46	10		T230	2
auto[0]	values[5]	values[7]	114	1			T231	4		T232	2		T233	8
auto[0]	values[6]	values[0]	214	1			T234	18		T66	8		T195	21
auto[0]	values[6]	values[1]	159	1			T49	18		T23	13		T129	14
auto[0]	values[6]	values[2]	205	1			T52	14		T20	14		T21	33
auto[0]	values[6]	values[3]	222	1			T15	13		T90	10		T19	15
auto[0]	values[6]	values[4]	156	1			T7	11		T235	20		T236	12
auto[0]	values[6]	values[5]	288	1			T21	15		T162	28		T195	10
auto[0]	values[6]	values[6]	291	1			T20	21		T21	22		T23	15
auto[0]	values[6]	values[7]	227	1			T174	11		T195	12		T179	12
auto[0]	values[7]	values[0]	221	1			T21	13		T172	27		T237	8
auto[0]	values[7]	values[1]	366	1			T7	38		T9	4		T15	25
auto[0]	values[7]	values[2]	193	1			T47	33		T184	11		T238	20
auto[0]	values[7]	values[3]	297	1			T7	21		T157	2		T162	31
auto[0]	values[7]	values[4]	112	1			T7	10		T228	13		T239	15
auto[0]	values[7]	values[5]	270	1			T46	16		T179	107		T128	10
auto[0]	values[7]	values[6]	282	1			T35	6		T19	36		T46	10
auto[0]	values[7]	values[7]	204	1			T15	8		T19	16		T54	14
auto[1]	values[0]	values[0]	291	1			T19	8		T21	7		T66	58
auto[1]	values[0]	values[1]	80	1			T199	8		T190	8		T129	8
auto[1]	values[0]	values[2]	117	1			T21	8		T178	7		T66	23
auto[1]	values[0]	values[3]	177	1			T15	12		T173	6		T175	12
auto[1]	values[0]	values[4]	137	1			T22	6		T41	10		T217	8
auto[1]	values[0]	values[5]	110	1			T41	20		T217	17		T175	12
auto[1]	values[0]	values[6]	191	1			T46	45		T162	6		T195	6
auto[1]	values[0]	values[7]	81	1			T21	5		T197	7		T173	3
auto[1]	values[1]	values[0]	168	1			T22	29		T217	23		T201	5
auto[1]	values[1]	values[1]	274	1			T66	111		T174	20		T240	11
auto[1]	values[1]	values[2]	155	1			T19	9		T178	16		T186	8
auto[1]	values[1]	values[3]	140	1			T195	8		T173	11		T199	9
auto[1]	values[1]	values[4]	64	1			T162	17		T179	8		T129	9
auto[1]	values[1]	values[5]	208	1			T23	19		T199	13		T241	6
auto[1]	values[1]	values[6]	125	1			T46	19		T54	14		T173	8
auto[1]	values[1]	values[7]	127	1			T70	4		T19	13		T46	11
auto[1]	values[2]	values[0]	84	1			T22	7		T172	18		T242	14
auto[1]	values[2]	values[1]	269	1			T25	26		T19	31		T23	6
auto[1]	values[2]	values[2]	122	1			T38	2		T46	9		T174	36
auto[1]	values[2]	values[3]	136	1			T23	13		T228	9		T239	10
auto[1]	values[2]	values[4]	171	1			T7	5		T23	7		T195	9
auto[1]	values[2]	values[5]	221	1			T51	12		T162	47		T190	6
auto[1]	values[2]	values[6]	307	1			T15	14		T46	9		T22	11
auto[1]	values[2]	values[7]	277	1			T15	28		T21	8		T178	13
auto[1]	values[3]	values[0]	193	1			T46	11		T54	6		T21	7
auto[1]	values[3]	values[1]	216	1			T7	59		T20	8		T23	8
auto[1]	values[3]	values[2]	141	1			T46	18		T21	13		T174	11
auto[1]	values[3]	values[3]	287	1			T15	10		T46	7		T20	21
auto[1]	values[3]	values[4]	176	1			T22	8		T174	18		T223	15
auto[1]	values[3]	values[5]	142	1			T172	9		T201	29		T228	36
auto[1]	values[3]	values[6]	193	1			T7	24		T20	9		T172	15
auto[1]	values[3]	values[7]	88	1			T20	17		T128	20		T243	10
auto[1]	values[4]	values[0]	199	1			T20	8		T21	18		T178	10
auto[1]	values[4]	values[1]	139	1			T207	18		T172	7		T199	11
auto[1]	values[4]	values[2]	156	1			T244	4		T173	6		T201	11
auto[1]	values[4]	values[3]	352	1			T7	11		T175	13		T190	13
auto[1]	values[4]	values[4]	198	1			T7	68		T20	3		T54	23
auto[1]	values[4]	values[5]	182	1			T162	6		T23	13		T217	12
auto[1]	values[4]	values[6]	148	1			T7	4		T174	11		T175	16
auto[1]	values[4]	values[7]	140	1			T128	5		T228	9		T131	13
auto[1]	values[5]	values[0]	115	1			T23	11		T66	7		T41	14
auto[1]	values[5]	values[1]	90	1			T20	8		T41	10		T128	11
auto[1]	values[5]	values[2]	125	1			T54	21		T21	15		T172	6
auto[1]	values[5]	values[3]	314	1			T19	7		T20	11		T162	12
auto[1]	values[5]	values[4]	189	1			T22	7		T217	1		T190	6
auto[1]	values[5]	values[5]	255	1			T20	15		T162	12		T66	86
auto[1]	values[5]	values[6]	161	1			T46	27		T162	8		T172	17
auto[1]	values[5]	values[7]	59	1			T217	12		T245	14		T59	9
auto[1]	values[6]	values[0]	129	1			T66	12		T195	20		T179	22
auto[1]	values[6]	values[1]	88	1			T23	7		T246	2		T129	7
auto[1]	values[6]	values[2]	98	1			T20	6		T21	11		T22	8
auto[1]	values[6]	values[3]	111	1			T15	10		T19	5		T178	8
auto[1]	values[6]	values[4]	148	1			T7	49		T247	20		T217	5
auto[1]	values[6]	values[5]	209	1			T21	9		T162	8		T195	12
auto[1]	values[6]	values[6]	154	1			T20	9		T21	28		T23	11
auto[1]	values[6]	values[7]	378	1			T174	9		T195	10		T179	59
auto[1]	values[7]	values[0]	88	1			T21	10		T172	13		T202	7
auto[1]	values[7]	values[1]	138	1			T7	10		T15	15		T172	22
auto[1]	values[7]	values[2]	98	1			T184	14		T129	10		T248	9
auto[1]	values[7]	values[3]	111	1			T7	4		T162	4		T174	6
auto[1]	values[7]	values[4]	135	1			T7	66		T53	18		T228	21
auto[1]	values[7]	values[5]	230	1			T46	4		T179	11		T128	10
auto[1]	values[7]	values[6]	352	1			T19	27		T46	10		T178	17
auto[1]	values[7]	values[7]	253	1			T15	54		T19	8		T54	6