Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2691267	1			T1	4593		T2	1		T4	1
all_pins[1]	2691267	1			T1	4593		T2	1		T4	1
all_pins[2]	2691267	1			T1	4593		T2	1		T4	1
all_pins[3]	2691267	1			T1	4593		T2	1		T4	1
all_pins[4]	2691267	1			T1	4593		T2	1		T4	1
all_pins[5]	2691267	1			T1	4593		T2	1		T4	1
all_pins[6]	2691267	1			T1	4593		T2	1		T4	1
all_pins[7]	2691267	1			T1	4593		T2	1		T4	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21377411	1			T1	36744		T2	8		T4	8
values[0x1]	152725	1			T20	11		T22	18		T24	56
transitions[0x0=>0x1]	151408	1			T20	11		T22	15		T24	40
transitions[0x1=>0x0]	151414	1			T20	11		T22	15		T24	40

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2690312	1			T1	4593		T2	1		T4	1
all_pins[0]	values[0x1]	955	1			T20	3		T22	4		T24	3
all_pins[0]	transitions[0x0=>0x1]	531	1			T20	3		T22	4		T33	3
all_pins[0]	transitions[0x1=>0x0]	143	1			T20	2		T22	1		T24	2
all_pins[1]	values[0x0]	2690700	1			T1	4593		T2	1		T4	1
all_pins[1]	values[0x1]	567	1			T20	2		T22	1		T24	5
all_pins[1]	transitions[0x0=>0x1]	461	1			T20	2		T22	1		T24	2
all_pins[1]	transitions[0x1=>0x0]	134	1			T20	1		T22	1		T24	5
all_pins[2]	values[0x0]	2691027	1			T1	4593		T2	1		T4	1
all_pins[2]	values[0x1]	240	1			T20	1		T22	1		T24	8
all_pins[2]	transitions[0x0=>0x1]	204	1			T20	1		T22	1		T24	8
all_pins[2]	transitions[0x1=>0x0]	146	1			T20	3		T22	3		T24	5
all_pins[3]	values[0x0]	2691085	1			T1	4593		T2	1		T4	1
all_pins[3]	values[0x1]	182	1			T20	3		T22	3		T24	5
all_pins[3]	transitions[0x0=>0x1]	139	1			T20	3		T22	2		T24	2
all_pins[3]	transitions[0x1=>0x0]	132	1			T20	1		T22	3		T24	11
all_pins[4]	values[0x0]	2691092	1			T1	4593		T2	1		T4	1
all_pins[4]	values[0x1]	175	1			T20	1		T22	4		T24	14
all_pins[4]	transitions[0x0=>0x1]	145	1			T20	1		T22	4		T24	11
all_pins[4]	transitions[0x1=>0x0]	950	1			T22	1		T24	3		T33	3
all_pins[5]	values[0x0]	2690287	1			T1	4593		T2	1		T4	1
all_pins[5]	values[0x1]	980	1			T22	1		T24	6		T33	3
all_pins[5]	transitions[0x0=>0x1]	411	1			T22	1		T24	5		T33	1
all_pins[5]	transitions[0x1=>0x0]	148865	1			T20	1		T22	2		T24	8
all_pins[6]	values[0x0]	2541833	1			T1	4593		T2	1		T4	1
all_pins[6]	values[0x1]	149434	1			T20	1		T22	2		T24	9
all_pins[6]	transitions[0x0=>0x1]	149379	1			T20	1		T22	1		T24	6
all_pins[6]	transitions[0x1=>0x0]	137	1			T22	1		T24	3		T33	3
all_pins[7]	values[0x0]	2691075	1			T1	4593		T2	1		T4	1
all_pins[7]	values[0x1]	192	1			T22	2		T24	6		T33	3
all_pins[7]	transitions[0x0=>0x1]	138	1			T22	1		T24	6		T33	2
all_pins[7]	transitions[0x1=>0x0]	907	1			T20	3		T22	3		T24	3