Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	346	1			T7	4		T15	2		T50	2
auto[ReadAddrCrossIntoMailbox]	240	1			T7	6		T15	1		T50	2
auto[ReadAddrCrossOutOfMailbox]	257	1			T7	3		T15	3		T50	2
auto[ReadAddrCrossAllMailbox]	157	1			T15	1		T27	2		T20	1
auto[ReadAddrOutsideMailbox]	3109	1			T2	6		T5	8		T7	23

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2085

1

T2

3

T5

4

T7

21

auto[1]

2024

1

T2

3

T5

4

T7

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	654	1			T2	2		T5	2		T7	10
read_ops[0x0b]	722	1			T2	2		T5	2		T7	4
read_ops[0x3b]	705	1			T2	2		T5	2		T7	5
read_ops[0x6b]	678	1			T7	6		T15	4		T50	4
read_ops[0xbb]	681	1			T7	5		T15	8		T50	8
read_ops[0xeb]	669	1			T5	2		T7	6		T15	1

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T19	1		T22	1		T174	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T19	1		T54	1		T23	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T20	1		T21	1		T162	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T7	2		T66	1		T34	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T7	1		T19	1		T20	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T7	1		T20	1		T22	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	8	1			T66	1		T172	1		T245	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T23	1		T41	1		T196	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	248	1			T2	1		T5	1		T7	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	246	1			T2	1		T5	1		T7	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T27	1		T205	1		T233	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T27	1		T19	1		T205	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T7	2		T178	1		T41	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T46	2		T20	1		T21	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T27	1		T46	1		T23	3
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	15	1			T27	1		T19	1		T23	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T21	1		T23	1		T231	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T231	1		T172	1		T249	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	294	1			T2	1		T5	1		T7	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	250	1			T2	1		T5	1		T15	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T205	1		T20	1		T54	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T205	1		T20	2		T21	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T162	1		T184	1		T201	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T7	1		T46	1		T21	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T21	1		T22	1		T23	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	13	1			T66	1		T184	1		T173	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T15	1		T54	1		T178	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T174	1		T201	2		T128	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	271	1			T2	1		T5	1		T7	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	254	1			T2	1		T5	1		T7	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	17	1			T46	1		T22	1		T23	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T7	2		T46	1		T20	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T27	1		T20	1		T217	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T15	1		T27	1		T23	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T27	1		T22	2		T41	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T27	1		T178	2		T23	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T54	1		T23	1		T41	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T66	1		T173	1		T128	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	264	1			T7	3		T50	2		T90	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	259	1			T7	1		T15	3		T50	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T50	1		T37	1		T205	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T15	2		T50	1		T37	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T7	1		T50	1		T20	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	14	1			T50	1		T23	1		T174	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T50	1		T20	1		T22	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T7	1		T15	2		T50	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T27	1		T66	1		T41	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T27	1		T20	1		T66	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	265	1			T7	3		T15	2		T50	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	242	1			T15	2		T50	1		T25	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T7	2		T20	3		T22	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T23	1		T66	1		T173	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T46	2		T66	1		T172	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T46	1		T23	1		T172	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T15	1		T20	1		T21	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T179	2		T186	1		T193	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	7	1			T162	1		T172	1		T175	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T193	1		T250	1		T251	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	234	1			T5	1		T7	3		T90	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	282	1			T5	1		T7	1		T90	1