Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2862	1			T25	26		T39	6		T19	31
values[1]	2778	1			T7	25		T9	4		T15	20
values[2]	3534	1			T7	97		T15	62		T16	8
values[3]	3176	1			T4	6		T7	31		T15	63
values[4]	3313	1			T7	114		T70	4		T19	56
values[5]	3391	1			T7	149		T15	58		T50	20
values[6]	3094	1			T5	187		T7	60		T15	20
values[7]	3902	1			T2	18		T19	44		T46	21

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3738	1			T7	194		T90	10		T70	4
values[1]	3074	1			T2	18		T15	58		T26	12
values[2]	4505	1			T5	187		T9	4		T15	40
values[3]	3126	1			T4	6		T7	133		T15	62
values[4]	3000	1			T27	14		T47	33		T19	25
values[5]	2852	1			T50	20		T25	26		T19	20
values[6]	2633	1			T15	63		T49	18		T35	6
values[7]	3122	1			T7	149		T16	8		T19	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25410

1

T2

18

T4

6

T5

187

auto[1]

640

1

T7

14

T15

5

T51

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	378	1			T162	52		T66	20		T174	20
auto[0]	values[0]	values[1]	420	1			T221	2		T172	25		T202	23
auto[0]	values[0]	values[2]	520	1			T162	36		T235	20		T66	41
auto[0]	values[0]	values[3]	252	1			T23	20		T182	14		T212	10
auto[0]	values[0]	values[4]	261	1			T162	25		T23	24		T252	14
auto[0]	values[0]	values[5]	324	1			T25	26		T162	18		T253	8
auto[0]	values[0]	values[6]	264	1			T39	6		T19	30		T21	24
auto[0]	values[0]	values[7]	386	1			T157	2		T21	20		T34	24
auto[0]	values[1]	values[0]	355	1			T54	39		T178	21		T254	23
auto[0]	values[1]	values[1]	436	1			T46	20		T187	14		T41	23
auto[0]	values[1]	values[2]	452	1			T9	4		T15	20		T52	14
auto[0]	values[1]	values[3]	289	1			T7	25		T19	20		T46	19
auto[0]	values[1]	values[4]	463	1			T27	14		T19	24		T178	20
auto[0]	values[1]	values[5]	240	1			T172	20		T217	35		T190	27
auto[0]	values[1]	values[6]	193	1			T49	18		T20	20		T213	10
auto[0]	values[1]	values[7]	271	1			T215	4		T66	18		T176	8
auto[0]	values[2]	values[0]	804	1			T7	20		T90	10		T20	26
auto[0]	values[2]	values[1]	490	1			T53	14		T162	19		T23	53
auto[0]	values[2]	values[2]	455	1			T174	58		T195	20		T175	22
auto[0]	values[2]	values[3]	542	1			T7	75		T15	62		T19	20
auto[0]	values[2]	values[4]	281	1			T46	20		T21	41		T174	20
auto[0]	values[2]	values[5]	301	1			T21	28		T66	20		T255	26
auto[0]	values[2]	values[6]	267	1			T19	43		T23	19		T194	12
auto[0]	values[2]	values[7]	295	1			T16	8		T22	19		T195	20
auto[0]	values[3]	values[0]	327	1			T173	19		T219	16		T201	26
auto[0]	values[3]	values[1]	462	1			T15	20		T173	40		T217	19
auto[0]	values[3]	values[2]	687	1			T20	20		T54	36		T23	22
auto[0]	values[3]	values[3]	305	1			T4	6		T7	29		T51	10
auto[0]	values[3]	values[4]	338	1			T47	33		T46	18		T20	25
auto[0]	values[3]	values[5]	337	1			T172	18		T237	8		T184	32
auto[0]	values[3]	values[6]	366	1			T15	42		T46	26		T20	20
auto[0]	values[3]	values[7]	278	1			T174	20		T217	24		T256	52
auto[0]	values[4]	values[0]	493	1			T7	72		T70	4		T169	12
auto[0]	values[4]	values[1]	232	1			T46	58		T128	20		T171	26
auto[0]	values[4]	values[2]	513	1			T20	20		T234	18		T66	134
auto[0]	values[4]	values[3]	365	1			T19	34		T192	14		T41	20
auto[0]	values[4]	values[4]	319	1			T21	23		T162	24		T23	20
auto[0]	values[4]	values[5]	402	1			T19	20		T20	21		T173	32
auto[0]	values[4]	values[6]	514	1			T162	46		T172	20		T175	21
auto[0]	values[4]	values[7]	401	1			T7	41		T21	23		T162	24
auto[0]	values[5]	values[0]	411	1			T7	97		T23	41		T224	2
auto[0]	values[5]	values[1]	401	1			T15	37		T54	20		T22	56
auto[0]	values[5]	values[2]	573	1			T66	68		T174	20		T232	2
auto[0]	values[5]	values[3]	320	1			T23	20		T195	20		T227	10
auto[0]	values[5]	values[4]	284	1			T64	20		T66	24		T175	22
auto[0]	values[5]	values[5]	409	1			T50	20		T46	29		T54	36
auto[0]	values[5]	values[6]	320	1			T15	18		T38	2		T41	23
auto[0]	values[5]	values[7]	595	1			T7	46		T19	20		T46	52
auto[0]	values[6]	values[0]	374	1			T37	16		T20	27		T21	20
auto[0]	values[6]	values[1]	244	1			T26	12		T21	24		T178	23
auto[0]	values[6]	values[2]	722	1			T5	187		T15	19		T46	24
auto[0]	values[6]	values[3]	398	1			T20	20		T195	19		T257	6
auto[0]	values[6]	values[4]	138	1			T23	20		T179	28		T258	20
auto[0]	values[6]	values[5]	373	1			T46	20		T207	18		T66	40
auto[0]	values[6]	values[6]	333	1			T35	6		T205	6		T127	8
auto[0]	values[6]	values[7]	444	1			T7	57		T21	21		T201	60
auto[0]	values[7]	values[0]	482	1			T19	23		T46	20		T21	31
auto[0]	values[7]	values[1]	329	1			T2	18		T21	25		T22	26
auto[0]	values[7]	values[2]	479	1			T66	69		T217	27		T201	17
auto[0]	values[7]	values[3]	572	1			T20	24		T178	26		T174	46
auto[0]	values[7]	values[4]	851	1			T20	22		T22	20		T172	28
auto[0]	values[7]	values[5]	399	1			T22	20		T162	20		T195	26
auto[0]	values[7]	values[6]	310	1			T19	20		T156	18		T21	20
auto[0]	values[7]	values[7]	371	1			T20	25		T162	40		T184	19
auto[1]	values[0]	values[0]	16	1			T162	3		T195	1		T41	1
auto[1]	values[0]	values[1]	6	1			T59	1		T259	1		T198	1
auto[1]	values[0]	values[2]	3	1			T66	1		T260	1		T171	1
auto[1]	values[0]	values[3]	4	1			T131	1		T261	3		-	-
auto[1]	values[0]	values[4]	9	1			T23	2		T193	1		T258	1
auto[1]	values[0]	values[5]	10	1			T162	2		T253	2		T206	1
auto[1]	values[0]	values[6]	6	1			T19	1		T173	2		T198	1
auto[1]	values[0]	values[7]	3	1			T201	1		T262	1		T263	1
auto[1]	values[1]	values[0]	10	1			T54	2		T178	1		T254	1
auto[1]	values[1]	values[1]	7	1			T41	1		T217	1		T179	4
auto[1]	values[1]	values[2]	13	1			T54	3		T129	2		T262	1
auto[1]	values[1]	values[3]	11	1			T46	1		T264	5		T265	2
auto[1]	values[1]	values[4]	16	1			T19	1		T41	2		T175	3
auto[1]	values[1]	values[5]	2	1			T217	2		-	-		-	-
auto[1]	values[1]	values[6]	7	1			T20	1		T128	2		T129	2
auto[1]	values[1]	values[7]	13	1			T66	2		T172	1		T266	8
auto[1]	values[2]	values[0]	25	1			T20	2		T244	2		T66	1
auto[1]	values[2]	values[1]	16	1			T53	4		T162	1		T217	2
auto[1]	values[2]	values[2]	11	1			T195	1		T179	2		T186	2
auto[1]	values[2]	values[3]	14	1			T7	2		T179	2		T258	2
auto[1]	values[2]	values[4]	3	1			T34	1		T175	1		T262	1
auto[1]	values[2]	values[5]	8	1			T172	1		T190	1		T132	4
auto[1]	values[2]	values[6]	10	1			T23	1		T190	4		T267	4
auto[1]	values[2]	values[7]	12	1			T22	1		T184	1		T247	4
auto[1]	values[3]	values[0]	17	1			T173	1		T201	3		T128	3
auto[1]	values[3]	values[1]	8	1			T217	2		T268	2		T269	1
auto[1]	values[3]	values[2]	11	1			T23	2		T66	2		T199	2
auto[1]	values[3]	values[3]	13	1			T7	2		T51	2		T46	1
auto[1]	values[3]	values[4]	6	1			T46	2		T41	2		T129	2
auto[1]	values[3]	values[5]	8	1			T172	2		T199	1		T245	1
auto[1]	values[3]	values[6]	7	1			T15	1		T22	1		T228	2
auto[1]	values[3]	values[7]	6	1			T217	1		T201	2		T129	1
auto[1]	values[4]	values[0]	13	1			T7	1		T129	2		T239	3
auto[1]	values[4]	values[1]	2	1			T46	1		T265	1		-	-
auto[1]	values[4]	values[2]	12	1			T66	3		T172	1		T199	1
auto[1]	values[4]	values[3]	9	1			T19	2		T184	3		T269	1
auto[1]	values[4]	values[4]	6	1			T162	1		T195	2		T41	2
auto[1]	values[4]	values[5]	6	1			T20	1		T173	1		T270	1
auto[1]	values[4]	values[6]	14	1			T162	1		T175	4		T271	2
auto[1]	values[4]	values[7]	12	1			T162	1		T172	1		T198	5
auto[1]	values[5]	values[0]	12	1			T7	4		T23	1		T245	1
auto[1]	values[5]	values[1]	9	1			T15	1		T22	3		T240	2
auto[1]	values[5]	values[2]	13	1			T66	2		T129	1		T171	3
auto[1]	values[5]	values[3]	6	1			T59	3		T193	1		T130	2
auto[1]	values[5]	values[4]	9	1			T198	1		T228	2		T132	2
auto[1]	values[5]	values[5]	12	1			T46	1		T54	4		T23	2
auto[1]	values[5]	values[6]	4	1			T15	2		T272	2		-	-
auto[1]	values[5]	values[7]	13	1			T7	2		T171	5		T273	1
auto[1]	values[6]	values[0]	12	1			T20	3		T21	2		T184	3
auto[1]	values[6]	values[1]	3	1			T178	1		T274	2		-	-
auto[1]	values[6]	values[2]	14	1			T15	1		T173	1		T186	1
auto[1]	values[6]	values[3]	5	1			T195	2		T241	1		T275	1
auto[1]	values[6]	values[4]	2	1			T270	1		T263	1		-	-
auto[1]	values[6]	values[5]	7	1			T66	1		T41	1		T276	2
auto[1]	values[6]	values[6]	12	1			T34	1		T59	1		T129	1
auto[1]	values[6]	values[7]	13	1			T7	3		T21	3		T201	1
auto[1]	values[7]	values[0]	9	1			T19	1		T46	1		T258	1
auto[1]	values[7]	values[1]	9	1			T34	1		T245	4		T59	1
auto[1]	values[7]	values[2]	27	1			T217	2		T201	3		T193	5
auto[1]	values[7]	values[3]	21	1			T178	2		T174	2		T197	1
auto[1]	values[7]	values[4]	14	1			T20	2		T172	2		T179	5
auto[1]	values[7]	values[5]	14	1			T22	3		T175	3		T240	2
auto[1]	values[7]	values[6]	6	1			T217	3		T193	1		T275	1
auto[1]	values[7]	values[7]	9	1			T162	3		T184	1		T277	2