Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1682

1

T1

2

T6

7

T12

8

auto[1]

1733

1

T6

13

T12

5

T13

5

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1882

1

T1

2

T15

1

T29

6

auto[1]

1533

1

T6

20

T12

13

T13

15

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2684

1

T1

2

T6

20

T12

13

auto[1]

731

1

T29

2

T18

2

T19

10

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	675	1			T1	2		T6	2		T12	2
valid[1]	698	1			T6	4		T12	3		T13	6
valid[2]	651	1			T6	2		T12	2		T13	4
valid[3]	700	1			T6	4		T12	2		T13	2
valid[4]	691	1			T6	8		T12	4		T13	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	119	1			T1	2		T18	1		T19	2
auto[0]	auto[0]	valid[0]	auto[1]	147	1			T6	1		T12	2		T13	1
auto[0]	auto[0]	valid[1]	auto[0]	131	1			T15	1		T55	3		T20	2
auto[0]	auto[0]	valid[1]	auto[1]	144	1			T6	2		T12	2		T13	4
auto[0]	auto[0]	valid[2]	auto[0]	103	1			T56	2		T21	1		T40	1
auto[0]	auto[0]	valid[2]	auto[1]	138	1			T6	1		T12	1		T13	1
auto[0]	auto[0]	valid[3]	auto[0]	121	1			T55	1		T20	5		T21	2
auto[0]	auto[0]	valid[3]	auto[1]	145	1			T6	1		T12	1		T13	2
auto[0]	auto[0]	valid[4]	auto[0]	114	1			T18	1		T19	1		T55	3
auto[0]	auto[0]	valid[4]	auto[1]	140	1			T6	2		T12	2		T13	2
auto[0]	auto[1]	valid[0]	auto[0]	101	1			T29	1		T19	1		T57	1
auto[0]	auto[1]	valid[0]	auto[1]	170	1			T6	1		T28	1		T83	2
auto[0]	auto[1]	valid[1]	auto[0]	125	1			T29	1		T19	2		T55	2
auto[0]	auto[1]	valid[1]	auto[1]	164	1			T6	2		T12	1		T13	2
auto[0]	auto[1]	valid[2]	auto[0]	113	1			T19	1		T20	4		T21	1
auto[0]	auto[1]	valid[2]	auto[1]	148	1			T6	1		T12	1		T13	3
auto[0]	auto[1]	valid[3]	auto[0]	117	1			T29	2		T55	1		T56	2
auto[0]	auto[1]	valid[3]	auto[1]	162	1			T6	3		T12	1		T83	2
auto[0]	auto[1]	valid[4]	auto[0]	107	1			T18	1		T19	2		T56	1
auto[0]	auto[1]	valid[4]	auto[1]	175	1			T6	6		T12	2		T85	4
auto[1]	auto[0]	valid[0]	auto[0]	68	1			T29	1		T19	2		T20	1
auto[1]	auto[0]	valid[1]	auto[0]	73	1			T19	1		T57	3		T20	1
auto[1]	auto[0]	valid[2]	auto[0]	80	1			T55	1		T57	1		T20	1
auto[1]	auto[0]	valid[3]	auto[0]	81	1			T29	1		T19	2		T55	1
auto[1]	auto[0]	valid[4]	auto[0]	78	1			T18	1		T55	1		T57	2
auto[1]	auto[1]	valid[0]	auto[0]	70	1			T19	1		T57	3		T20	1
auto[1]	auto[1]	valid[1]	auto[0]	61	1			T19	1		T56	1		T57	2
auto[1]	auto[1]	valid[2]	auto[0]	69	1			T19	1		T56	2		T20	1
auto[1]	auto[1]	valid[3]	auto[0]	74	1			T19	1		T57	1		T289	1
auto[1]	auto[1]	valid[4]	auto[0]	77	1			T18	1		T19	1		T55	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal