Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	829	1			T20	7		T22	10		T24	25
all_values[1]	829	1			T20	7		T22	10		T24	25
all_values[2]	829	1			T20	7		T22	10		T24	25
all_values[3]	829	1			T20	7		T22	10		T24	25
all_values[4]	829	1			T20	7		T22	10		T24	25
all_values[5]	829	1			T20	7		T22	10		T24	25
all_values[6]	829	1			T20	7		T22	10		T24	25
all_values[7]	829	1			T20	7		T22	10		T24	25

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3684

1

T20

21

T22

46

T24

90

auto[1]

2948

1

T20

35

T22

34

T24

110

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2630

1

T20

29

T22

30

T24

80

auto[1]

4002

1

T20

27

T22

50

T24

120

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3773

1

T20

34

T22

46

T24

120

auto[1]

2859

1

T20

22

T22

34

T24

80

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	178	1			T22	1		T24	8		T33	5
all_values[0]	auto[0]	auto[0]	auto[1]	73	1			T20	1		T24	2		T34	4
all_values[0]	auto[0]	auto[1]	auto[0]	134	1			T20	1		T22	1		T24	4
all_values[0]	auto[0]	auto[1]	auto[1]	96	1			T20	1		T22	2		T24	1
all_values[0]	auto[1]	auto[0]	auto[1]	200	1			T20	1		T22	2		T24	8
all_values[0]	auto[1]	auto[1]	auto[1]	148	1			T20	3		T22	4		T24	2
all_values[1]	auto[0]	auto[0]	auto[0]	162	1			T20	1		T22	3		T24	2
all_values[1]	auto[0]	auto[0]	auto[1]	98	1			T22	2		T24	2		T33	1
all_values[1]	auto[0]	auto[1]	auto[0]	132	1			T20	2		T22	1		T24	7
all_values[1]	auto[0]	auto[1]	auto[1]	74	1			T24	1		T33	2		T160	2
all_values[1]	auto[1]	auto[0]	auto[1]	202	1			T22	2		T24	2		T33	2
all_values[1]	auto[1]	auto[1]	auto[1]	161	1			T20	4		T22	2		T24	11
all_values[2]	auto[0]	auto[0]	auto[0]	180	1			T20	4		T22	2		T24	6
all_values[2]	auto[0]	auto[0]	auto[1]	81	1			T24	2		T33	2		T160	1
all_values[2]	auto[0]	auto[1]	auto[0]	125	1			T20	1		T22	5		T24	4
all_values[2]	auto[0]	auto[1]	auto[1]	81	1			T22	2		T24	4		T33	2
all_values[2]	auto[1]	auto[0]	auto[1]	214	1			T20	1		T24	2		T33	4
all_values[2]	auto[1]	auto[1]	auto[1]	148	1			T20	1		T22	1		T24	7
all_values[3]	auto[0]	auto[0]	auto[0]	190	1			T20	1		T22	1		T24	5
all_values[3]	auto[0]	auto[0]	auto[1]	77	1			T20	1		T22	2		T24	1
all_values[3]	auto[0]	auto[1]	auto[0]	150	1			T20	1		T22	1		T24	7
all_values[3]	auto[0]	auto[1]	auto[1]	67	1			T20	1		T24	3		T33	2
all_values[3]	auto[1]	auto[0]	auto[1]	196	1			T20	1		T22	3		T24	5
all_values[3]	auto[1]	auto[1]	auto[1]	149	1			T20	2		T22	3		T24	4
all_values[4]	auto[0]	auto[0]	auto[0]	177	1			T20	2		T22	2		T24	2
all_values[4]	auto[0]	auto[0]	auto[1]	87	1			T22	1		T24	3		T33	2
all_values[4]	auto[0]	auto[1]	auto[0]	140	1			T20	3		T22	1		T24	2
all_values[4]	auto[0]	auto[1]	auto[1]	68	1			T20	1		T22	1		T24	6
all_values[4]	auto[1]	auto[0]	auto[1]	203	1			T22	1		T24	3		T33	4
all_values[4]	auto[1]	auto[1]	auto[1]	154	1			T20	1		T22	4		T24	9
all_values[5]	auto[0]	auto[0]	auto[0]	255	1			T20	3		T22	6		T24	6
all_values[5]	auto[0]	auto[1]	auto[0]	215	1			T20	3		T22	2		T24	7
all_values[5]	auto[1]	auto[0]	auto[1]	208	1			T20	1		T24	6		T33	2
all_values[5]	auto[1]	auto[1]	auto[1]	151	1			T22	2		T24	6		T33	3
all_values[6]	auto[0]	auto[0]	auto[0]	150	1			T22	2		T24	5		T33	1
all_values[6]	auto[0]	auto[0]	auto[1]	88	1			T22	2		T24	2		T33	1
all_values[6]	auto[0]	auto[1]	auto[0]	141	1			T20	2		T24	5		T33	4
all_values[6]	auto[0]	auto[1]	auto[1]	77	1			T24	5		T33	3		T161	3
all_values[6]	auto[1]	auto[0]	auto[1]	221	1			T20	1		T22	5		T24	2
all_values[6]	auto[1]	auto[1]	auto[1]	152	1			T20	4		T22	1		T24	6
all_values[7]	auto[0]	auto[0]	auto[0]	158	1			T20	2		T22	1		T24	8
all_values[7]	auto[0]	auto[0]	auto[1]	97	1			T22	4		T24	5		T33	1
all_values[7]	auto[0]	auto[1]	auto[0]	143	1			T20	3		T22	1		T24	2
all_values[7]	auto[0]	auto[1]	auto[1]	79	1			T24	3		T33	1		T34	3
all_values[7]	auto[1]	auto[0]	auto[1]	189	1			T20	1		T22	4		T24	3
all_values[7]	auto[1]	auto[1]	auto[1]	163	1			T20	1		T24	4		T33	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal