Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47361

1

T1

68

T32

1

T15

40

auto[1]

16440

1

T6

231

T12

13

T13

169

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46659

1

T1

46

T6

231

T12

13

auto[1]

17142

1

T1

22

T32

1

T15

10

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32931	1			T1	33		T6	118		T12	13
others[1]	5262	1			T1	7		T6	20		T13	12
others[2]	5421	1			T1	5		T6	15		T13	13
others[3]	6152	1			T1	7		T6	28		T13	20
interest[1]	3539	1			T1	4		T6	16		T13	9
interest[4]	21497	1			T1	23		T6	60		T12	13
interest[64]	10496	1			T1	12		T6	34		T13	32

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15570	1			T1	22		T15	9		T29	52
auto[0]	auto[0]	others[1]	2431	1			T1	3		T15	4		T29	9
auto[0]	auto[0]	others[2]	2593	1			T1	3		T15	6		T29	6
auto[0]	auto[0]	others[3]	2991	1			T1	6		T15	4		T29	8
auto[0]	auto[0]	interest[1]	1655	1			T1	3		T29	3		T18	6
auto[0]	auto[0]	interest[4]	10156	1			T1	15		T15	6		T29	35
auto[0]	auto[0]	interest[64]	4979	1			T1	9		T15	7		T29	17
auto[0]	auto[1]	others[0]	8549	1			T6	118		T12	13		T13	83
auto[0]	auto[1]	others[1]	1417	1			T6	20		T13	12		T29	1
auto[0]	auto[1]	others[2]	1325	1			T6	15		T13	13		T57	9
auto[0]	auto[1]	others[3]	1559	1			T6	28		T13	20		T15	1
auto[0]	auto[1]	interest[1]	896	1			T6	16		T13	9		T29	1
auto[0]	auto[1]	interest[4]	5647	1			T6	60		T12	13		T13	55
auto[0]	auto[1]	interest[64]	2694	1			T6	34		T13	32		T15	2
auto[1]	auto[0]	others[0]	8812	1			T1	11		T15	8		T29	32
auto[1]	auto[0]	others[1]	1414	1			T1	4		T29	3		T18	4
auto[1]	auto[0]	others[2]	1503	1			T1	2		T15	1		T29	8
auto[1]	auto[0]	others[3]	1602	1			T1	1		T29	2		T18	6
auto[1]	auto[0]	interest[1]	988	1			T1	1		T29	2		T18	2
auto[1]	auto[0]	interest[4]	5694	1			T1	8		T15	3		T29	20
auto[1]	auto[0]	interest[64]	2823	1			T1	3		T32	1		T15	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal