Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2866217	1			T1	1		T2	10648		T3	1
all_values[1]	2866217	1			T1	1		T2	10648		T3	1
all_values[2]	2866217	1			T1	1		T2	10648		T3	1
all_values[3]	2866217	1			T1	1		T2	10648		T3	1
all_values[4]	2866217	1			T1	1		T2	10648		T3	1
all_values[5]	2866217	1			T1	1		T2	10648		T3	1
all_values[6]	2866217	1			T1	1		T2	10648		T3	1
all_values[7]	2866217	1			T1	1		T2	10648		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22782741

1

T1

8

T2

85184

T3

8

auto[1]

146995

1

T14

39

T18

125

T19

111

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22902250

1

T1

8

T2

85184

T3

8

auto[1]

27486

1

T13

356

T14

307

T15

9

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2838804	1			T1	1		T2	10648		T3	1
all_values[0]	auto[0]	auto[1]	12821	1			T13	192		T14	126		T15	9
all_values[0]	auto[1]	auto[0]	14136	1			T14	3		T18	14		T19	11
all_values[0]	auto[1]	auto[1]	456	1			T14	1		T18	4		T19	2
all_values[1]	auto[0]	auto[0]	2835681	1			T1	1		T2	10648		T3	1
all_values[1]	auto[0]	auto[1]	8286	1			T13	94		T14	122		T32	95
all_values[1]	auto[1]	auto[0]	21823	1			T14	1		T18	4		T19	7
all_values[1]	auto[1]	auto[1]	427	1			T14	5		T18	8		T19	4
all_values[2]	auto[0]	auto[0]	2845461	1			T1	1		T2	10648		T3	1
all_values[2]	auto[0]	auto[1]	3340	1			T13	70		T14	43		T32	8
all_values[2]	auto[1]	auto[0]	17203	1			T14	7		T18	10		T19	7
all_values[2]	auto[1]	auto[1]	213	1			T18	4		T19	3		T20	2
all_values[3]	auto[0]	auto[0]	2839870	1			T1	1		T2	10648		T3	1
all_values[3]	auto[0]	auto[1]	190	1			T14	1		T18	6		T19	6
all_values[3]	auto[1]	auto[0]	25976	1			T18	10		T19	6		T20	7
all_values[3]	auto[1]	auto[1]	181	1			T14	4		T18	7		T19	8
all_values[4]	auto[0]	auto[0]	2856259	1			T1	1		T2	10648		T3	1
all_values[4]	auto[0]	auto[1]	226	1			T18	9		T19	6		T173	1
all_values[4]	auto[1]	auto[0]	9543	1			T14	2		T18	8		T19	13
all_values[4]	auto[1]	auto[1]	189	1			T18	4		T19	5		T20	2
all_values[5]	auto[0]	auto[0]	2849568	1			T1	1		T2	10648		T3	1
all_values[5]	auto[0]	auto[1]	186	1			T14	1		T18	6		T19	4
all_values[5]	auto[1]	auto[0]	16286	1			T14	6		T18	8		T19	7
all_values[5]	auto[1]	auto[1]	177	1			T18	10		T19	5		T20	4
all_values[6]	auto[0]	auto[0]	2844930	1			T1	1		T2	10648		T3	1
all_values[6]	auto[0]	auto[1]	195	1			T14	1		T18	3		T19	4
all_values[6]	auto[1]	auto[0]	20891	1			T14	3		T18	13		T19	8
all_values[6]	auto[1]	auto[1]	201	1			T14	3		T18	3		T19	7
all_values[7]	auto[0]	auto[0]	2846736	1			T1	1		T2	10648		T3	1
all_values[7]	auto[0]	auto[1]	188	1			T18	5		T19	5		T20	3
all_values[7]	auto[1]	auto[0]	19083	1			T14	4		T18	10		T19	13
all_values[7]	auto[1]	auto[1]	210	1			T18	8		T19	5		T20	4