Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	32474	1			T2	258		T3	6		T7	140
auto[SpiFlashAddrCfg]	6400	1			T2	67		T3	2		T7	24
auto[SpiFlashAddr3b]	7799	1			T2	57		T3	6		T7	27
auto[SpiFlashAddr4b]	6546	1			T2	46		T3	6		T7	20

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30845

1

T2

221

T3

20

T7

139

auto[1]

22374

1

T2

207

T7

72

T11

9

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29042

1

T2

263

T3

12

T7

81

auto[1]

24177

1

T2

165

T3

8

T7

130

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	36312	1			T2	288		T3	4		T7	149
values[1]	949	1			T2	10		T7	6		T12	6
values[2]	1225	1			T2	6		T3	4		T7	5
values[3]	1295	1			T2	13		T3	6		T7	1
values[4]	1317	1			T2	9		T7	3		T12	2
values[5]	1328	1			T2	11		T7	4		T13	8
values[6]	1240	1			T2	16		T3	4		T7	2
values[7]	1263	1			T2	13		T7	1		T13	12
values[8]	8290	1			T2	62		T3	2		T7	40

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28248

1

T2

428

T3

20

T11

27

auto[1]

24971

1

T7

211

T10

4

T15

22

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

50518

1

T2

409

T3

18

T7

201

write

2701

1

T2

19

T3

2

T7

10

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

16409

1

T2

128

T3

8

T7

64

valids[0x1]

36810

1

T2

300

T3

12

T7

147

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1322	1			T2	11		T7	9		T11	2
internal_process_ops[0x5a]	1370	1			T2	9		T7	5		T11	2
internal_process_ops[0x05]	20619	1			T2	179		T3	2		T7	81
internal_process_ops[0x35]	1305	1			T2	9		T7	6		T13	11
internal_process_ops[0x15]	1333	1			T2	12		T7	5		T13	7
internal_process_ops[0x03]	887	1			T2	7		T10	3		T13	8
internal_process_ops[0x0b]	960	1			T2	13		T3	4		T10	1
internal_process_ops[0x3b]	902	1			T2	9		T3	4		T12	2
internal_process_ops[0x6b]	910	1			T2	10		T3	2		T7	1
internal_process_ops[0xbb]	847	1			T2	10		T11	1		T13	5
internal_process_ops[0xeb]	886	1			T2	9		T7	1		T13	6

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51908

1

T2

419

T3

20

T7

206

auto[1]

1311

1

T2

9

T7

5

T11

1

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51180

1

T2

412

T3

20

T7

204

auto[1]

2039

1

T2

16

T7

7

T11

1

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9580

1

T2

133

T3

6

T11

13

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6251

1

T2

121

T13

54

T14

29

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1810

1

T2

32

T3

2

T11

3

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1594

1

T2

32

T13

16

T14

18

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2220

1

T2

21

T3

4

T12

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1912

1

T2

31

T11

6

T13

25

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1873

1

T2

24

T3

6

T11

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1601

1

T2

15

T11

2

T13

9

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

82

1

T2

1

T13

1

T14

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

103

1

T2

1

T13

3

T14

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

71

1

T2

1

T47

2

T48

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

97

1

T2

1

T11

1

T14

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

131

1

T2

2

T14

6

T165

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

59

1

T2

1

T13

1

T166

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

71

1

T13

3

T14

2

T47

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

105

1

T13

4

T166

1

T167

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

103

1

T2

2

T3

2

T166

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

65

1

T2

1

T13

3

T47

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

98

1

T2

2

T13

5

T14

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

75

1

T47

1

T48

2

T41

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

136

1

T2

1

T14

2

T47

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

64

1

T2

2

T14

1

T41

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

58

1

T2

1

T14

1

T168

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

89

1

T2

3

T13

2

T14

3

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10122

1

T7

97

T15

13

T32

122

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5823

1

T7

41

T15

3

T32

51

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1180

1

T7

15

T10

4

T32

21

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1149

1

T7

6

T15

2

T32

21

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1521

1

T7

13

T32

25

T44

12

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1494

1

T7

11

T32

23

T44

25

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1211

1

T7

8

T15

2

T32

14

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1177

1

T7

10

T15

2

T32

27

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

64

1

T32

2

T70

1

T169

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

92

1

T7

1

T32

1

T44

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

82

1

T32

4

T68

3

T170

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

107

1

T7

1

T32

3

T44

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

66

1

T7

3

T44

2

T170

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

60

1

T32

1

T68

1

T69

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

90

1

T32

1

T44

2

T68

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

85

1

T32

2

T44

2

T170

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

72

1

T44

1

T68

2

T69

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

69

1

T44

1

T68

3

T171

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

84

1

T32

3

T68

1

T171

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

86

1

T7

3

T44

2

T171

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

87

1

T7

2

T32

1

T171

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

75

1

T32

1

T171

1

T170

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

95

1

T68

2

T170

1

T69

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

80

1

T44

4

T69

1

T172

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3391	1			T2	44		T11	3		T13	55
auto[0]	values[0]	valids[0x1]	14949	1			T2	244		T3	4		T11	12
auto[0]	values[1]	valids[0x1]	529	1			T2	10		T12	6		T13	3
auto[0]	values[2]	valids[0x0]	436	1			T2	3		T13	1		T14	5
auto[0]	values[2]	valids[0x1]	284	1			T2	3		T3	4		T13	1
auto[0]	values[3]	valids[0x0]	496	1			T2	10		T3	6		T11	2
auto[0]	values[3]	valids[0x1]	255	1			T2	3		T13	1		T14	1
auto[0]	values[4]	valids[0x0]	471	1			T2	8		T12	2		T13	2
auto[0]	values[4]	valids[0x1]	295	1			T2	1		T13	5		T35	2
auto[0]	values[5]	valids[0x0]	518	1			T2	9		T13	5		T14	6
auto[0]	values[5]	valids[0x1]	257	1			T2	2		T13	3		T35	1
auto[0]	values[6]	valids[0x0]	454	1			T2	9		T13	2		T14	4
auto[0]	values[6]	valids[0x1]	298	1			T2	7		T3	4		T13	6
auto[0]	values[7]	valids[0x0]	470	1			T2	10		T13	7		T14	4
auto[0]	values[7]	valids[0x1]	282	1			T2	3		T13	5		T35	4
auto[0]	values[8]	valids[0x0]	3075	1			T2	35		T3	2		T11	7
auto[0]	values[8]	valids[0x1]	1788	1			T2	27		T11	3		T13	15
auto[1]	values[0]	valids[0x0]	3243	1			T7	34		T15	8		T32	51
auto[1]	values[0]	valids[0x1]	14729	1			T7	115		T15	7		T32	159
auto[1]	values[1]	valids[0x1]	420	1			T7	6		T32	2		T44	5
auto[1]	values[2]	valids[0x0]	304	1			T7	3		T32	5		T44	9
auto[1]	values[2]	valids[0x1]	201	1			T7	2		T32	3		T44	6
auto[1]	values[3]	valids[0x0]	313	1			T7	1		T32	5		T44	2
auto[1]	values[3]	valids[0x1]	231	1			T10	3		T32	3		T44	3
auto[1]	values[4]	valids[0x0]	335	1			T7	1		T32	6		T44	4
auto[1]	values[4]	valids[0x1]	216	1			T7	2		T32	7		T44	3
auto[1]	values[5]	valids[0x0]	307	1			T7	1		T32	9		T44	1
auto[1]	values[5]	valids[0x1]	246	1			T7	3		T15	1		T44	2
auto[1]	values[6]	valids[0x0]	292	1			T32	4		T44	1		T45	2
auto[1]	values[6]	valids[0x1]	196	1			T7	2		T32	2		T44	2
auto[1]	values[7]	valids[0x0]	297	1			T7	1		T15	1		T32	6
auto[1]	values[7]	valids[0x1]	214	1			T32	3		T44	4		T68	3
auto[1]	values[8]	valids[0x0]	2007	1			T7	23		T15	3		T32	29
auto[1]	values[8]	valids[0x1]	1420	1			T7	17		T10	1		T15	2