Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3064316

1

T2

19314

T3

1

T4

1

auto[1]

19237

1

T2

168

T7

71

T11

7

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

963250

1

T2

80

T3

1

T4

1

auto[1]

2120303

1

T2

19402

T7

8443

T11

136

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	635173	1			T2	3510		T3	1		T4	1
auto[524288:1048575]	319849	1			T2	4304		T7	263		T10	4
auto[1048576:1572863]	350030	1			T2	4967		T7	27		T13	151
auto[1572864:2097151]	346056	1			T2	258		T10	146		T13	5365
auto[2097152:2621439]	324089	1			T2	2656		T7	1		T11	139
auto[2621440:3145727]	387298	1			T2	3723		T7	695		T11	3
auto[3145728:3670015]	409103	1			T2	36		T7	3664		T13	296
auto[3670016:4194303]	311955	1			T2	28		T7	2750		T10	85

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2139140

1

T2

19467

T3

1

T4

1

auto[1]

944413

1

T2

15

T7

5

T10

396

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2633293

1

T2

18778

T3

1

T4

1

auto[1]

450260

1

T2

704

T7

2328

T13

1499

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	227790	1			T2	5		T3	1		T4	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	338735	1			T2	3097		T7	1028		T13	3195
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	82445	1			T2	7		T7	5		T10	4
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	181727	1			T2	4279		T7	258		T13	134
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	113100	1			T2	11		T7	2		T13	6
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	186942	1			T2	4883		T7	3		T13	133
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	86419	1			T2	1		T10	146		T13	5
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	194844	1			T13	5102		T14	4380		T32	1156
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	88405	1			T2	11		T7	1		T11	3
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	187869	1			T2	2612		T11	129		T13	641
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	118656	1			T2	8		T7	1		T11	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	208032	1			T2	3705		T7	694		T11	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	155473	1			T2	3		T7	11		T13	12
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	177789	1			T2	5		T7	3652		T13	258
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	81414	1			T2	3		T7	1		T10	85
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	188882	1			T2	3		T7	422		T13	522
auto[0]	auto[1]	auto[0:524287]	auto[0]	2510	1			T2	1		T7	1		T14	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	63160	1			T2	407		T13	256		T44	129
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	304	1			T14	2		T32	4		T47	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	52795	1			T14	3092		T32	769		T48	1046
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	606	1			T2	1		T14	3		T16	4
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	47094	1			T14	1		T35	128		T32	2562
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	2229	1			T2	1		T13	1		T32	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	60064	1			T2	256		T13	256		T14	2921
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	288	1			T2	2		T13	6		T16	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	45388	1			T13	959		T32	2		T47	129
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	221	1			T2	3		T14	1		T32	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	58022	1			T2	1		T47	1202		T44	523
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	730	1			T2	7		T13	5		T32	4
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	72448	1			T2	2		T13	2		T32	385
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	619	1			T7	4		T14	4		T16	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	39316	1			T7	2322		T14	512		T32	2692
auto[1]	auto[0]	auto[0:524287]	auto[0]	299	1			T7	4		T14	3		T32	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	2159	1			T7	43		T32	12		T44	2
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	173	1			T2	2		T13	5		T14	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1658	1			T2	16		T13	4		T32	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	190	1			T2	5		T7	1		T13	5
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1643	1			T2	67		T7	21		T13	7
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	200	1			T13	1		T14	1		T32	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1602	1			T32	3		T47	16		T44	4
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	178	1			T2	3		T11	1		T13	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1542	1			T2	28		T11	6		T13	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	185	1			T2	1		T13	1		T47	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1615	1			T2	1		T13	1		T47	12
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	199	1			T7	1		T13	2		T15	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1748	1			T13	8		T15	1		T171	7
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	169	1			T2	2		T35	1		T32	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1211	1			T2	20		T35	9		T32	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	57	1			T44	1		T41	2		T166	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	463	1			T44	4		T41	52		T69	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	66	1			T32	1		T48	4		T41	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	681	1			T48	3		T41	30		T69	59
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	45	1			T14	1		T32	2		T68	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	410	1			T14	1		T32	13		T68	8
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	60	1			T32	1		T44	2		T70	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	638	1			T44	1		T70	39		T158	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	57	1			T13	3		T32	1		T47	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	362	1			T13	2		T32	4		T47	4
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	47	1			T2	1		T68	1		T70	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	520	1			T2	3		T68	6		T70	24
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	69	1			T2	2		T13	2		T32	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	647	1			T2	17		T13	7		T47	9
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	47	1			T7	1		T171	2		T69	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	297	1			T171	13		T69	54		T158	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1679632	1			T2	18629		T3	1		T4	1
auto[0]	auto[0]	auto[1]	938890	1			T2	4		T7	2		T10	396
auto[0]	auto[1]	auto[0]	440698	1			T2	680		T7	2327		T13	1485
auto[0]	auto[1]	auto[1]	5096	1			T2	1		T16	4		T32	1
auto[1]	auto[0]	auto[0]	14433	1			T2	138		T7	67		T11	6
auto[1]	auto[0]	auto[1]	338	1			T2	7		T7	3		T11	1
auto[1]	auto[1]	auto[0]	4377	1			T2	20		T7	1		T13	14
auto[1]	auto[1]	auto[1]	89	1			T2	3		T32	2		T44	1