Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16226

1

T2

221

T3

20

T11

18

auto[1]

12022

1

T2

207

T11

9

T13

118

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3665	1			T2	40		T13	68		T14	20
values[1]	3925	1			T2	80		T14	21		T47	48
values[2]	3287	1			T2	132		T13	20		T14	20
values[3]	3637	1			T11	27		T14	61		T165	4
values[4]	3164	1			T2	59		T12	14		T13	20
values[5]	3747	1			T2	52		T13	29		T14	45
values[6]	3743	1			T2	20		T3	20		T13	105
values[7]	3080	1			T2	45		T13	30		T14	73

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3855	1			T2	65		T13	63		T14	61
values[1]	3435	1			T13	24		T14	62		T47	110
values[2]	3770	1			T2	87		T13	22		T14	51
values[3]	3217	1			T2	60		T3	20		T12	14
values[4]	3260	1			T2	45		T14	42		T47	24
values[5]	3431	1			T13	69		T14	26		T35	50
values[6]	3288	1			T2	20		T11	27		T13	22
values[7]	3992	1			T2	151		T254	2		T41	175

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	247	1			T218	47		T255	39		T149	15
auto[0]	values[0]	values[1]	210	1			T13	17		T14	11		T167	9
auto[0]	values[0]	values[2]	283	1			T2	12		T13	12		T46	6
auto[0]	values[0]	values[3]	226	1			T256	4		T257	10		T191	6
auto[0]	values[0]	values[4]	175	1			T48	15		T41	9		T197	21
auto[0]	values[0]	values[5]	186	1			T35	10		T85	14		T258	2
auto[0]	values[0]	values[6]	188	1			T13	12		T41	13		T167	16
auto[0]	values[0]	values[7]	268	1			T2	13		T41	14		T158	14
auto[0]	values[1]	values[0]	305	1			T41	9		T23	24		T24	21
auto[0]	values[1]	values[1]	311	1			T195	43		T36	17		T259	39
auto[0]	values[1]	values[2]	316	1			T2	16		T260	6		T261	10
auto[0]	values[1]	values[3]	224	1			T2	27		T47	10		T51	9
auto[0]	values[1]	values[4]	176	1			T14	12		T262	2		T166	15
auto[0]	values[1]	values[5]	305	1			T166	10		T217	15		T186	4
auto[0]	values[1]	values[6]	280	1			T2	10		T263	2		T167	10
auto[0]	values[1]	values[7]	248	1			T200	12		T214	17		T218	28
auto[0]	values[2]	values[0]	271	1			T2	5		T158	13		T264	14
auto[0]	values[2]	values[1]	351	1			T47	15		T209	16		T265	13
auto[0]	values[2]	values[2]	172	1			T2	17		T41	12		T266	8
auto[0]	values[2]	values[3]	109	1			T47	21		T201	6		T195	5
auto[0]	values[2]	values[4]	265	1			T48	13		T167	13		T200	10
auto[0]	values[2]	values[5]	238	1			T13	20		T191	8		T242	20
auto[0]	values[2]	values[6]	261	1			T14	11		T65	14		T226	12
auto[0]	values[2]	values[7]	259	1			T2	11		T34	26		T267	15
auto[0]	values[3]	values[0]	346	1			T14	11		T167	10		T23	26
auto[0]	values[3]	values[1]	317	1			T14	10		T268	6		T269	6
auto[0]	values[3]	values[2]	247	1			T64	18		T167	14		T23	18
auto[0]	values[3]	values[3]	239	1			T270	6		T195	11		T219	8
auto[0]	values[3]	values[4]	343	1			T14	13		T271	6		T272	20
auto[0]	values[3]	values[5]	329	1			T196	24		T273	14		T82	4
auto[0]	values[3]	values[6]	269	1			T11	18		T165	4		T65	14
auto[0]	values[3]	values[7]	222	1			T41	11		T158	10		T217	23
auto[0]	values[4]	values[0]	208	1			T206	12		T23	14		T34	12
auto[0]	values[4]	values[1]	232	1			T14	17		T167	12		T226	13
auto[0]	values[4]	values[2]	222	1			T274	6		T24	12		T267	12
auto[0]	values[4]	values[3]	273	1			T12	14		T80	18		T41	6
auto[0]	values[4]	values[4]	191	1			T83	2		T275	14		T224	10
auto[0]	values[4]	values[5]	148	1			T13	12		T189	2		T264	9
auto[0]	values[4]	values[6]	219	1			T234	14		T24	14		T195	7
auto[0]	values[4]	values[7]	323	1			T2	51		T259	105		T276	4
auto[0]	values[5]	values[0]	160	1			T14	12		T47	21		T277	4
auto[0]	values[5]	values[1]	269	1			T47	12		T158	12		T278	16
auto[0]	values[5]	values[2]	312	1			T14	20		T41	11		T81	6
auto[0]	values[5]	values[3]	261	1			T191	50		T279	6		T226	16
auto[0]	values[5]	values[4]	299	1			T48	11		T166	11		T167	20
auto[0]	values[5]	values[5]	326	1			T13	7		T47	12		T191	75
auto[0]	values[5]	values[6]	315	1			T166	14		T193	16		T280	15
auto[0]	values[5]	values[7]	367	1			T2	42		T41	16		T191	5
auto[0]	values[6]	values[0]	363	1			T13	23		T41	100		T215	18
auto[0]	values[6]	values[1]	250	1			T281	8		T282	8		T283	2
auto[0]	values[6]	values[2]	170	1			T246	4		T191	12		T36	16
auto[0]	values[6]	values[3]	267	1			T2	8		T3	20		T13	38
auto[0]	values[6]	values[4]	328	1			T47	16		T24	11		T200	17
auto[0]	values[6]	values[5]	345	1			T35	15		T200	16		T216	28
auto[0]	values[6]	values[6]	246	1			T168	14		T36	32		T197	8
auto[0]	values[6]	values[7]	224	1			T160	8		T226	9		T195	12
auto[0]	values[7]	values[0]	418	1			T13	13		T14	12		T16	18
auto[0]	values[7]	values[1]	179	1			T48	6		T166	8		T23	10
auto[0]	values[7]	values[2]	339	1			T14	12		T168	42		T24	11
auto[0]	values[7]	values[3]	129	1			T166	14		T34	12		T202	12
auto[0]	values[7]	values[4]	130	1			T2	9		T41	13		T166	10
auto[0]	values[7]	values[5]	137	1			T14	21		T284	12		T282	15
auto[0]	values[7]	values[6]	173	1			T41	15		T166	13		T23	14
auto[0]	values[7]	values[7]	217	1			T23	34		T195	10		T132	19
auto[1]	values[0]	values[0]	160	1			T218	8		T255	61		T149	26
auto[1]	values[0]	values[1]	192	1			T13	7		T14	9		T167	12
auto[1]	values[0]	values[2]	373	1			T2	8		T13	10		T243	24
auto[1]	values[0]	values[3]	303	1			T191	14		T24	2		T218	13
auto[1]	values[0]	values[4]	151	1			T48	6		T41	11		T197	4
auto[1]	values[0]	values[5]	250	1			T35	10		T282	123		T54	17
auto[1]	values[0]	values[6]	153	1			T13	10		T41	7		T167	11
auto[1]	values[0]	values[7]	300	1			T2	7		T41	41		T158	6
auto[1]	values[1]	values[0]	142	1			T41	11		T23	11		T24	29
auto[1]	values[1]	values[1]	141	1			T195	4		T36	3		T259	6
auto[1]	values[1]	values[2]	276	1			T2	4		T158	50		T191	8
auto[1]	values[1]	values[3]	198	1			T2	13		T47	38		T51	11
auto[1]	values[1]	values[4]	173	1			T14	9		T166	5		T23	7
auto[1]	values[1]	values[5]	167	1			T166	13		T217	6		T264	5
auto[1]	values[1]	values[6]	229	1			T2	10		T167	15		T168	14
auto[1]	values[1]	values[7]	434	1			T200	29		T214	12		T218	8
auto[1]	values[2]	values[0]	168	1			T2	60		T158	8		T264	9
auto[1]	values[2]	values[1]	178	1			T47	75		T209	9		T265	7
auto[1]	values[2]	values[2]	220	1			T2	30		T41	80		T191	6
auto[1]	values[2]	values[3]	88	1			T47	4		T195	15		T132	11
auto[1]	values[2]	values[4]	87	1			T48	7		T167	7		T200	10
auto[1]	values[2]	values[5]	163	1			T191	20		T24	12		T132	13
auto[1]	values[2]	values[6]	173	1			T14	9		T65	6		T228	16
auto[1]	values[2]	values[7]	284	1			T2	9		T34	7		T267	6
auto[1]	values[3]	values[0]	286	1			T14	9		T227	14		T167	10
auto[1]	values[3]	values[1]	201	1			T14	10		T23	11		T267	14
auto[1]	values[3]	values[2]	127	1			T50	6		T167	7		T23	2
auto[1]	values[3]	values[3]	140	1			T195	9		T240	6		T280	13
auto[1]	values[3]	values[4]	141	1			T14	8		T22	5		T215	6
auto[1]	values[3]	values[5]	64	1			T49	8		T226	2		T218	6
auto[1]	values[3]	values[6]	142	1			T11	9		T65	6		T41	7
auto[1]	values[3]	values[7]	224	1			T41	67		T158	10		T217	8
auto[1]	values[4]	values[0]	152	1			T23	6		T34	15		T216	10
auto[1]	values[4]	values[1]	134	1			T14	5		T167	13		T226	7
auto[1]	values[4]	values[2]	173	1			T24	11		T267	8		T285	4
auto[1]	values[4]	values[3]	218	1			T41	87		T167	9		T192	9
auto[1]	values[4]	values[4]	202	1			T224	10		T259	50		T202	9
auto[1]	values[4]	values[5]	195	1			T13	8		T264	11		T216	5
auto[1]	values[4]	values[6]	193	1			T24	7		T195	13		T54	14
auto[1]	values[4]	values[7]	81	1			T2	8		T259	15		T211	6
auto[1]	values[5]	values[0]	160	1			T14	9		T47	12		T224	5
auto[1]	values[5]	values[1]	251	1			T47	8		T158	8		T286	2
auto[1]	values[5]	values[2]	234	1			T14	4		T41	9		T167	5
auto[1]	values[5]	values[3]	172	1			T191	7		T226	4		T282	12
auto[1]	values[5]	values[4]	130	1			T48	9		T166	11		T167	4
auto[1]	values[5]	values[5]	262	1			T13	22		T47	53		T191	9
auto[1]	values[5]	values[6]	101	1			T166	8		T193	4		T280	5
auto[1]	values[5]	values[7]	128	1			T2	10		T41	26		T191	15
auto[1]	values[6]	values[0]	206	1			T13	10		T41	6		T215	10
auto[1]	values[6]	values[1]	131	1			T282	12		T194	27		T211	10
auto[1]	values[6]	values[2]	111	1			T191	8		T287	12		T36	6
auto[1]	values[6]	values[3]	259	1			T2	12		T13	34		T191	11
auto[1]	values[6]	values[4]	290	1			T47	8		T24	14		T200	3
auto[1]	values[6]	values[5]	183	1			T35	15		T288	14		T200	8
auto[1]	values[6]	values[6]	197	1			T168	6		T36	21		T197	12
auto[1]	values[6]	values[7]	173	1			T254	2		T226	11		T195	8
auto[1]	values[7]	values[0]	263	1			T13	17		T14	8		T245	7
auto[1]	values[7]	values[1]	88	1			T48	23		T166	12		T23	18
auto[1]	values[7]	values[2]	195	1			T14	15		T289	14		T168	36
auto[1]	values[7]	values[3]	111	1			T166	6		T34	12		T202	8
auto[1]	values[7]	values[4]	179	1			T2	36		T41	61		T166	11
auto[1]	values[7]	values[5]	133	1			T14	5		T282	5		T224	9
auto[1]	values[7]	values[6]	149	1			T41	5		T166	7		T290	4
auto[1]	values[7]	values[7]	240	1			T23	15		T195	162		T132	6