Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2866217	1			T1	1		T2	10648		T3	1
all_pins[1]	2866217	1			T1	1		T2	10648		T3	1
all_pins[2]	2866217	1			T1	1		T2	10648		T3	1
all_pins[3]	2866217	1			T1	1		T2	10648		T3	1
all_pins[4]	2866217	1			T1	1		T2	10648		T3	1
all_pins[5]	2866217	1			T1	1		T2	10648		T3	1
all_pins[6]	2866217	1			T1	1		T2	10648		T3	1
all_pins[7]	2866217	1			T1	1		T2	10648		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	22906549	1			T1	8		T2	85184		T3	8
values[0x1]	23187	1			T14	13		T18	48		T19	39
transitions[0x0=>0x1]	22593	1			T14	13		T18	34		T19	36
transitions[0x1=>0x0]	22600	1			T14	13		T18	34		T19	36

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2865733	1			T1	1		T2	10648		T3	1
all_pins[0]	values[0x1]	484	1			T14	1		T18	4		T19	2
all_pins[0]	transitions[0x0=>0x1]	253	1			T14	1		T18	3		T19	2
all_pins[0]	transitions[0x1=>0x0]	220	1			T14	5		T18	7		T19	4
all_pins[1]	values[0x0]	2865766	1			T1	1		T2	10648		T3	1
all_pins[1]	values[0x1]	451	1			T14	5		T18	8		T19	4
all_pins[1]	transitions[0x0=>0x1]	386	1			T14	5		T18	7		T19	4
all_pins[1]	transitions[0x1=>0x0]	154	1			T18	3		T19	3		T20	2
all_pins[2]	values[0x0]	2865998	1			T1	1		T2	10648		T3	1
all_pins[2]	values[0x1]	219	1			T18	4		T19	3		T20	2
all_pins[2]	transitions[0x0=>0x1]	174	1			T19	3		T20	2		T147	3
all_pins[2]	transitions[0x1=>0x0]	136	1			T14	4		T18	3		T19	8
all_pins[3]	values[0x0]	2866036	1			T1	1		T2	10648		T3	1
all_pins[3]	values[0x1]	181	1			T14	4		T18	7		T19	8
all_pins[3]	transitions[0x0=>0x1]	136	1			T14	4		T18	7		T19	6
all_pins[3]	transitions[0x1=>0x0]	144	1			T18	4		T19	3		T20	2
all_pins[4]	values[0x0]	2866028	1			T1	1		T2	10648		T3	1
all_pins[4]	values[0x1]	189	1			T18	4		T19	5		T20	2
all_pins[4]	transitions[0x0=>0x1]	152	1			T18	2		T19	4		T20	2
all_pins[4]	transitions[0x1=>0x0]	682	1			T18	8		T19	4		T20	4
all_pins[5]	values[0x0]	2865498	1			T1	1		T2	10648		T3	1
all_pins[5]	values[0x1]	719	1			T18	10		T19	5		T20	4
all_pins[5]	transitions[0x0=>0x1]	648	1			T18	8		T19	5		T20	4
all_pins[5]	transitions[0x1=>0x0]	20663	1			T14	3		T18	1		T19	7
all_pins[6]	values[0x0]	2845483	1			T1	1		T2	10648		T3	1
all_pins[6]	values[0x1]	20734	1			T14	3		T18	3		T19	7
all_pins[6]	transitions[0x0=>0x1]	20692	1			T14	3		T18	1		T19	7
all_pins[6]	transitions[0x1=>0x0]	168	1			T18	6		T19	5		T20	4
all_pins[7]	values[0x0]	2866007	1			T1	1		T2	10648		T3	1
all_pins[7]	values[0x1]	210	1			T18	8		T19	5		T20	4
all_pins[7]	transitions[0x0=>0x1]	152	1			T18	6		T19	5		T20	4
all_pins[7]	transitions[0x1=>0x0]	433	1			T14	1		T18	2		T19	2