Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	347	1			T2	3		T13	5		T14	5
auto[ReadAddrCrossIntoMailbox]	239	1			T2	4		T13	4		T14	3
auto[ReadAddrCrossOutOfMailbox]	283	1			T2	5		T13	2		T35	1
auto[ReadAddrCrossAllMailbox]	194	1			T2	4		T13	2		T14	2
auto[ReadAddrOutsideMailbox]	3053	1			T2	42		T3	10		T11	3

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1994

1

T2

32

T3

5

T12

1

auto[1]

2122

1

T2

26

T3

5

T11

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	662	1			T2	7		T13	8		T14	7
read_ops[0x0b]	734	1			T2	13		T3	4		T13	11
read_ops[0x3b]	713	1			T2	9		T3	4		T12	2
read_ops[0x6b]	694	1			T2	10		T3	2		T11	2
read_ops[0xbb]	648	1			T2	10		T11	1		T13	5
read_ops[0xeb]	665	1			T2	9		T13	6		T14	7

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	23	1			T85	1		T260	1		T166	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T85	1		T260	1		T167	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T2	1		T13	1		T271	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T271	1		T282	1		T36	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T41	2		T191	1		T245	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T41	1		T168	1		T226	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T14	1		T245	1		T34	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T166	1		T23	1		T24	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	240	1			T2	5		T13	4		T14	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	250	1			T2	1		T13	3		T14	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T2	1		T13	2		T35	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	16	1			T14	1		T166	1		T200	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T2	1		T13	1		T191	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T158	1		T168	1		T23	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T35	1		T271	1		T191	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T271	1		T195	1		T54	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T2	1		T41	1		T271	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T271	1		T167	2		T195	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	267	1			T2	2		T3	2		T13	6
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	287	1			T2	8		T3	2		T13	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	21	1			T13	1		T35	1		T24	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T2	1		T13	1		T41	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T191	1		T217	1		T215	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T2	1		T41	1		T167	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T22	1		T23	1		T217	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T13	1		T166	1		T200	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T191	1		T167	1		T54	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T167	1		T195	1		T132	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	260	1			T2	2		T3	2		T12	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	271	1			T2	5		T3	2		T12	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T14	1		T23	1		T245	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T14	1		T166	2		T167	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T13	1		T216	1		T293	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T14	1		T158	1		T191	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T2	1		T41	1		T252	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T13	1		T48	1		T41	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T2	2		T13	1		T14	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T13	1		T23	1		T226	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	259	1			T2	4		T3	1		T14	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	245	1			T2	3		T3	1		T11	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	23	1			T41	2		T166	3		T217	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T41	1		T167	1		T168	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	14	1			T14	2		T168	1		T252	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T35	1		T168	1		T252	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T2	3		T217	1		T200	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T41	2		T245	1		T216	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T41	1		T23	1		T217	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T2	1		T35	1		T195	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	215	1			T2	4		T13	2		T14	4
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	251	1			T2	2		T11	1		T13	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	21	1			T2	1		T14	1		T247	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T13	1		T14	1		T166	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T13	1		T47	2		T41	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T2	1		T167	1		T264	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	14	1			T247	2		T168	1		T252	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T2	1		T247	2		T191	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T41	1		T226	1		T294	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T294	1		T214	1		T193	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	233	1			T2	4		T13	2		T14	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	275	1			T2	2		T13	2		T14	3