Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3099	1			T3	20		T13	46		T14	42
values[1]	3166	1			T2	72		T13	21		T14	24
values[2]	3699	1			T2	67		T12	14		T13	60
values[3]	3095	1			T2	119		T14	40		T47	147
values[4]	3758	1			T13	30		T64	18		T263	2
values[5]	3406	1			T2	40		T13	42		T14	47
values[6]	3676	1			T2	45		T11	27		T13	73
values[7]	4349	1			T2	85		T47	68		T65	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3662	1			T2	65		T13	31		T47	90
values[1]	3699	1			T2	67		T13	20		T47	33
values[2]	3137	1			T2	59		T11	27		T13	74
values[3]	3423	1			T2	72		T13	62		T14	47
values[4]	3351	1			T2	40		T14	65		T80	18
values[5]	3508	1			T2	85		T13	45		T14	46
values[6]	3619	1			T2	20		T13	20		T14	63
values[7]	3849	1			T2	20		T3	20		T12	14

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27591

1

T2

419

T3

20

T11

26

auto[1]

657

1

T2

9

T11

1

T13

13

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	390	1			T166	22		T190	4		T168	37
auto[0]	values[0]	values[1]	413	1			T277	4		T23	27		T279	6
auto[0]	values[0]	values[2]	368	1			T13	22		T295	10		T296	6
auto[0]	values[0]	values[3]	567	1			T41	103		T167	36		T264	20
auto[0]	values[0]	values[4]	244	1			T80	18		T23	19		T24	21
auto[0]	values[0]	values[5]	290	1			T13	23		T166	23		T200	20
auto[0]	values[0]	values[6]	406	1			T14	20		T23	24		T216	23
auto[0]	values[0]	values[7]	372	1			T3	20		T14	20		T47	64
auto[0]	values[1]	values[0]	373	1			T191	20		T288	14		T278	16
auto[0]	values[1]	values[1]	363	1			T48	21		T226	24		T215	88
auto[0]	values[1]	values[2]	285	1			T281	8		T260	6		T191	20
auto[0]	values[1]	values[3]	288	1			T2	52		T292	10		T34	19
auto[0]	values[1]	values[4]	461	1			T2	19		T14	24		T158	20
auto[0]	values[1]	values[5]	485	1			T13	21		T167	26		T226	20
auto[0]	values[1]	values[6]	462	1			T168	19		T230	12		T297	10
auto[0]	values[1]	values[7]	369	1			T224	20		T36	15		T203	22
auto[0]	values[2]	values[0]	455	1			T13	29		T166	19		T226	20
auto[0]	values[2]	values[1]	572	1			T2	47		T41	20		T23	44
auto[0]	values[2]	values[2]	386	1			T47	24		T41	20		T167	23
auto[0]	values[2]	values[3]	429	1			T13	26		T166	17		T167	22
auto[0]	values[2]	values[4]	475	1			T2	20		T234	14		T239	44
auto[0]	values[2]	values[5]	424	1			T14	20		T166	20		T167	20
auto[0]	values[2]	values[6]	292	1			T14	20		T48	20		T213	12
auto[0]	values[2]	values[7]	571	1			T12	14		T166	22		T261	10
auto[0]	values[3]	values[0]	539	1			T2	20		T47	90		T50	4
auto[0]	values[3]	values[1]	346	1			T47	31		T41	20		T81	6
auto[0]	values[3]	values[2]	464	1			T2	57		T46	6		T49	6
auto[0]	values[3]	values[3]	457	1			T2	20		T14	20		T41	113
auto[0]	values[3]	values[4]	209	1			T14	20		T226	18		T202	47
auto[0]	values[3]	values[5]	248	1			T47	24		T41	55		T298	2
auto[0]	values[3]	values[6]	336	1			T41	72		T223	20		T255	20
auto[0]	values[3]	values[7]	421	1			T2	17		T34	24		T282	155
auto[0]	values[4]	values[0]	513	1			T227	14		T160	8		T167	22
auto[0]	values[4]	values[1]	408	1			T252	8		T214	48		T299	8
auto[0]	values[4]	values[2]	341	1			T13	29		T64	18		T247	8
auto[0]	values[4]	values[3]	458	1			T263	2		T256	4		T168	79
auto[0]	values[4]	values[4]	423	1			T289	14		T217	30		T24	23
auto[0]	values[4]	values[5]	460	1			T166	20		T191	20		T34	24
auto[0]	values[4]	values[6]	428	1			T191	83		T23	19		T300	18
auto[0]	values[4]	values[7]	626	1			T191	57		T23	20		T34	18
auto[0]	values[5]	values[0]	381	1			T200	86		T208	22		T301	2
auto[0]	values[5]	values[1]	440	1			T258	2		T168	41		T24	25
auto[0]	values[5]	values[2]	220	1			T13	21		T48	20		T158	20
auto[0]	values[5]	values[3]	422	1			T158	20		T191	56		T23	39
auto[0]	values[5]	values[4]	614	1			T14	21		T48	27		T291	16
auto[0]	values[5]	values[5]	517	1			T2	19		T14	26		T65	19
auto[0]	values[5]	values[6]	437	1			T2	20		T13	20		T35	29
auto[0]	values[5]	values[7]	301	1			T35	20		T85	14		T290	4
auto[0]	values[6]	values[0]	443	1			T2	43		T41	33		T167	39
auto[0]	values[6]	values[1]	472	1			T13	19		T271	6		T168	21
auto[0]	values[6]	values[2]	551	1			T11	26		T14	20		T254	2
auto[0]	values[6]	values[3]	297	1			T13	31		T14	25		T16	18
auto[0]	values[6]	values[4]	412	1			T196	24		T167	20		T23	35
auto[0]	values[6]	values[5]	518	1			T242	20		T302	8		T216	19
auto[0]	values[6]	values[6]	417	1			T14	20		T246	4		T228	16
auto[0]	values[6]	values[7]	475	1			T13	18		T200	66		T303	38
auto[0]	values[7]	values[0]	474	1			T206	12		T304	2		T267	21
auto[0]	values[7]	values[1]	603	1			T2	20		T167	24		T237	18
auto[0]	values[7]	values[2]	448	1			T47	48		T226	23		T267	20
auto[0]	values[7]	values[3]	416	1			T268	6		T274	6		T226	20
auto[0]	values[7]	values[4]	442	1			T65	20		T41	77		T168	106
auto[0]	values[7]	values[5]	485	1			T2	65		T189	2		T193	32
auto[0]	values[7]	values[6]	756	1			T47	20		T166	20		T243	24
auto[0]	values[7]	values[7]	633	1			T41	112		T168	39		T305	8
auto[1]	values[0]	values[0]	9	1			T282	4		T207	1		T306	2
auto[1]	values[0]	values[1]	6	1			T23	1		T264	1		T255	1
auto[1]	values[0]	values[2]	1	1			T232	1		-	-		-	-
auto[1]	values[0]	values[3]	9	1			T41	3		T167	2		T214	1
auto[1]	values[0]	values[4]	3	1			T23	1		T195	2		-	-
auto[1]	values[0]	values[5]	5	1			T13	1		T197	1		T212	1
auto[1]	values[0]	values[6]	12	1			T14	1		T216	3		T203	1
auto[1]	values[0]	values[7]	4	1			T14	1		T47	1		T267	2
auto[1]	values[1]	values[0]	6	1			T193	1		T307	1		T308	4
auto[1]	values[1]	values[1]	6	1			T54	6		-	-		-	-
auto[1]	values[1]	values[2]	5	1			T216	2		T309	1		T150	2
auto[1]	values[1]	values[3]	8	1			T34	1		T195	2		T197	1
auto[1]	values[1]	values[4]	15	1			T2	1		T265	1		T203	1
auto[1]	values[1]	values[5]	10	1			T167	1		T226	3		T214	1
auto[1]	values[1]	values[6]	16	1			T168	1		T197	2		T132	1
auto[1]	values[1]	values[7]	14	1			T36	5		T203	2		T310	1
auto[1]	values[2]	values[0]	15	1			T13	2		T166	2		T193	1
auto[1]	values[2]	values[1]	12	1			T215	1		T259	1		T311	2
auto[1]	values[2]	values[2]	11	1			T47	1		T167	2		T287	2
auto[1]	values[2]	values[3]	17	1			T13	3		T166	3		T167	2
auto[1]	values[2]	values[4]	8	1			T148	1		T150	2		T205	2
auto[1]	values[2]	values[5]	16	1			T167	1		T34	2		T193	1
auto[1]	values[2]	values[6]	7	1			T54	1		T312	2		T313	2
auto[1]	values[2]	values[7]	9	1			T22	1		T168	2		T259	1
auto[1]	values[3]	values[0]	13	1			T50	2		T259	2		T218	5
auto[1]	values[3]	values[1]	5	1			T47	2		T211	1		T314	1
auto[1]	values[3]	values[2]	21	1			T2	2		T49	2		T36	2
auto[1]	values[3]	values[3]	10	1			T51	1		T239	2		T202	3
auto[1]	values[3]	values[4]	4	1			T226	2		T203	1		T211	1
auto[1]	values[3]	values[5]	1	1			T315	1		-	-		-	-
auto[1]	values[3]	values[6]	7	1			T41	2		T154	3		T316	2
auto[1]	values[3]	values[7]	14	1			T2	3		T282	3		T211	4
auto[1]	values[4]	values[0]	21	1			T248	4		T224	4		T194	3
auto[1]	values[4]	values[1]	17	1			T214	1		T299	6		T208	1
auto[1]	values[4]	values[2]	8	1			T13	1		T23	2		T267	1
auto[1]	values[4]	values[3]	14	1			T168	1		T36	2		T187	1
auto[1]	values[4]	values[4]	5	1			T217	1		T208	1		T309	1
auto[1]	values[4]	values[5]	14	1			T265	2		T203	2		T198	3
auto[1]	values[4]	values[6]	12	1			T191	1		T23	3		T240	2
auto[1]	values[4]	values[7]	10	1			T34	2		T216	1		T195	2
auto[1]	values[5]	values[0]	8	1			T200	1		T317	1		T205	2
auto[1]	values[5]	values[1]	8	1			T318	1		T255	2		T313	2
auto[1]	values[5]	values[2]	7	1			T13	1		T226	1		T132	2
auto[1]	values[5]	values[3]	13	1			T191	2		T23	2		T36	2
auto[1]	values[5]	values[4]	13	1			T48	2		T200	3		T187	1
auto[1]	values[5]	values[5]	10	1			T2	1		T65	1		T202	3
auto[1]	values[5]	values[6]	8	1			T35	1		T194	1		T203	1
auto[1]	values[5]	values[7]	7	1			T23	2		T255	1		T203	2
auto[1]	values[6]	values[0]	8	1			T2	2		T41	1		T167	1
auto[1]	values[6]	values[1]	10	1			T13	1		T168	1		T214	3
auto[1]	values[6]	values[2]	17	1			T11	1		T215	3		T195	2
auto[1]	values[6]	values[3]	11	1			T13	2		T14	2		T41	2
auto[1]	values[6]	values[4]	12	1			T167	1		T23	1		T311	5
auto[1]	values[6]	values[5]	14	1			T216	1		T265	3		T203	2
auto[1]	values[6]	values[6]	5	1			T14	2		T216	1		T133	1
auto[1]	values[6]	values[7]	14	1			T13	2		T200	1		T187	1
auto[1]	values[7]	values[0]	14	1			T36	5		T199	2		T212	3
auto[1]	values[7]	values[1]	18	1			T167	1		T214	2		T239	1
auto[1]	values[7]	values[2]	4	1			T307	2		T55	2		-	-
auto[1]	values[7]	values[3]	7	1			T319	2		T133	3		T198	1
auto[1]	values[7]	values[4]	11	1			T41	1		T168	2		T199	2
auto[1]	values[7]	values[5]	11	1			T193	1		T229	5		T320	2
auto[1]	values[7]	values[6]	18	1			T24	4		T36	3		T218	3
auto[1]	values[7]	values[7]	9	1			T226	2		T202	1		T309	2