Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1694

1

T4

2

T6

4

T13

8

auto[1]

1731

1

T4

3

T6

2

T13

7

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1829

1

T4

5

T13

13

T14

16

auto[1]

1596

1

T6

6

T13

2

T27

17

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2723

1

T4

4

T6

6

T13

11

auto[1]

702

1

T4

1

T13

4

T14

6

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	678	1			T6	2		T13	5		T14	4
valid[1]	676	1			T6	1		T13	3		T14	1
valid[2]	735	1			T6	2		T14	3		T27	5
valid[3]	665	1			T4	4		T6	1		T13	4
valid[4]	671	1			T4	1		T13	3		T14	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	105	1			T13	3		T14	1		T335	1
auto[0]	auto[0]	valid[0]	auto[1]	145	1			T6	1		T27	1		T31	2
auto[0]	auto[0]	valid[1]	auto[0]	124	1			T13	1		T15	1		T44	1
auto[0]	auto[0]	valid[1]	auto[1]	153	1			T6	1		T27	2		T44	1
auto[0]	auto[0]	valid[2]	auto[0]	120	1			T14	1		T32	2		T52	1
auto[0]	auto[0]	valid[2]	auto[1]	187	1			T6	2		T27	3		T76	3
auto[0]	auto[0]	valid[3]	auto[0]	112	1			T4	2		T13	1		T14	3
auto[0]	auto[0]	valid[3]	auto[1]	165	1			T31	3		T76	1		T78	1
auto[0]	auto[0]	valid[4]	auto[0]	115	1			T13	1		T15	1		T52	1
auto[0]	auto[0]	valid[4]	auto[1]	131	1			T27	1		T76	2		T66	6
auto[0]	auto[1]	valid[0]	auto[0]	119	1			T13	1		T14	2		T48	1
auto[0]	auto[1]	valid[0]	auto[1]	178	1			T6	1		T13	1		T27	4
auto[0]	auto[1]	valid[1]	auto[0]	99	1			T13	1		T15	3		T48	3
auto[0]	auto[1]	valid[1]	auto[1]	176	1			T13	1		T66	4		T77	1
auto[0]	auto[1]	valid[2]	auto[0]	106	1			T15	3		T32	1		T48	2
auto[0]	auto[1]	valid[2]	auto[1]	163	1			T27	2		T31	1		T76	4
auto[0]	auto[1]	valid[3]	auto[0]	119	1			T4	1		T13	1		T14	1
auto[0]	auto[1]	valid[3]	auto[1]	134	1			T6	1		T27	3		T31	1
auto[0]	auto[1]	valid[4]	auto[0]	108	1			T4	1		T14	2		T48	2
auto[0]	auto[1]	valid[4]	auto[1]	164	1			T27	1		T31	1		T44	2
auto[1]	auto[0]	valid[0]	auto[0]	63	1			T30	1		T166	1		T330	1
auto[1]	auto[0]	valid[1]	auto[0]	62	1			T48	1		T335	1		T166	1
auto[1]	auto[0]	valid[2]	auto[0]	74	1			T32	1		T33	1		T48	1
auto[1]	auto[0]	valid[3]	auto[0]	62	1			T13	1		T14	2		T65	1
auto[1]	auto[0]	valid[4]	auto[0]	76	1			T13	1		T30	1		T15	1
auto[1]	auto[1]	valid[0]	auto[0]	68	1			T14	1		T48	1		T44	1
auto[1]	auto[1]	valid[1]	auto[0]	62	1			T14	1		T32	1		T328	1
auto[1]	auto[1]	valid[2]	auto[0]	85	1			T14	2		T15	1		T335	1
auto[1]	auto[1]	valid[3]	auto[0]	73	1			T4	1		T13	1		T48	1
auto[1]	auto[1]	valid[4]	auto[0]	77	1			T13	1		T15	1		T48	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal