Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	831	1			T14	7		T18	24		T19	24
all_values[1]	831	1			T14	7		T18	24		T19	24
all_values[2]	831	1			T14	7		T18	24		T19	24
all_values[3]	831	1			T14	7		T18	24		T19	24
all_values[4]	831	1			T14	7		T18	24		T19	24
all_values[5]	831	1			T14	7		T18	24		T19	24
all_values[6]	831	1			T14	7		T18	24		T19	24
all_values[7]	831	1			T14	7		T18	24		T19	24

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3530

1

T14

23

T18

88

T19

100

auto[1]

3118

1

T14

33

T18

104

T19

92

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2680

1

T14

29

T18

82

T19

77

auto[1]

3968

1

T14

27

T18

110

T19

115

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3794

1

T14

37

T18

114

T19

101

auto[1]

2854

1

T14

19

T18

78

T19

91

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	170	1			T18	5		T19	6		T20	6
all_values[0]	auto[0]	auto[0]	auto[1]	75	1			T23	1		T24	4		T164	2
all_values[0]	auto[0]	auto[1]	auto[0]	159	1			T14	1		T18	8		T19	3
all_values[0]	auto[0]	auto[1]	auto[1]	72	1			T14	1		T18	1		T19	2
all_values[0]	auto[1]	auto[0]	auto[1]	182	1			T14	4		T18	3		T19	9
all_values[0]	auto[1]	auto[1]	auto[1]	173	1			T14	1		T18	7		T19	4
all_values[1]	auto[0]	auto[0]	auto[0]	159	1			T14	1		T18	4		T19	4
all_values[1]	auto[0]	auto[0]	auto[1]	81	1			T18	3		T19	2		T20	1
all_values[1]	auto[0]	auto[1]	auto[0]	162	1			T18	6		T19	6		T20	7
all_values[1]	auto[0]	auto[1]	auto[1]	85	1			T14	4		T18	3		T19	2
all_values[1]	auto[1]	auto[0]	auto[1]	180	1			T14	1		T18	5		T19	6
all_values[1]	auto[1]	auto[1]	auto[1]	164	1			T14	1		T18	3		T19	4
all_values[2]	auto[0]	auto[0]	auto[0]	172	1			T18	7		T19	9		T20	4
all_values[2]	auto[0]	auto[0]	auto[1]	83	1			T18	2		T19	1		T23	1
all_values[2]	auto[0]	auto[1]	auto[0]	137	1			T14	5		T18	7		T19	2
all_values[2]	auto[0]	auto[1]	auto[1]	70	1			T18	1		T19	2		T20	1
all_values[2]	auto[1]	auto[0]	auto[1]	198	1			T14	2		T18	2		T19	8
all_values[2]	auto[1]	auto[1]	auto[1]	171	1			T18	5		T19	2		T20	1
all_values[3]	auto[0]	auto[0]	auto[0]	191	1			T14	1		T18	3		T19	3
all_values[3]	auto[0]	auto[0]	auto[1]	84	1			T14	1		T18	3		T19	3
all_values[3]	auto[0]	auto[1]	auto[0]	131	1			T18	3		T19	2		T20	5
all_values[3]	auto[0]	auto[1]	auto[1]	70	1			T18	3		T19	3		T23	1
all_values[3]	auto[1]	auto[0]	auto[1]	184	1			T14	1		T18	9		T19	5
all_values[3]	auto[1]	auto[1]	auto[1]	171	1			T14	4		T18	3		T19	8
all_values[4]	auto[0]	auto[0]	auto[0]	173	1			T14	4		T18	3		T20	5
all_values[4]	auto[0]	auto[0]	auto[1]	90	1			T18	4		T19	2		T20	2
all_values[4]	auto[0]	auto[1]	auto[0]	136	1			T14	2		T18	5		T19	8
all_values[4]	auto[0]	auto[1]	auto[1]	75	1			T18	3		T19	2		T20	1
all_values[4]	auto[1]	auto[0]	auto[1]	189	1			T14	1		T18	5		T19	9
all_values[4]	auto[1]	auto[1]	auto[1]	168	1			T18	4		T19	3		T20	2
all_values[5]	auto[0]	auto[0]	auto[0]	244	1			T14	1		T18	3		T19	6
all_values[5]	auto[0]	auto[1]	auto[0]	224	1			T14	5		T18	5		T19	9
all_values[5]	auto[1]	auto[0]	auto[1]	188	1			T18	5		T19	5		T23	2
all_values[5]	auto[1]	auto[1]	auto[1]	175	1			T14	1		T18	11		T19	4
all_values[6]	auto[0]	auto[0]	auto[0]	173	1			T14	1		T18	10		T19	2
all_values[6]	auto[0]	auto[0]	auto[1]	84	1			T18	1		T19	1		T20	1
all_values[6]	auto[0]	auto[1]	auto[0]	138	1			T14	2		T18	5		T19	6
all_values[6]	auto[0]	auto[1]	auto[1]	77	1			T14	2		T18	2		T19	1
all_values[6]	auto[1]	auto[0]	auto[1]	187	1			T14	1		T18	2		T19	7
all_values[6]	auto[1]	auto[1]	auto[1]	172	1			T14	1		T18	4		T19	7
all_values[7]	auto[0]	auto[0]	auto[0]	183	1			T14	4		T18	3		T19	6
all_values[7]	auto[0]	auto[0]	auto[1]	78	1			T18	2		T19	2		T20	2
all_values[7]	auto[0]	auto[1]	auto[0]	128	1			T14	2		T18	5		T19	5
all_values[7]	auto[0]	auto[1]	auto[1]	90	1			T18	4		T19	1		T20	2
all_values[7]	auto[1]	auto[0]	auto[1]	182	1			T18	4		T19	4		T20	2
all_values[7]	auto[1]	auto[1]	auto[1]	170	1			T14	1		T18	6		T19	6

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal