Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46935

1

T4

84

T13

385

T14

402

auto[1]

17169

1

T6

6

T13

43

T27

255

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46742

1

T4

63

T6

6

T13

286

auto[1]

17362

1

T4

21

T13

142

T14

139

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32956	1			T4	43		T6	6		T13	211
others[1]	5377	1			T4	9		T13	38		T14	34
others[2]	5306	1			T4	5		T13	25		T14	29
others[3]	6121	1			T4	8		T13	35		T14	42
interest[1]	3524	1			T4	4		T13	32		T14	19
interest[4]	21374	1			T4	30		T6	6		T13	128
interest[64]	10820	1			T4	15		T13	87		T14	74

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15033	1			T4	32		T13	116		T14	131
auto[0]	auto[0]	others[1]	2499	1			T4	7		T13	18		T14	24
auto[0]	auto[0]	others[2]	2444	1			T4	3		T13	11		T14	19
auto[0]	auto[0]	others[3]	2807	1			T4	5		T13	19		T14	27
auto[0]	auto[0]	interest[1]	1669	1			T4	3		T13	23		T14	14
auto[0]	auto[0]	interest[4]	9649	1			T4	22		T13	66		T14	88
auto[0]	auto[0]	interest[64]	5121	1			T4	13		T13	56		T14	48
auto[0]	auto[1]	others[0]	8996	1			T6	6		T13	26		T27	136
auto[0]	auto[1]	others[1]	1419	1			T13	2		T27	26		T76	12
auto[0]	auto[1]	others[2]	1387	1			T13	6		T27	15		T44	3
auto[0]	auto[1]	others[3]	1623	1			T13	2		T27	25		T44	3
auto[0]	auto[1]	interest[1]	927	1			T13	2		T27	12		T76	11
auto[0]	auto[1]	interest[4]	5961	1			T6	6		T13	17		T27	88
auto[0]	auto[1]	interest[64]	2817	1			T13	5		T27	41		T44	5
auto[1]	auto[0]	others[0]	8927	1			T4	11		T13	69		T14	73
auto[1]	auto[0]	others[1]	1459	1			T4	2		T13	18		T14	10
auto[1]	auto[0]	others[2]	1475	1			T4	2		T13	8		T14	10
auto[1]	auto[0]	others[3]	1691	1			T4	3		T13	14		T14	15
auto[1]	auto[0]	interest[1]	928	1			T4	1		T13	7		T14	5
auto[1]	auto[0]	interest[4]	5764	1			T4	8		T13	45		T14	50
auto[1]	auto[0]	interest[64]	2882	1			T4	2		T13	26		T14	26

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal