Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2410096	1			T1	1		T2	1		T3	70447
all_values[1]	2410096	1			T1	1		T2	1		T3	70447
all_values[2]	2410096	1			T1	1		T2	1		T3	70447
all_values[3]	2410096	1			T1	1		T2	1		T3	70447
all_values[4]	2410096	1			T1	1		T2	1		T3	70447
all_values[5]	2410096	1			T1	1		T2	1		T3	70447
all_values[6]	2410096	1			T1	1		T2	1		T3	70447
all_values[7]	2410096	1			T1	1		T2	1		T3	70447

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19138633

1

T1

8

T2

8

T3

563576

auto[1]

142135

1

T6

54

T13

23759

T14

24

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19255129

1

T1

8

T2

8

T3

563360

auto[1]

25639

1

T3

216

T6

482

T11

2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2388634	1			T1	1		T2	1		T3	70345
all_values[0]	auto[0]	auto[1]	11517	1			T3	102		T6	192		T13	116
all_values[0]	auto[1]	auto[0]	9464	1			T6	4		T13	5733		T14	4
all_values[0]	auto[1]	auto[1]	481	1			T6	4		T13	207		T15	4
all_values[1]	auto[0]	auto[0]	2390616	1			T1	1		T2	1		T3	70382
all_values[1]	auto[0]	auto[1]	7972	1			T3	65		T6	185		T13	262
all_values[1]	auto[1]	auto[0]	11141	1			T6	5		T14	4		T16	1
all_values[1]	auto[1]	auto[1]	367	1			T6	3		T14	1		T15	4
all_values[2]	auto[0]	auto[0]	2387039	1			T1	1		T2	1		T3	70398
all_values[2]	auto[0]	auto[1]	3075	1			T3	49		T6	80		T13	40
all_values[2]	auto[1]	auto[0]	19671	1			T6	4		T13	5877		T15	8
all_values[2]	auto[1]	auto[1]	311	1			T13	62		T15	2		T16	2
all_values[3]	auto[0]	auto[0]	2378219	1			T1	1		T2	1		T3	70447
all_values[3]	auto[0]	auto[1]	202	1			T11	2		T13	2		T15	5
all_values[3]	auto[1]	auto[0]	31475	1			T6	5		T13	5936		T14	5
all_values[3]	auto[1]	auto[1]	200	1			T13	2		T14	1		T18	5
all_values[4]	auto[0]	auto[0]	2394281	1			T1	1		T2	1		T3	70447
all_values[4]	auto[0]	auto[1]	200	1			T6	5		T13	3		T15	1
all_values[4]	auto[1]	auto[0]	15427	1			T6	2		T14	3		T15	5
all_values[4]	auto[1]	auto[1]	188	1			T6	1		T14	3		T15	3
all_values[5]	auto[0]	auto[0]	2370829	1			T1	1		T2	1		T3	70447
all_values[5]	auto[0]	auto[1]	182	1			T6	4		T14	2		T15	4
all_values[5]	auto[1]	auto[0]	38923	1			T6	3		T13	5938		T15	2
all_values[5]	auto[1]	auto[1]	162	1			T6	1		T13	2		T14	1
all_values[6]	auto[0]	auto[0]	2401913	1			T1	1		T2	1		T3	70447
all_values[6]	auto[0]	auto[1]	161	1			T6	2		T13	3		T14	3
all_values[6]	auto[1]	auto[0]	7799	1			T6	9		T14	1		T15	5
all_values[6]	auto[1]	auto[1]	223	1			T6	1		T15	5		T16	3
all_values[7]	auto[0]	auto[0]	2403588	1			T1	1		T2	1		T3	70447
all_values[7]	auto[0]	auto[1]	205	1			T13	2		T14	3		T15	4
all_values[7]	auto[1]	auto[0]	6110	1			T6	8		T13	2		T15	2
all_values[7]	auto[1]	auto[1]	193	1			T6	4		T14	1		T15	5