Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	32976	1			T2	8		T3	114		T5	2
auto[SpiFlashAddrCfg]	6452	1			T2	6		T3	49		T6	82
auto[SpiFlashAddr3b]	7953	1			T2	2		T3	49		T6	71
auto[SpiFlashAddr4b]	6194	1			T3	46		T6	71		T7	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29751

1

T2

16

T3

163

T5

2

auto[1]

23824

1

T3

95

T6

279

T13

283

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28242

1

T2

10

T3

139

T5

2

auto[1]

25333

1

T2

6

T3

119

T6

306

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	36958	1			T2	6		T3	135		T5	2
values[1]	955	1			T3	8		T6	9		T9	4
values[2]	1169	1			T3	7		T6	13		T11	3
values[3]	1244	1			T3	11		T6	13		T9	6
values[4]	1313	1			T3	14		T6	18		T9	4
values[5]	1229	1			T2	2		T3	3		T6	13
values[6]	1201	1			T3	7		T6	6		T7	2
values[7]	1235	1			T2	2		T3	10		T6	10
values[8]	8271	1			T2	6		T3	63		T6	99

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29523

1

T2

16

T3

258

T5

2

auto[1]

24052

1

T11

5

T13

376

T24

437

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

50806

1

T2

16

T3

247

T5

2

write

2769

1

T3

11

T6

34

T7

4

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

16117

1

T2

8

T3

130

T5

2

valids[0x1]

37458

1

T2

8

T3

128

T6

338

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1316	1			T2	2		T3	13		T6	13
internal_process_ops[0x5a]	1330	1			T3	7		T6	10		T10	6
internal_process_ops[0x05]	21248	1			T2	2		T3	22		T6	178
internal_process_ops[0x35]	1369	1			T3	9		T6	12		T8	2
internal_process_ops[0x15]	1398	1			T2	2		T3	4		T6	12
internal_process_ops[0x03]	926	1			T3	12		T6	17		T13	13
internal_process_ops[0x0b]	957	1			T3	6		T6	9		T9	2
internal_process_ops[0x3b]	920	1			T2	2		T3	6		T6	11
internal_process_ops[0x6b]	917	1			T2	2		T3	6		T6	15
internal_process_ops[0xbb]	991	1			T3	6		T6	14		T7	4
internal_process_ops[0xeb]	908	1			T2	2		T3	10		T6	11

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52220

1

T2

16

T3

254

T5

2

auto[1]

1355

1

T3

4

T6

17

T13

18

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51614

1

T2

16

T3

246

T5

2

auto[1]

1961

1

T3

12

T6

18

T13

29

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10213

1

T2

8

T3

93

T5

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6859

1

T3

19

T6

160

T13

28

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1783

1

T2

6

T3

22

T6

29

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1628

1

T3

25

T6

44

T13

24

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2301

1

T2

2

T3

23

T6

31

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1956

1

T3

23

T6

31

T13

28

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1846

1

T3

20

T6

30

T7

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1510

1

T3

22

T6

33

T13

21

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

87

1

T6

2

T13

1

T33

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

57

1

T6

1

T13

1

T33

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

85

1

T3

2

T6

4

T13

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

96

1

T6

1

T32

1

T33

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

91

1

T6

1

T7

4

T13

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

87

1

T3

1

T6

5

T32

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

105

1

T3

1

T6

3

T13

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

97

1

T33

1

T36

2

T15

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

115

1

T6

4

T13

3

T32

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

85

1

T6

3

T13

2

T32

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

77

1

T3

2

T6

1

T38

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

108

1

T3

1

T6

1

T13

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

106

1

T3

2

T6

2

T13

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

78

1

T3

2

T6

5

T32

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

84

1

T33

4

T36

5

T38

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

69

1

T6

1

T35

2

T32

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8394

1

T13

114

T24

114

T27

159

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6825

1

T13

92

T24

152

T27

299

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1235

1

T11

5

T13

17

T24

20

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1100

1

T13

33

T24

29

T27

24

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1493

1

T13

21

T24

40

T27

15

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1478

1

T13

23

T24

23

T27

29

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1112

1

T13

26

T24

20

T27

20

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1073

1

T13

21

T24

19

T27

20

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

88

1

T13

9

T24

2

T27

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

99

1

T13

1

T24

2

T14

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

74

1

T24

3

T27

2

T14

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

99

1

T13

2

T24

2

T14

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

80

1

T14

3

T156

4

T157

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

70

1

T13

1

T24

1

T158

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

92

1

T24

1

T27

1

T14

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

84

1

T13

2

T24

1

T27

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

69

1

T13

3

T27

2

T159

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

83

1

T13

1

T24

2

T27

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

99

1

T13

1

T14

1

T160

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

89

1

T24

1

T27

2

T159

7

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

96

1

T13

1

T27

8

T14

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

83

1

T13

4

T24

2

T27

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

66

1

T13

1

T24

1

T14

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

71

1

T13

3

T24

2

T27

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3387	1			T3	62		T5	2		T6	54
auto[0]	values[0]	valids[0x1]	16328	1			T2	6		T3	73		T6	270
auto[0]	values[1]	valids[0x1]	486	1			T3	8		T6	9		T9	4
auto[0]	values[2]	valids[0x0]	429	1			T3	3		T6	8		T13	4
auto[0]	values[2]	valids[0x1]	248	1			T3	4		T6	5		T32	2
auto[0]	values[3]	valids[0x0]	466	1			T3	8		T6	11		T9	6
auto[0]	values[3]	valids[0x1]	267	1			T3	3		T6	2		T13	2
auto[0]	values[4]	valids[0x0]	540	1			T3	4		T6	13		T9	4
auto[0]	values[4]	valids[0x1]	256	1			T3	10		T6	5		T13	2
auto[0]	values[5]	valids[0x0]	485	1			T3	3		T6	9		T13	8
auto[0]	values[5]	valids[0x1]	293	1			T2	2		T6	4		T13	5
auto[0]	values[6]	valids[0x0]	491	1			T3	5		T6	4		T7	2
auto[0]	values[6]	valids[0x1]	242	1			T3	2		T6	2		T13	2
auto[0]	values[7]	valids[0x0]	473	1			T2	2		T3	8		T6	3
auto[0]	values[7]	valids[0x1]	265	1			T3	2		T6	7		T13	1
auto[0]	values[8]	valids[0x0]	3071	1			T2	6		T3	37		T6	65
auto[0]	values[8]	valids[0x1]	1796	1			T3	26		T6	34		T9	2
auto[1]	values[0]	valids[0x0]	2997	1			T13	58		T24	50		T27	48
auto[1]	values[0]	valids[0x1]	14246	1			T13	197		T24	254		T27	449
auto[1]	values[1]	valids[0x1]	469	1			T13	9		T24	12		T27	7
auto[1]	values[2]	valids[0x0]	294	1			T11	3		T13	3		T24	5
auto[1]	values[2]	valids[0x1]	198	1			T13	4		T27	4		T14	1
auto[1]	values[3]	valids[0x0]	303	1			T13	5		T24	11		T27	3
auto[1]	values[3]	valids[0x1]	208	1			T13	4		T24	3		T27	6
auto[1]	values[4]	valids[0x0]	323	1			T13	8		T24	7		T27	3
auto[1]	values[4]	valids[0x1]	194	1			T13	4		T24	2		T27	2
auto[1]	values[5]	valids[0x0]	255	1			T13	4		T24	8		T27	11
auto[1]	values[5]	valids[0x1]	196	1			T13	2		T27	1		T14	2
auto[1]	values[6]	valids[0x0]	266	1			T13	11		T24	5		T27	4
auto[1]	values[6]	valids[0x1]	202	1			T13	3		T24	3		T27	2
auto[1]	values[7]	valids[0x0]	283	1			T11	2		T13	3		T24	4
auto[1]	values[7]	valids[0x1]	214	1			T24	1		T27	1		T14	7
auto[1]	values[8]	valids[0x0]	2054	1			T13	29		T24	39		T27	37
auto[1]	values[8]	valids[0x1]	1350	1			T13	32		T24	33		T27	24