Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2872118

1

T2

1

T3

10672

T5

4603

auto[1]

19955

1

T3

19

T6

165

T13

123

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

809624

1

T2

1

T3

81

T5

4603

auto[1]

2082449

1

T3

10610

T6

29805

T8

114

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	571400	1			T2	1		T3	3		T5	138
auto[524288:1048575]	366926	1			T3	1648		T5	971		T6	8773
auto[1048576:1572863]	344407	1			T3	8		T5	982		T6	338
auto[1572864:2097151]	391994	1			T3	533		T5	483		T6	10446
auto[2097152:2621439]	305264	1			T3	270		T5	1		T6	678
auto[2621440:3145727]	310524	1			T3	3060		T5	1879		T6	474
auto[3145728:3670015]	300843	1			T3	1990		T5	145		T6	3849
auto[3670016:4194303]	300715	1			T3	3179		T5	4		T6	3013

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2103402

1

T2

1

T3

10691

T5

22

auto[1]

788671

1

T5

4581

T6

11

T8

689

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2504440

1

T2

1

T3

6804

T5

4597

auto[1]

387633

1

T3

3887

T5

6

T6

2150

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	186415	1			T2	1		T3	3		T5	138
auto[0]	auto[0]	auto[0:524287]	auto[1]	339387	1			T6	2319		T8	56		T13	1255
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	90769	1			T3	2		T5	971		T6	7
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	225419	1			T3	1		T6	8761		T8	8
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	112210	1			T5	980		T6	9		T8	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	193876	1			T3	1		T6	314		T8	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	107878	1			T3	8		T5	483		T6	17
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	216581	1			T3	522		T6	10401		T13	895
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	82762	1			T3	9		T5	1		T6	11
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	165475	1			T3	260		T6	643		T13	628
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	65120	1			T3	10		T5	1879		T6	6
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	196698	1			T3	3046		T6	454		T13	1292
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	71662	1			T3	13		T5	145		T6	21
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	181188	1			T3	264		T6	1628		T13	5999
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	72933	1			T3	5		T6	9		T8	101
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	180022	1			T3	2647		T6	2990		T8	49
auto[0]	auto[1]	auto[0:524287]	auto[0]	4438	1			T6	1		T13	14		T24	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	38461	1			T13	3015		T32	7		T14	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1027	1			T3	3		T13	3		T24	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	47231	1			T3	1641		T13	256		T24	256
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	481	1			T3	2		T5	2		T13	6
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	35400	1			T3	2		T13	2796		T27	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	3545	1			T6	1		T13	2		T32	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	62013	1			T14	23		T33	1		T159	128
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	4265	1			T3	1		T13	9		T24	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	50379	1			T13	261		T24	1399		T32	1782
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	814	1			T3	1		T13	1		T27	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	45268	1			T13	1		T14	1797		T39	788
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	3005	1			T3	2		T13	1		T27	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	42064	1			T3	1706		T6	2148		T27	512
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	336	1			T3	9		T5	4		T13	10
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	44996	1			T3	514		T13	740		T27	128
auto[1]	auto[0]	auto[0:524287]	auto[0]	240	1			T6	2		T13	6		T24	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2055	1			T6	12		T13	14		T24	9
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	182	1			T3	1		T6	2		T24	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1671	1			T6	3		T24	8		T33	5
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	193	1			T6	2		T13	3		T27	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1940	1			T6	13		T13	12		T27	41
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	165	1			T3	2		T6	2		T13	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1321	1			T3	1		T6	25		T13	5
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	208	1			T6	3		T13	3		T24	4
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1601	1			T6	21		T13	1		T24	38
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	210	1			T3	2		T6	1		T13	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2129	1			T3	1		T6	13		T13	6
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	207	1			T3	3		T6	3		T13	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1857	1			T3	2		T6	49		T13	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	171	1			T3	1		T6	3		T13	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1895	1			T6	11		T13	6		T24	42
auto[1]	auto[1]	auto[0:524287]	auto[0]	44	1			T13	3		T32	4		T14	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	360	1			T13	4		T32	6		T38	7
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	51	1			T27	2		T14	1		T33	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	576	1			T27	7		T14	2		T36	69
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	41	1			T3	2		T13	1		T27	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	266	1			T3	1		T13	1		T27	8
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	46	1			T14	1		T33	1		T18	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	445	1			T18	2		T194	6		T201	68
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	54	1			T13	1		T32	1		T201	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	520	1			T13	1		T32	3		T201	35
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	42	1			T13	1		T39	1		T38	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	243	1			T13	35		T39	17		T38	4
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	67	1			T32	1		T14	1		T15	4
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	793	1			T32	17		T14	1		T15	136
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	43	1			T3	2		T13	4		T18	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	319	1			T3	1		T13	8		T173	4

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1716265	1			T2	1		T3	6791		T5	18
auto[0]	auto[0]	auto[1]	772130	1			T5	4579		T6	4		T8	689
auto[0]	auto[1]	auto[0]	367535	1			T3	3881		T5	4		T6	2150
auto[0]	auto[1]	auto[1]	16188	1			T5	2		T13	1		T27	2
auto[1]	auto[0]	auto[0]	15755	1			T3	13		T6	158		T13	64
auto[1]	auto[0]	auto[1]	290	1			T6	7		T24	8		T27	2
auto[1]	auto[1]	auto[0]	3847	1			T3	6		T13	57		T27	17
auto[1]	auto[1]	auto[1]	63	1			T13	2		T27	1		T32	3