Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16849

1

T2

16

T3

163

T5

2

auto[1]

12674

1

T3

95

T6

279

T13

105

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3272	1			T3	91		T6	69		T7	22
values[1]	3245	1			T3	41		T6	84		T13	64
values[2]	3920	1			T5	2		T6	109		T13	23
values[3]	3794	1			T3	21		T13	22		T35	16
values[4]	3613	1			T6	82		T8	4		T10	8
values[5]	4168	1			T3	20		T6	80		T13	22
values[6]	3896	1			T3	65		T6	20		T13	74
values[7]	3615	1			T2	16		T3	20		T6	61

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3745	1			T3	41		T6	44		T32	78
values[1]	3570	1			T3	20		T5	2		T6	34
values[2]	4146	1			T3	68		T6	127		T13	23
values[3]	3672	1			T6	50		T13	24		T32	20
values[4]	2930	1			T2	16		T3	21		T6	87
values[5]	4598	1			T6	123		T36	131		T15	82
values[6]	3396	1			T3	85		T13	96		T35	16
values[7]	3466	1			T3	23		T6	40		T7	22

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	170	1			T32	11		T121	17		T151	10
auto[0]	values[0]	values[1]	234	1			T13	12		T186	14		T222	6
auto[0]	values[0]	values[2]	127	1			T3	9		T223	10		T63	11
auto[0]	values[0]	values[3]	276	1			T196	6		T80	14		T214	2
auto[0]	values[0]	values[4]	201	1			T6	10		T32	17		T224	2
auto[0]	values[0]	values[5]	163	1			T6	16		T63	6		T69	7
auto[0]	values[0]	values[6]	309	1			T3	23		T36	13		T183	7
auto[0]	values[0]	values[7]	249	1			T3	17		T7	22		T15	22
auto[0]	values[1]	values[0]	166	1			T33	12		T225	4		T187	11
auto[0]	values[1]	values[1]	394	1			T6	12		T36	9		T185	8
auto[0]	values[1]	values[2]	273	1			T3	12		T32	13		T205	59
auto[0]	values[1]	values[3]	356	1			T6	21		T13	8		T32	4
auto[0]	values[1]	values[4]	121	1			T3	12		T36	6		T199	12
auto[0]	values[1]	values[5]	293	1			T15	13		T20	12		T187	21
auto[0]	values[1]	values[6]	222	1			T13	12		T33	19		T185	8
auto[0]	values[1]	values[7]	130	1			T6	9		T13	12		T140	2
auto[0]	values[2]	values[0]	205	1			T32	9		T36	13		T38	5
auto[0]	values[2]	values[1]	275	1			T5	2		T32	10		T33	13
auto[0]	values[2]	values[2]	379	1			T6	45		T32	13		T182	12
auto[0]	values[2]	values[3]	287	1			T226	10		T184	15		T70	16
auto[0]	values[2]	values[4]	124	1			T6	8		T36	7		T63	5
auto[0]	values[2]	values[5]	496	1			T15	11		T185	14		T201	9
auto[0]	values[2]	values[6]	276	1			T13	10		T33	10		T210	26
auto[0]	values[2]	values[7]	176	1			T33	11		T15	10		T187	15
auto[0]	values[3]	values[0]	269	1			T3	15		T15	9		T67	20
auto[0]	values[3]	values[1]	212	1			T227	4		T216	10		T63	13
auto[0]	values[3]	values[2]	212	1			T185	11		T187	10		T69	12
auto[0]	values[3]	values[3]	169	1			T15	12		T228	8		T191	37
auto[0]	values[3]	values[4]	180	1			T13	16		T229	2		T173	18
auto[0]	values[3]	values[5]	375	1			T206	80		T187	16		T230	2
auto[0]	values[3]	values[6]	329	1			T15	11		T231	16		T19	11
auto[0]	values[3]	values[7]	256	1			T219	2		T173	8		T187	8
auto[0]	values[4]	values[0]	419	1			T6	18		T15	11		T185	10
auto[0]	values[4]	values[1]	182	1			T36	14		T232	13		T233	4
auto[0]	values[4]	values[2]	315	1			T6	9		T234	2		T36	80
auto[0]	values[4]	values[3]	223	1			T33	10		T192	13		T175	16
auto[0]	values[4]	values[4]	149	1			T15	12		T235	14		T187	14
auto[0]	values[4]	values[5]	430	1			T6	10		T36	71		T187	14
auto[0]	values[4]	values[6]	205	1			T32	17		T36	22		T187	7
auto[0]	values[4]	values[7]	370	1			T8	4		T10	8		T173	11
auto[0]	values[5]	values[0]	361	1			T173	34		T151	33		T152	40
auto[0]	values[5]	values[1]	242	1			T32	11		T15	10		T205	8
auto[0]	values[5]	values[2]	369	1			T33	18		T236	10		T184	21
auto[0]	values[5]	values[3]	364	1			T211	12		T237	4		T176	18
auto[0]	values[5]	values[4]	291	1			T32	20		T36	8		T38	13
auto[0]	values[5]	values[5]	306	1			T6	20		T15	10		T238	4
auto[0]	values[5]	values[6]	349	1			T3	15		T38	21		T173	9
auto[0]	values[5]	values[7]	141	1			T13	12		T77	18		T181	12
auto[0]	values[6]	values[0]	249	1			T3	16		T32	11		T239	14
auto[0]	values[6]	values[1]	250	1			T173	11		T152	13		T240	2
auto[0]	values[6]	values[2]	326	1			T3	18		T13	13		T33	14
auto[0]	values[6]	values[3]	217	1			T6	11		T38	13		T15	15
auto[0]	values[6]	values[4]	292	1			T15	13		T20	13		T63	18
auto[0]	values[6]	values[5]	483	1			T36	39		T81	22		T69	23
auto[0]	values[6]	values[6]	236	1			T3	16		T13	22		T105	12
auto[0]	values[6]	values[7]	217	1			T13	12		T33	28		T206	21
auto[0]	values[7]	values[0]	172	1			T6	12		T38	16		T63	19
auto[0]	values[7]	values[1]	143	1			T3	10		T36	10		T205	17
auto[0]	values[7]	values[2]	320	1			T241	8		T242	12		T216	9
auto[0]	values[7]	values[3]	285	1			T15	37		T243	22		T63	11
auto[0]	values[7]	values[4]	241	1			T2	16		T6	13		T32	13
auto[0]	values[7]	values[5]	122	1			T244	8		T201	24		T245	10
auto[0]	values[7]	values[6]	153	1			T13	13		T246	2		T173	9
auto[0]	values[7]	values[7]	523	1			T6	12		T9	18		T33	15
auto[1]	values[0]	values[0]	264	1			T32	9		T121	3		T151	17
auto[1]	values[0]	values[1]	212	1			T13	8		T192	7		T71	12
auto[1]	values[0]	values[2]	143	1			T3	14		T247	16		T63	9
auto[1]	values[0]	values[3]	148	1			T121	8		T63	12		T248	6
auto[1]	values[0]	values[4]	200	1			T6	36		T32	59		T249	21
auto[1]	values[0]	values[5]	162	1			T6	7		T63	14		T69	13
auto[1]	values[0]	values[6]	182	1			T3	22		T36	54		T183	31
auto[1]	values[0]	values[7]	232	1			T3	6		T15	158		T201	7
auto[1]	values[1]	values[0]	182	1			T33	8		T187	9		T70	25
auto[1]	values[1]	values[1]	312	1			T6	22		T36	11		T185	32
auto[1]	values[1]	values[2]	151	1			T3	8		T32	9		T205	6
auto[1]	values[1]	values[3]	187	1			T6	9		T13	16		T32	16
auto[1]	values[1]	values[4]	119	1			T3	9		T36	14		T20	8
auto[1]	values[1]	values[5]	118	1			T15	7		T20	32		T187	5
auto[1]	values[1]	values[6]	133	1			T13	8		T33	5		T185	28
auto[1]	values[1]	values[7]	88	1			T6	11		T13	8		T173	11
auto[1]	values[2]	values[0]	105	1			T32	28		T36	7		T38	15
auto[1]	values[2]	values[1]	220	1			T32	10		T33	8		T183	14
auto[1]	values[2]	values[2]	361	1			T6	44		T32	14		T205	42
auto[1]	values[2]	values[3]	222	1			T184	6		T70	17		T192	4
auto[1]	values[2]	values[4]	180	1			T6	12		T36	25		T63	15
auto[1]	values[2]	values[5]	285	1			T15	31		T189	18		T185	6
auto[1]	values[2]	values[6]	175	1			T13	13		T33	13		T174	8
auto[1]	values[2]	values[7]	154	1			T33	11		T15	10		T187	15
auto[1]	values[3]	values[0]	214	1			T3	6		T15	11		T250	12
auto[1]	values[3]	values[1]	344	1			T216	11		T63	22		T184	17
auto[1]	values[3]	values[2]	239	1			T185	111		T187	10		T69	29
auto[1]	values[3]	values[3]	180	1			T15	8		T191	10		T168	11
auto[1]	values[3]	values[4]	118	1			T13	6		T173	5		T216	11
auto[1]	values[3]	values[5]	129	1			T206	11		T187	7		T178	11
auto[1]	values[3]	values[6]	280	1			T35	16		T15	9		T251	24
auto[1]	values[3]	values[7]	288	1			T173	12		T187	12		T201	7
auto[1]	values[4]	values[0]	218	1			T6	6		T15	9		T185	10
auto[1]	values[4]	values[1]	178	1			T36	6		T232	102		T178	15
auto[1]	values[4]	values[2]	237	1			T6	29		T36	11		T70	17
auto[1]	values[4]	values[3]	137	1			T33	10		T252	10		T192	7
auto[1]	values[4]	values[4]	119	1			T15	24		T253	2		T187	6
auto[1]	values[4]	values[5]	165	1			T6	10		T36	10		T187	8
auto[1]	values[4]	values[6]	171	1			T32	3		T36	8		T187	13
auto[1]	values[4]	values[7]	95	1			T173	10		T184	13		T174	6
auto[1]	values[5]	values[0]	248	1			T173	17		T151	7		T152	18
auto[1]	values[5]	values[1]	105	1			T32	9		T15	10		T205	12
auto[1]	values[5]	values[2]	188	1			T33	10		T184	9		T192	14
auto[1]	values[5]	values[3]	204	1			T173	4		T183	38		T187	30
auto[1]	values[5]	values[4]	155	1			T134	2		T32	6		T36	13
auto[1]	values[5]	values[5]	633	1			T6	60		T15	10		T173	8
auto[1]	values[5]	values[6]	115	1			T3	5		T38	6		T173	11
auto[1]	values[5]	values[7]	97	1			T13	10		T168	9		T207	8
auto[1]	values[6]	values[0]	202	1			T3	4		T32	10		T216	12
auto[1]	values[6]	values[1]	179	1			T173	10		T152	7		T70	17
auto[1]	values[6]	values[2]	270	1			T3	7		T13	10		T33	9
auto[1]	values[6]	values[3]	192	1			T6	9		T38	47		T15	9
auto[1]	values[6]	values[4]	144	1			T15	7		T20	11		T63	2
auto[1]	values[6]	values[5]	326	1			T36	11		T69	9		T204	10
auto[1]	values[6]	values[6]	113	1			T3	4		T13	9		T183	21
auto[1]	values[6]	values[7]	200	1			T13	8		T33	17		T37	2
auto[1]	values[7]	values[0]	301	1			T6	8		T38	38		T120	4
auto[1]	values[7]	values[1]	88	1			T3	10		T36	10		T205	6
auto[1]	values[7]	values[2]	236	1			T216	11		T183	21		T179	8
auto[1]	values[7]	values[3]	225	1			T15	8		T190	24		T63	13
auto[1]	values[7]	values[4]	296	1			T6	8		T32	7		T15	12
auto[1]	values[7]	values[5]	112	1			T201	21		T245	22		T177	7
auto[1]	values[7]	values[6]	148	1			T13	9		T173	11		T187	7
auto[1]	values[7]	values[7]	250	1			T6	8		T33	5		T185	10