Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2410096	1			T1	1		T2	1		T3	70447
all_pins[1]	2410096	1			T1	1		T2	1		T3	70447
all_pins[2]	2410096	1			T1	1		T2	1		T3	70447
all_pins[3]	2410096	1			T1	1		T2	1		T3	70447
all_pins[4]	2410096	1			T1	1		T2	1		T3	70447
all_pins[5]	2410096	1			T1	1		T2	1		T3	70447
all_pins[6]	2410096	1			T1	1		T2	1		T3	70447
all_pins[7]	2410096	1			T1	1		T2	1		T3	70447

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	19270279	1			T1	8		T2	8		T3	563576
values[0x1]	10489	1			T6	14		T13	721		T14	7
transitions[0x0=>0x1]	9878	1			T6	10		T13	719		T14	6
transitions[0x1=>0x0]	9894	1			T6	10		T13	719		T14	6

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2409595	1			T1	1		T2	1		T3	70447
all_pins[0]	values[0x1]	501	1			T6	4		T13	221		T15	4
all_pins[0]	transitions[0x0=>0x1]	403	1			T6	2		T13	221		T15	4
all_pins[0]	transitions[0x1=>0x0]	296	1			T6	1		T14	1		T15	4
all_pins[1]	values[0x0]	2409702	1			T1	1		T2	1		T3	70447
all_pins[1]	values[0x1]	394	1			T6	3		T14	1		T15	4
all_pins[1]	transitions[0x0=>0x1]	252	1			T6	3		T14	1		T15	3
all_pins[1]	transitions[0x1=>0x0]	185	1			T13	67		T15	1		T16	2
all_pins[2]	values[0x0]	2409769	1			T1	1		T2	1		T3	70447
all_pins[2]	values[0x1]	327	1			T13	67		T15	2		T16	2
all_pins[2]	transitions[0x0=>0x1]	278	1			T13	65		T15	2		T16	2
all_pins[2]	transitions[0x1=>0x0]	151	1			T14	1		T18	4		T19	4
all_pins[3]	values[0x0]	2409896	1			T1	1		T2	1		T3	70447
all_pins[3]	values[0x1]	200	1			T13	2		T14	1		T18	5
all_pins[3]	transitions[0x0=>0x1]	155	1			T13	2		T14	1		T18	3
all_pins[3]	transitions[0x1=>0x0]	143	1			T6	1		T14	3		T15	3
all_pins[4]	values[0x0]	2409908	1			T1	1		T2	1		T3	70447
all_pins[4]	values[0x1]	188	1			T6	1		T14	3		T15	3
all_pins[4]	transitions[0x0=>0x1]	149	1			T6	1		T14	2		T15	3
all_pins[4]	transitions[0x1=>0x0]	938	1			T6	1		T13	431		T15	3
all_pins[5]	values[0x0]	2409119	1			T1	1		T2	1		T3	70447
all_pins[5]	values[0x1]	977	1			T6	1		T13	431		T14	1
all_pins[5]	transitions[0x0=>0x1]	847	1			T6	1		T13	431		T14	1
all_pins[5]	transitions[0x1=>0x0]	7579	1			T6	1		T15	5		T16	3
all_pins[6]	values[0x0]	2402387	1			T1	1		T2	1		T3	70447
all_pins[6]	values[0x1]	7709	1			T6	1		T15	5		T16	3
all_pins[6]	transitions[0x0=>0x1]	7662	1			T15	4		T16	3		T18	2
all_pins[6]	transitions[0x1=>0x0]	146	1			T6	3		T14	1		T15	4
all_pins[7]	values[0x0]	2409903	1			T1	1		T2	1		T3	70447
all_pins[7]	values[0x1]	193	1			T6	4		T14	1		T15	5
all_pins[7]	transitions[0x0=>0x1]	132	1			T6	3		T14	1		T15	4
all_pins[7]	transitions[0x1=>0x0]	456	1			T6	3		T13	221		T15	3