Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	383	1			T3	2		T6	8		T13	3
auto[ReadAddrCrossIntoMailbox]	250	1			T3	2		T6	5		T13	2
auto[ReadAddrCrossOutOfMailbox]	292	1			T3	3		T6	5		T13	4
auto[ReadAddrCrossAllMailbox]	191	1			T3	1		T6	8		T13	1
auto[ReadAddrOutsideMailbox]	3218	1			T2	6		T3	38		T6	51

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2182

1

T2

3

T3

18

T6

43

auto[1]

2152

1

T2

3

T3

28

T6

34

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	711	1			T3	12		T6	17		T13	11
read_ops[0x0b]	757	1			T3	6		T6	9		T9	2
read_ops[0x3b]	690	1			T2	2		T3	6		T6	11
read_ops[0x6b]	720	1			T2	2		T3	6		T6	15
read_ops[0xbb]	760	1			T3	6		T6	14		T7	4
read_ops[0xeb]	696	1			T2	2		T3	10		T6	11

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T6	2		T33	1		T199	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T3	1		T13	1		T32	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T173	1		T152	1		T28	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T3	2		T32	1		T36	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T15	1		T216	1		T187	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	35	1			T13	2		T32	1		T15	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T6	1		T33	1		T173	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T6	1		T15	1		T20	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	255	1			T3	5		T6	7		T13	4
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	253	1			T3	4		T6	6		T13	4
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	21	1			T38	1		T228	1		T206	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T32	1		T36	1		T38	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T6	1		T36	1		T206	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T6	1		T13	1		T36	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T3	1		T13	1		T36	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T36	1		T15	4		T173	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T32	1		T36	1		T221	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	26	1			T6	1		T13	1		T15	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	276	1			T3	3		T6	5		T9	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	280	1			T3	2		T6	1		T9	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T3	1		T32	1		T211	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T211	3		T199	2		T228	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T6	1		T187	1		T70	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T13	1		T32	1		T36	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T36	3		T15	1		T173	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T3	1		T6	1		T32	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T6	2		T33	1		T211	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T211	1		T63	1		T184	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	269	1			T2	1		T3	2		T6	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	233	1			T2	1		T3	2		T6	4
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T6	1		T15	1		T173	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T6	1		T13	1		T36	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T33	1		T36	1		T211	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T211	1		T63	1		T212	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T6	1		T36	1		T15	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T6	1		T32	1		T33	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T36	1		T152	1		T28	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T6	2		T32	1		T33	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	256	1			T2	1		T3	1		T6	7
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	271	1			T2	1		T3	5		T6	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T6	1		T13	1		T36	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T36	1		T15	2		T199	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T36	1		T15	1		T187	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T6	1		T33	1		T205	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	14	1			T15	2		T187	2		T221	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	12	1			T3	1		T33	1		T173	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T183	1		T221	1		T184	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T33	1		T20	1		T221	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	304	1			T3	1		T6	6		T7	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	292	1			T3	4		T6	6		T7	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T6	1		T211	1		T15	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T6	2		T32	2		T36	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	13	1			T6	1		T191	1		T204	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	12	1			T206	1		T187	1		T204	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T6	1		T13	1		T32	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T6	1		T33	2		T36	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T3	1		T6	1		T216	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	8	1			T36	1		T204	1		T192	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	264	1			T2	1		T3	3		T6	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	265	1			T2	1		T3	6		T6	3