Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4184	1			T3	21		T6	47		T32	76
values[1]	4337	1			T6	68		T13	20		T33	44
values[2]	4162	1			T3	72		T6	78		T8	4
values[3]	3331	1			T3	40		T6	110		T9	18
values[4]	3515	1			T3	44		T13	51		T35	16
values[5]	3190	1			T3	41		T5	2		T6	44
values[6]	2744	1			T2	16		T3	20		T6	62
values[7]	4060	1			T3	20		T6	96		T7	22

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3523	1			T6	126		T13	22		T140	2
values[1]	4277	1			T2	16		T3	44		T6	30
values[2]	3529	1			T3	21		T6	58		T13	42
values[3]	2865	1			T3	43		T5	2		T6	86
values[4]	4026	1			T3	65		T6	164		T8	4
values[5]	4121	1			T3	44		T6	21		T13	42
values[6]	3049	1			T6	20		T13	51		T32	113
values[7]	4133	1			T3	41		T13	43		T32	27

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28846

1

T2

16

T3

254

T5

2

auto[1]

677

1

T3

4

T6

17

T13

4

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	572	1			T6	46		T63	27		T204	66
auto[0]	values[0]	values[1]	733	1			T38	20		T15	54		T199	12
auto[0]	values[0]	values[2]	577	1			T36	78		T173	20		T152	29
auto[0]	values[0]	values[3]	268	1			T15	41		T173	27		T28	42
auto[0]	values[0]	values[4]	438	1			T36	66		T244	8		T214	2
auto[0]	values[0]	values[5]	727	1			T15	43		T187	51		T28	24
auto[0]	values[0]	values[6]	289	1			T32	73		T36	19		T187	20
auto[0]	values[0]	values[7]	499	1			T3	21		T201	19		T70	39
auto[0]	values[1]	values[0]	515	1			T15	40		T254	6		T238	4
auto[0]	values[1]	values[1]	794	1			T6	29		T33	22		T38	36
auto[0]	values[1]	values[2]	610	1			T6	36		T33	21		T173	22
auto[0]	values[1]	values[3]	229	1			T196	6		T184	20		T153	20
auto[0]	values[1]	values[4]	602	1			T216	18		T206	91		T183	32
auto[0]	values[1]	values[5]	668	1			T183	37		T255	6		T192	49
auto[0]	values[1]	values[6]	306	1			T13	19		T217	14		T252	10
auto[0]	values[1]	values[7]	495	1			T36	49		T187	22		T201	20
auto[0]	values[2]	values[0]	523	1			T36	18		T204	187		T70	27
auto[0]	values[2]	values[1]	695	1			T3	24		T234	2		T20	45
auto[0]	values[2]	values[2]	328	1			T33	20		T36	50		T185	116
auto[0]	values[2]	values[3]	513	1			T32	20		T15	160		T203	18
auto[0]	values[2]	values[4]	500	1			T3	23		T6	78		T8	4
auto[0]	values[2]	values[5]	350	1			T3	23		T211	12		T228	8
auto[0]	values[2]	values[6]	451	1			T77	18		T236	10		T187	21
auto[0]	values[2]	values[7]	705	1			T36	21		T173	21		T152	20
auto[0]	values[3]	values[0]	401	1			T6	22		T215	18		T183	19
auto[0]	values[3]	values[1]	315	1			T3	20		T9	18		T32	20
auto[0]	values[3]	values[2]	523	1			T13	20		T38	34		T216	20
auto[0]	values[3]	values[3]	258	1			T6	66		T219	2		T256	8
auto[0]	values[3]	values[4]	509	1			T3	20		T121	20		T216	25
auto[0]	values[3]	values[5]	460	1			T6	21		T185	20		T63	19
auto[0]	values[3]	values[6]	394	1			T33	23		T15	20		T186	14
auto[0]	values[3]	values[7]	418	1			T15	20		T187	20		T63	20
auto[0]	values[4]	values[0]	137	1			T183	20		T201	20		T152	37
auto[0]	values[4]	values[1]	300	1			T32	25		T15	20		T205	20
auto[0]	values[4]	values[2]	403	1			T3	21		T185	19		T69	33
auto[0]	values[4]	values[3]	505	1			T3	23		T32	21		T204	19
auto[0]	values[4]	values[4]	454	1			T205	20		T201	20		T222	6
auto[0]	values[4]	values[5]	686	1			T13	19		T35	14		T38	20
auto[0]	values[4]	values[6]	566	1			T13	31		T36	20		T237	4
auto[0]	values[4]	values[7]	390	1			T32	26		T173	28		T187	42
auto[0]	values[5]	values[0]	205	1			T105	12		T235	14		T246	2
auto[0]	values[5]	values[1]	415	1			T36	29		T224	2		T257	4
auto[0]	values[5]	values[2]	522	1			T13	22		T33	23		T36	89
auto[0]	values[5]	values[3]	290	1			T5	2		T10	8		T33	20
auto[0]	values[5]	values[4]	573	1			T3	20		T6	20		T13	23
auto[0]	values[5]	values[5]	373	1			T3	21		T15	20		T20	24
auto[0]	values[5]	values[6]	243	1			T6	20		T33	21		T15	24
auto[0]	values[5]	values[7]	502	1			T13	41		T15	19		T198	18
auto[0]	values[6]	values[0]	404	1			T33	19		T15	43		T176	18
auto[0]	values[6]	values[1]	188	1			T2	16		T33	28		T28	24
auto[0]	values[6]	values[2]	286	1			T33	20		T36	20		T185	38
auto[0]	values[6]	values[3]	349	1			T3	19		T33	21		T231	27
auto[0]	values[6]	values[4]	374	1			T6	58		T187	23		T64	16
auto[0]	values[6]	values[5]	277	1			T13	22		T187	67		T201	23
auto[0]	values[6]	values[6]	306	1			T38	26		T151	27		T191	26
auto[0]	values[6]	values[7]	482	1			T183	25		T204	144		T179	16
auto[0]	values[7]	values[0]	686	1			T6	53		T13	22		T140	2
auto[0]	values[7]	values[1]	742	1			T33	21		T80	14		T189	16
auto[0]	values[7]	values[2]	182	1			T6	19		T192	20		T245	24
auto[0]	values[7]	values[3]	378	1			T6	20		T7	22		T206	27
auto[0]	values[7]	values[4]	483	1			T13	24		T32	39		T20	43
auto[0]	values[7]	values[5]	501	1			T134	2		T32	18		T15	20
auto[0]	values[7]	values[6]	424	1			T32	35		T38	58		T243	22
auto[0]	values[7]	values[7]	555	1			T3	19		T241	8		T20	23
auto[1]	values[0]	values[0]	8	1			T6	1		T204	1		T179	2
auto[1]	values[0]	values[1]	7	1			T15	2		T205	1		T70	1
auto[1]	values[0]	values[2]	18	1			T36	3		T212	2		T232	1
auto[1]	values[0]	values[3]	10	1			T15	1		T173	3		T28	1
auto[1]	values[0]	values[4]	4	1			T36	1		T178	1		T258	2
auto[1]	values[0]	values[5]	15	1			T187	2		T28	1		T192	2
auto[1]	values[0]	values[6]	9	1			T32	3		T36	1		T128	1
auto[1]	values[0]	values[7]	10	1			T201	1		T259	1		T42	2
auto[1]	values[1]	values[0]	12	1			T15	5		T127	1		T260	2
auto[1]	values[1]	values[1]	30	1			T6	1		T38	3		T70	3
auto[1]	values[1]	values[2]	27	1			T6	2		T33	1		T173	1
auto[1]	values[1]	values[3]	7	1			T184	1		T261	3		T262	3
auto[1]	values[1]	values[4]	16	1			T216	2		T204	2		T260	2
auto[1]	values[1]	values[5]	5	1			T183	1		T192	1		T259	1
auto[1]	values[1]	values[6]	6	1			T13	1		T121	1		T185	1
auto[1]	values[1]	values[7]	15	1			T36	3		T152	1		T174	1
auto[1]	values[2]	values[0]	14	1			T36	2		T70	2		T263	1
auto[1]	values[2]	values[1]	19	1			T20	3		T63	1		T263	2
auto[1]	values[2]	values[2]	8	1			T185	6		T153	1		T264	1
auto[1]	values[2]	values[3]	11	1			T184	2		T153	3		T265	1
auto[1]	values[2]	values[4]	19	1			T3	2		T202	1		T63	1
auto[1]	values[2]	values[5]	4	1			T63	2		T70	1		T71	1
auto[1]	values[2]	values[6]	8	1			T152	3		T266	1		T267	1
auto[1]	values[2]	values[7]	14	1			T232	1		T249	2		T268	3
auto[1]	values[3]	values[0]	8	1			T6	1		T183	2		T184	2
auto[1]	values[3]	values[1]	5	1			T153	1		T193	1		T127	1
auto[1]	values[3]	values[2]	3	1			T212	2		T269	1		-	-
auto[1]	values[3]	values[3]	1	1			T266	1		-	-		-	-
auto[1]	values[3]	values[4]	13	1			T37	2		T216	1		T201	1
auto[1]	values[3]	values[5]	11	1			T63	1		T269	1		T265	1
auto[1]	values[3]	values[6]	7	1			T33	1		T174	1		T128	3
auto[1]	values[3]	values[7]	5	1			T153	1		T270	1		T271	2
auto[1]	values[4]	values[0]	2	1			T183	1		T152	1		-	-
auto[1]	values[4]	values[1]	4	1			T32	1		T263	1		T272	1
auto[1]	values[4]	values[2]	12	1			T185	1		T69	1		T153	1
auto[1]	values[4]	values[3]	13	1			T204	1		T179	1		T192	1
auto[1]	values[4]	values[4]	10	1			T179	1		T232	2		T273	2
auto[1]	values[4]	values[5]	17	1			T13	1		T35	2		T15	3
auto[1]	values[4]	values[6]	8	1			T245	1		T259	1		T274	2
auto[1]	values[4]	values[7]	8	1			T32	1		T173	1		T212	1
auto[1]	values[5]	values[0]	4	1			T192	1		T262	3		-	-
auto[1]	values[5]	values[1]	4	1			T36	1		T274	2		T271	1
auto[1]	values[5]	values[2]	18	1			T36	2		T251	4		T262	3
auto[1]	values[5]	values[3]	8	1			T152	3		T192	1		T268	2
auto[1]	values[5]	values[4]	10	1			T6	4		T212	1		T269	4
auto[1]	values[5]	values[5]	7	1			T187	3		T178	1		T275	1
auto[1]	values[5]	values[6]	8	1			T33	2		T15	1		T271	1
auto[1]	values[5]	values[7]	8	1			T13	2		T15	1		T179	1
auto[1]	values[6]	values[0]	14	1			T33	1		T15	1		T185	5
auto[1]	values[6]	values[1]	4	1			T28	1		T271	3		-	-
auto[1]	values[6]	values[2]	5	1			T185	2		T127	1		T268	2
auto[1]	values[6]	values[3]	14	1			T3	1		T231	1		T187	1
auto[1]	values[6]	values[4]	11	1			T6	4		T192	1		T276	5
auto[1]	values[6]	values[5]	10	1			T187	3		T201	2		T184	4
auto[1]	values[6]	values[6]	10	1			T38	1		T191	1		T192	1
auto[1]	values[6]	values[7]	10	1			T204	4		T179	4		T232	1
auto[1]	values[7]	values[0]	18	1			T6	3		T216	1		T192	3
auto[1]	values[7]	values[1]	22	1			T33	2		T189	2		T247	2
auto[1]	values[7]	values[2]	7	1			T6	1		T277	2		T258	2
auto[1]	values[7]	values[3]	11	1			T206	1		T127	2		T278	2
auto[1]	values[7]	values[4]	10	1			T32	1		T20	1		T70	2
auto[1]	values[7]	values[5]	10	1			T32	2		T209	2		T173	1
auto[1]	values[7]	values[6]	14	1			T32	2		T38	2		T184	1
auto[1]	values[7]	values[7]	17	1			T3	1		T20	1		T70	1