Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1757

1

T1

8

T3

9

T4

6

auto[1]

1879

1

T1

3

T3

9

T4

4

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1999

1

T3

13

T6

13

T13

45

auto[1]

1637

1

T1

11

T3

5

T4

10

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2884

1

T1

11

T3

11

T4

10

auto[1]

752

1

T3

7

T6

6

T13

13

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	775	1			T1	3		T3	9		T4	2
valid[1]	698	1			T1	1		T3	3		T4	2
valid[2]	732	1			T1	2		T3	4		T4	2
valid[3]	725	1			T1	3		T3	1		T4	1
valid[4]	706	1			T1	2		T3	1		T4	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	115	1			T3	1		T6	1		T13	2
auto[0]	auto[0]	valid[0]	auto[1]	167	1			T1	1		T13	1		T297	1
auto[0]	auto[0]	valid[1]	auto[0]	122	1			T3	1		T6	2		T13	3
auto[0]	auto[0]	valid[1]	auto[1]	159	1			T4	2		T26	2		T33	1
auto[0]	auto[0]	valid[2]	auto[0]	101	1			T6	1		T13	3		T14	2
auto[0]	auto[0]	valid[2]	auto[1]	180	1			T1	2		T3	1		T4	2
auto[0]	auto[0]	valid[3]	auto[0]	136	1			T13	3		T32	1		T14	6
auto[0]	auto[0]	valid[3]	auto[1]	160	1			T1	3		T13	1		T26	1
auto[0]	auto[0]	valid[4]	auto[0]	131	1			T13	2		T24	1		T14	3
auto[0]	auto[0]	valid[4]	auto[1]	115	1			T1	2		T4	2		T26	2
auto[0]	auto[1]	valid[0]	auto[0]	124	1			T3	2		T13	2		T36	2
auto[0]	auto[1]	valid[0]	auto[1]	197	1			T1	2		T3	2		T4	2
auto[0]	auto[1]	valid[1]	auto[0]	118	1			T13	5		T14	2		T33	1
auto[0]	auto[1]	valid[1]	auto[1]	167	1			T1	1		T26	1		T33	1
auto[0]	auto[1]	valid[2]	auto[0]	129	1			T3	1		T6	1		T13	3
auto[0]	auto[1]	valid[2]	auto[1]	169	1			T3	1		T13	1		T26	1
auto[0]	auto[1]	valid[3]	auto[0]	119	1			T3	1		T6	1		T13	2
auto[0]	auto[1]	valid[3]	auto[1]	165	1			T4	1		T159	1		T297	1
auto[0]	auto[1]	valid[4]	auto[0]	152	1			T6	1		T13	7		T32	2
auto[0]	auto[1]	valid[4]	auto[1]	158	1			T3	1		T4	1		T26	2
auto[1]	auto[0]	valid[0]	auto[0]	91	1			T3	3		T13	2		T33	1
auto[1]	auto[0]	valid[1]	auto[0]	65	1			T3	2		T13	2		T27	1
auto[1]	auto[0]	valid[2]	auto[0]	76	1			T3	1		T14	2		T33	2
auto[1]	auto[0]	valid[3]	auto[0]	69	1			T13	1		T288	1		T194	1
auto[1]	auto[0]	valid[4]	auto[0]	70	1			T6	1		T13	3		T14	1
auto[1]	auto[1]	valid[0]	auto[0]	81	1			T3	1		T6	1		T13	1
auto[1]	auto[1]	valid[1]	auto[0]	67	1			T6	1		T13	1		T24	2
auto[1]	auto[1]	valid[2]	auto[0]	77	1			T25	1		T14	1		T36	1
auto[1]	auto[1]	valid[3]	auto[0]	76	1			T6	2		T13	1		T25	1
auto[1]	auto[1]	valid[4]	auto[0]	80	1			T6	1		T13	2		T14	4

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal