Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	795	1			T6	10		T13	4		T14	4
all_values[1]	795	1			T6	10		T13	4		T14	4
all_values[2]	795	1			T6	10		T13	4		T14	4
all_values[3]	795	1			T6	10		T13	4		T14	4
all_values[4]	795	1			T6	10		T13	4		T14	4
all_values[5]	795	1			T6	10		T13	4		T14	4
all_values[6]	795	1			T6	10		T13	4		T14	4
all_values[7]	795	1			T6	10		T13	4		T14	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3484

1

T6

39

T13

22

T14

16

auto[1]

2876

1

T6

41

T13

10

T14

16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2465

1

T6

37

T13

8

T14

11

auto[1]

3895

1

T6

43

T13

24

T14

21

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3548

1

T6

49

T13

16

T14

17

auto[1]

2812

1

T6

31

T13

16

T14

15

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	140	1			T6	1		T15	3		T16	2
all_values[0]	auto[0]	auto[0]	auto[1]	85	1			T6	2		T15	1		T16	1
all_values[0]	auto[0]	auto[1]	auto[0]	116	1			T14	2		T15	3		T16	2
all_values[0]	auto[0]	auto[1]	auto[1]	87	1			T6	2		T13	1		T15	2
all_values[0]	auto[1]	auto[0]	auto[1]	201	1			T6	2		T13	1		T14	2
all_values[0]	auto[1]	auto[1]	auto[1]	166	1			T6	3		T13	2		T15	4
all_values[1]	auto[0]	auto[0]	auto[0]	178	1			T13	2		T15	3		T16	2
all_values[1]	auto[0]	auto[0]	auto[1]	79	1			T13	1		T14	1		T15	2
all_values[1]	auto[0]	auto[1]	auto[0]	127	1			T6	3		T14	2		T18	1
all_values[1]	auto[0]	auto[1]	auto[1]	76	1			T6	2		T15	1		T18	4
all_values[1]	auto[1]	auto[0]	auto[1]	176	1			T6	3		T13	1		T15	5
all_values[1]	auto[1]	auto[1]	auto[1]	159	1			T6	2		T14	1		T15	3
all_values[2]	auto[0]	auto[0]	auto[0]	172	1			T6	6		T14	1		T15	5
all_values[2]	auto[0]	auto[0]	auto[1]	90	1			T14	1		T18	2		T19	2
all_values[2]	auto[0]	auto[1]	auto[0]	128	1			T6	2		T15	4		T16	2
all_values[2]	auto[0]	auto[1]	auto[1]	58	1			T13	1		T16	1		T18	1
all_values[2]	auto[1]	auto[0]	auto[1]	210	1			T6	2		T13	3		T14	2
all_values[2]	auto[1]	auto[1]	auto[1]	137	1			T15	1		T16	1		T18	3
all_values[3]	auto[0]	auto[0]	auto[0]	161	1			T6	5		T15	2		T16	5
all_values[3]	auto[0]	auto[0]	auto[1]	81	1			T15	2		T18	1		T21	1
all_values[3]	auto[0]	auto[1]	auto[0]	115	1			T6	2		T14	3		T15	5
all_values[3]	auto[0]	auto[1]	auto[1]	77	1			T13	1		T18	2		T19	1
all_values[3]	auto[1]	auto[0]	auto[1]	188	1			T6	1		T13	3		T15	4
all_values[3]	auto[1]	auto[1]	auto[1]	173	1			T6	2		T14	1		T15	1
all_values[4]	auto[0]	auto[0]	auto[0]	164	1			T6	3		T13	1		T15	5
all_values[4]	auto[0]	auto[0]	auto[1]	75	1			T6	2		T13	1		T16	1
all_values[4]	auto[0]	auto[1]	auto[0]	123	1			T14	1		T15	4		T16	1
all_values[4]	auto[0]	auto[1]	auto[1]	77	1			T6	1		T14	1		T15	2
all_values[4]	auto[1]	auto[0]	auto[1]	216	1			T6	3		T13	2		T15	3
all_values[4]	auto[1]	auto[1]	auto[1]	140	1			T6	1		T14	2		T16	2
all_values[5]	auto[0]	auto[0]	auto[0]	231	1			T6	2		T14	1		T15	6
all_values[5]	auto[0]	auto[1]	auto[0]	220	1			T6	3		T13	2		T15	1
all_values[5]	auto[1]	auto[0]	auto[1]	191	1			T6	3		T13	1		T14	2
all_values[5]	auto[1]	auto[1]	auto[1]	153	1			T6	2		T13	1		T14	1
all_values[6]	auto[0]	auto[0]	auto[0]	166	1			T13	1		T15	3		T16	3
all_values[6]	auto[0]	auto[0]	auto[1]	66	1			T6	2		T13	2		T14	1
all_values[6]	auto[0]	auto[1]	auto[0]	134	1			T6	5		T14	1		T15	4
all_values[6]	auto[0]	auto[1]	auto[1]	83	1			T15	1		T16	2		T18	2
all_values[6]	auto[1]	auto[0]	auto[1]	180	1			T6	2		T13	1		T14	2
all_values[6]	auto[1]	auto[1]	auto[1]	166	1			T6	1		T15	2		T16	2
all_values[7]	auto[0]	auto[0]	auto[0]	155	1			T13	1		T15	3		T18	1
all_values[7]	auto[0]	auto[0]	auto[1]	78	1			T13	1		T14	1		T15	1
all_values[7]	auto[0]	auto[1]	auto[0]	135	1			T6	5		T13	1		T15	1
all_values[7]	auto[0]	auto[1]	auto[1]	71	1			T6	1		T14	1		T15	2
all_values[7]	auto[1]	auto[0]	auto[1]	201	1			T14	2		T15	2		T16	4
all_values[7]	auto[1]	auto[1]	auto[1]	155	1			T6	4		T13	1		T15	5

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal