Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51139

1

T3

374

T6

214

T12

3

auto[1]

16403

1

T1

11

T3

88

T4

10

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49156

1

T1

11

T3

325

T4

10

auto[1]

18386

1

T3

137

T6

82

T12

1

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34735	1			T1	11		T3	232		T4	10
others[1]	5653	1			T3	46		T6	25		T12	1
others[2]	5685	1			T3	35		T6	9		T13	115
others[3]	6578	1			T3	43		T6	16		T13	129
interest[1]	3683	1			T3	24		T6	10		T13	66
interest[4]	22806	1			T1	11		T3	142		T4	10
interest[64]	11208	1			T3	82		T6	46		T13	206

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16849	1			T3	111		T6	76		T12	2
auto[0]	auto[0]	others[1]	2716	1			T3	18		T6	8		T13	73
auto[0]	auto[0]	others[2]	2704	1			T3	12		T6	3		T13	70
auto[0]	auto[0]	others[3]	3239	1			T3	29		T6	10		T13	76
auto[0]	auto[0]	interest[1]	1788	1			T3	13		T6	6		T13	38
auto[0]	auto[0]	interest[4]	10991	1			T3	73		T6	46		T12	2
auto[0]	auto[0]	interest[64]	5457	1			T3	54		T6	29		T13	122
auto[0]	auto[1]	others[0]	8463	1			T1	11		T3	43		T4	10
auto[0]	auto[1]	others[1]	1360	1			T3	12		T6	2		T13	8
auto[0]	auto[1]	others[2]	1360	1			T3	11		T6	1		T13	5
auto[0]	auto[1]	others[3]	1591	1			T3	4		T6	2		T13	13
auto[0]	auto[1]	interest[1]	899	1			T3	5		T6	1		T13	7
auto[0]	auto[1]	interest[4]	5638	1			T1	11		T3	26		T4	10
auto[0]	auto[1]	interest[64]	2730	1			T3	13		T6	7		T13	16
auto[1]	auto[0]	others[0]	9423	1			T3	78		T6	45		T13	213
auto[1]	auto[0]	others[1]	1577	1			T3	16		T6	15		T12	1
auto[1]	auto[0]	others[2]	1621	1			T3	12		T6	5		T13	40
auto[1]	auto[0]	others[3]	1748	1			T3	10		T6	4		T13	40
auto[1]	auto[0]	interest[1]	996	1			T3	6		T6	3		T13	21
auto[1]	auto[0]	interest[4]	6177	1			T3	43		T6	26		T13	128
auto[1]	auto[0]	interest[64]	3021	1			T3	15		T6	10		T13	68

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal