Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2573732	1			T1	1		T2	1		T3	6683
all_values[1]	2573732	1			T1	1		T2	1		T3	6683
all_values[2]	2573732	1			T1	1		T2	1		T3	6683
all_values[3]	2573732	1			T1	1		T2	1		T3	6683
all_values[4]	2573732	1			T1	1		T2	1		T3	6683
all_values[5]	2573732	1			T1	1		T2	1		T3	6683
all_values[6]	2573732	1			T1	1		T2	1		T3	6683
all_values[7]	2573732	1			T1	1		T2	1		T3	6683

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19996947

1

T1

8

T2

8

T3

53464

auto[1]

592909

1

T10

65

T15

59

T16

70

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20563276

1

T1

8

T2

8

T3

53464

auto[1]

26580

1

T10

150

T43

2

T15

73

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2471060	1			T1	1		T2	1		T3	6683
all_values[0]	auto[0]	auto[1]	12610	1			T10	56		T43	2		T15	9
all_values[0]	auto[1]	auto[0]	89577	1			T10	5		T15	2		T16	2
all_values[0]	auto[1]	auto[1]	485	1			T10	2		T15	2		T16	1
all_values[1]	auto[0]	auto[0]	2540092	1			T1	1		T2	1		T3	6683
all_values[1]	auto[0]	auto[1]	8323	1			T10	53		T15	4		T42	88
all_values[1]	auto[1]	auto[0]	25066	1			T10	6		T15	6		T16	6
all_values[1]	auto[1]	auto[1]	251	1			T15	4		T16	2		T17	1
all_values[2]	auto[0]	auto[0]	2497001	1			T1	1		T2	1		T3	6683
all_values[2]	auto[0]	auto[1]	2922	1			T10	3		T15	8		T42	82
all_values[2]	auto[1]	auto[0]	73505	1			T10	8		T15	1		T16	7
all_values[2]	auto[1]	auto[1]	304	1			T10	2		T15	7		T16	2
all_values[3]	auto[0]	auto[0]	2439180	1			T1	1		T2	1		T3	6683
all_values[3]	auto[0]	auto[1]	168	1			T10	3		T15	7		T16	4
all_values[3]	auto[1]	auto[0]	134214	1			T10	6		T15	2		T16	7
all_values[3]	auto[1]	auto[1]	170	1			T10	5		T15	5		T16	4
all_values[4]	auto[0]	auto[0]	2504637	1			T1	1		T2	1		T3	6683
all_values[4]	auto[0]	auto[1]	195	1			T10	4		T15	4		T16	4
all_values[4]	auto[1]	auto[0]	68741	1			T10	3		T15	6		T16	2
all_values[4]	auto[1]	auto[1]	159	1			T10	3		T15	2		T16	6
all_values[5]	auto[0]	auto[0]	2473972	1			T1	1		T2	1		T3	6683
all_values[5]	auto[0]	auto[1]	163	1			T10	3		T15	5		T16	5
all_values[5]	auto[1]	auto[0]	99463	1			T10	5		T15	7		T16	4
all_values[5]	auto[1]	auto[1]	134	1			T10	1		T15	2		T16	5
all_values[6]	auto[0]	auto[0]	2501337	1			T1	1		T2	1		T3	6683
all_values[6]	auto[0]	auto[1]	181	1			T10	3		T15	6		T16	4
all_values[6]	auto[1]	auto[0]	72030	1			T10	2		T15	5		T16	2
all_values[6]	auto[1]	auto[1]	184	1			T10	5		T15	1		T16	9
all_values[7]	auto[0]	auto[0]	2544941	1			T1	1		T2	1		T3	6683
all_values[7]	auto[0]	auto[1]	165	1			T10	2		T15	5		T16	5
all_values[7]	auto[1]	auto[0]	28460	1			T10	7		T15	5		T16	8
all_values[7]	auto[1]	auto[1]	166	1			T10	5		T15	2		T16	3