Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35678	1			T1	2		T3	11		T5	2
auto[SpiFlashAddrCfg]	7769	1			T2	3		T3	1		T8	6
auto[SpiFlashAddr3b]	9753	1			T1	2		T3	1		T10	47
auto[SpiFlashAddr4b]	7852	1			T3	7		T10	32		T11	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34532

1

T1

4

T2

3

T3

14

auto[1]

26520

1

T3

6

T8

14

T10

84

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32176

1

T2

1

T3

13

T5

2

auto[1]

28876

1

T1

4

T2

2

T3

7

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	40561	1			T1	2		T3	13		T5	2
values[1]	1112	1			T3	1		T8	4		T10	3
values[2]	1625	1			T3	3		T10	16		T11	2
values[3]	1536	1			T10	12		T13	10		T36	5
values[4]	1496	1			T10	4		T13	9		T36	14
values[5]	1580	1			T3	1		T10	7		T13	14
values[6]	1478	1			T10	5		T11	4		T13	6
values[7]	1560	1			T2	2		T10	7		T13	12
values[8]	10104	1			T1	2		T2	1		T3	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28334

1

T1

4

T5

2

T8

14

auto[1]

32718

1

T2

3

T3

20

T36

280

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

57627

1

T1

4

T2

3

T3

18

write

3425

1

T3

2

T10

11

T13

21

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20104

1

T2

2

T3

11

T5

2

valids[0x1]

40948

1

T1

4

T2

1

T3

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1650	1			T10	6		T13	5		T36	16
internal_process_ops[0x5a]	1687	1			T1	2		T3	1		T10	12
internal_process_ops[0x05]	20983	1			T1	2		T8	2		T10	72
internal_process_ops[0x35]	1647	1			T3	1		T10	7		T13	9
internal_process_ops[0x15]	1750	1			T3	2		T10	6		T11	2
internal_process_ops[0x03]	1013	1			T2	1		T10	4		T13	8
internal_process_ops[0x0b]	1066	1			T10	5		T13	14		T25	4
internal_process_ops[0x3b]	1068	1			T3	1		T10	12		T12	2
internal_process_ops[0x6b]	1063	1			T2	2		T10	5		T13	5
internal_process_ops[0xbb]	1049	1			T10	4		T12	6		T13	11
internal_process_ops[0xeb]	1082	1			T5	2		T10	3		T11	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59361

1

T1

4

T2

3

T3

18

auto[1]

1691

1

T3

2

T10

1

T13

12

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58581

1

T1

4

T2

3

T3

20

auto[1]

2471

1

T10

7

T13

20

T36

17

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9062

1

T1

2

T5

2

T10

102

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5653

1

T8

8

T10

22

T11

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1923

1

T10

17

T12

6

T13

14

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1710

1

T8

6

T10

16

T11

10

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2503

1

T1

2

T10

22

T13

26

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2156

1

T10

25

T11

2

T13

38

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2007

1

T10

14

T12

2

T13

18

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1777

1

T10

15

T11

2

T13

21

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

111

1

T10

2

T13

2

T155

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

107

1

T13

1

T37

3

T49

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

91

1

T10

3

T13

1

T37

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

115

1

T10

1

T13

2

T156

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

103

1

T10

2

T13

2

T37

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

80

1

T13

1

T43

1

T44

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

102

1

T13

1

T37

7

T43

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

113

1

T13

1

T44

1

T46

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

113

1

T13

1

T43

2

T48

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

99

1

T13

1

T37

2

T43

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

75

1

T13

2

T37

2

T46

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

84

1

T13

1

T37

1

T43

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

78

1

T10

1

T45

1

T157

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

79

1

T13

4

T45

1

T48

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

97

1

T10

2

T43

1

T158

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

96

1

T13

1

T43

5

T48

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11877

1

T3

9

T36

85

T42

32

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8184

1

T3

2

T36

30

T42

14

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1593

1

T2

3

T3

1

T36

26

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1686

1

T36

28

T42

6

T51

5

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2113

1

T3

1

T36

18

T42

5

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2131

1

T36

25

T42

8

T51

8

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1714

1

T3

3

T36

30

T42

11

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1538

1

T3

2

T36

21

T42

9

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

122

1

T42

2

T51

1

T66

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

125

1

T36

1

T66

1

T89

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

104

1

T36

2

T42

7

T52

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

127

1

T36

2

T89

2

T81

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

118

1

T66

1

T89

1

T81

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

113

1

T52

1

T159

2

T18

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

127

1

T36

1

T159

1

T160

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

101

1

T52

1

T66

3

T89

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

128

1

T36

3

T42

1

T52

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

111

1

T81

1

T161

2

T31

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

136

1

T36

2

T51

1

T89

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

104

1

T51

1

T160

3

T18

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

116

1

T89

1

T159

2

T160

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

137

1

T36

1

T42

1

T159

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

113

1

T36

3

T66

5

T159

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

100

1

T3

2

T36

2

T159

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3721	1			T5	2		T8	2		T10	30
auto[0]	values[0]	valids[0x1]	13813	1			T1	2		T8	4		T10	117
auto[0]	values[1]	valids[0x1]	564	1			T8	4		T10	3		T11	2
auto[0]	values[2]	valids[0x0]	535	1			T10	10		T13	3		T37	2
auto[0]	values[2]	valids[0x1]	331	1			T10	6		T11	2		T13	3
auto[0]	values[3]	valids[0x0]	540	1			T10	3		T13	3		T37	4
auto[0]	values[3]	valids[0x1]	284	1			T10	9		T13	7		T37	6
auto[0]	values[4]	valids[0x0]	486	1			T10	3		T13	7		T37	3
auto[0]	values[4]	valids[0x1]	254	1			T10	1		T13	2		T37	1
auto[0]	values[5]	valids[0x0]	560	1			T10	7		T13	8		T37	5
auto[0]	values[5]	valids[0x1]	303	1			T13	6		T25	4		T37	1
auto[0]	values[6]	valids[0x0]	508	1			T10	3		T13	4		T37	3
auto[0]	values[6]	valids[0x1]	295	1			T10	2		T11	4		T13	2
auto[0]	values[7]	valids[0x0]	529	1			T10	2		T13	7		T26	2
auto[0]	values[7]	valids[0x1]	326	1			T10	5		T13	5		T37	6
auto[0]	values[8]	valids[0x0]	3401	1			T8	4		T10	24		T11	4
auto[0]	values[8]	valids[0x1]	1884	1			T1	2		T10	19		T11	2
auto[1]	values[0]	valids[0x0]	4478	1			T3	8		T36	62		T42	21
auto[1]	values[0]	valids[0x1]	18549	1			T3	5		T36	81		T42	38
auto[1]	values[1]	valids[0x1]	548	1			T3	1		T36	14		T42	2
auto[1]	values[2]	valids[0x0]	427	1			T3	1		T36	2		T42	4
auto[1]	values[2]	valids[0x1]	332	1			T3	2		T36	6		T52	2
auto[1]	values[3]	valids[0x0]	418	1			T36	4		T42	1		T51	1
auto[1]	values[3]	valids[0x1]	294	1			T36	1		T42	1		T51	6
auto[1]	values[4]	valids[0x0]	454	1			T36	9		T51	3		T52	4
auto[1]	values[4]	valids[0x1]	302	1			T36	5		T52	5		T89	3
auto[1]	values[5]	valids[0x0]	435	1			T36	4		T42	3		T52	3
auto[1]	values[5]	valids[0x1]	282	1			T3	1		T42	5		T52	3
auto[1]	values[6]	valids[0x0]	390	1			T36	4		T42	3		T52	3
auto[1]	values[6]	valids[0x1]	285	1			T36	1		T42	2		T52	5
auto[1]	values[7]	valids[0x0]	434	1			T2	2		T36	3		T51	2
auto[1]	values[7]	valids[0x1]	271	1			T36	1		T42	2		T52	3
auto[1]	values[8]	valids[0x0]	2788	1			T3	2		T36	55		T42	16
auto[1]	values[8]	valids[0x1]	2031	1			T2	1		T36	28		T42	12