Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3420433

1

T1

946

T2

53

T3

1541

auto[1]

30902

1

T10

64

T13

144

T36

114

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1042096

1

T1

946

T2

53

T3

5

auto[1]

2409239

1

T3

1536

T10

14467

T13

24635

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	634556	1			T1	2		T2	33		T4	41
auto[524288:1048575]	447814	1			T1	88		T3	514		T10	265
auto[1048576:1572863]	395395	1			T2	4		T10	2061		T12	20
auto[1572864:2097151]	373863	1			T1	378		T2	15		T4	1
auto[2097152:2621439]	391454	1			T1	154		T3	512		T10	6134
auto[2621440:3145727]	361033	1			T1	39		T3	515		T10	933
auto[3145728:3670015]	440754	1			T1	283		T4	1		T10	14
auto[3670016:4194303]	406466	1			T1	2		T2	1		T10	19

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2445776

1

T1

23

T2

5

T3

1541

auto[1]

1005559

1

T1

923

T2

48

T4

41

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3059786

1

T1

946

T2

53

T3

1029

auto[1]

391549

1

T3

512

T10

2476

T13

6779

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	187173	1			T1	2		T2	33		T4	41
auto[0]	auto[0]	auto[0:524287]	auto[1]	383050	1			T13	4609		T36	1		T37	1832
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	148190	1			T1	88		T3	2		T10	4
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	240684	1			T3	512		T10	256		T36	3270
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	128840	1			T2	4		T10	2		T12	20
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	222629	1			T10	512		T13	5523		T36	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	123527	1			T1	378		T2	15		T4	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	210403	1			T10	5077		T13	258		T36	2221
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	97733	1			T1	154		T10	6		T13	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	252465	1			T10	6111		T13	4824		T36	128
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	98195	1			T1	39		T3	3		T10	6
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	211647	1			T3	512		T10	2		T13	137
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	133367	1			T1	283		T4	1		T10	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	241124	1			T10	1		T13	130		T37	2482
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	110399	1			T1	2		T2	1		T10	4
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	245486	1			T10	1		T13	2295		T36	3079
auto[0]	auto[1]	auto[0:524287]	auto[0]	2093	1			T10	1		T36	7		T43	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	58397	1			T43	128		T48	4		T157	1146
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1766	1			T10	3		T36	25		T37	6
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	52834	1			T10	1		T46	256		T48	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1686	1			T10	7		T13	6		T37	7
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	38744	1			T10	1529		T13	2190		T43	385
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1189	1			T10	1		T37	39		T51	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	35594	1			T13	2068		T37	5		T51	128
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	521	1			T10	1		T13	1		T36	6
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	37538	1			T3	512		T42	257		T52	512
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1213	1			T10	1		T13	7		T36	42
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	46231	1			T10	920		T13	2346		T36	512
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1196	1			T13	3		T36	22		T44	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	60471	1			T13	130		T44	256		T52	395
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	767	1			T13	2		T36	34		T51	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	45281	1			T13	1		T36	1183		T51	260
auto[1]	auto[0]	auto[0:524287]	auto[0]	468	1			T13	2		T36	6		T37	5
auto[1]	auto[0]	auto[0:524287]	auto[1]	2635	1			T13	15		T37	75		T43	5
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	481	1			T36	32		T37	7		T66	4
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3046	1			T36	8		T45	79		T49	256
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	380	1			T13	4		T36	16		T37	9
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2404	1			T13	37		T43	40		T44	8
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	382	1			T10	1		T13	2		T36	13
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2270	1			T10	6		T13	7		T43	15
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	455	1			T10	1		T37	15		T46	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2285	1			T10	15		T46	15		T159	17
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	412	1			T10	1		T13	4		T36	7
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2834	1			T10	3		T13	29		T44	53
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	532	1			T10	1		T13	2		T36	9
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	3038	1			T10	10		T13	9		T37	135
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	376	1			T10	1		T13	1		T36	12
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2876	1			T10	13		T13	7		T43	5
auto[1]	auto[1]	auto[0:524287]	auto[0]	99	1			T48	2		T169	11		T198	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	641	1			T48	61		T169	37		T198	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	134	1			T10	1		T48	3		T82	5
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	679	1			T48	63		T30	7		T196	10
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	95	1			T10	1		T36	6		T43	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	617	1			T10	10		T43	1		T42	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	60	1			T48	1		T19	2		T211	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	438	1			T48	17		T19	3		T211	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	58	1			T42	1		T46	1		T183	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	399	1			T46	24		T183	1		T184	33
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	74	1			T13	2		T36	2		T37	4
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	427	1			T13	10		T184	5		T161	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	98	1			T13	2		T36	3		T89	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	928	1			T13	4		T89	11		T47	10
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	137	1			T13	1		T46	1		T158	7
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	1144	1			T13	6		T46	22		T82	63

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2034880	1			T1	23		T2	5		T3	1029
auto[0]	auto[0]	auto[1]	1000032	1			T1	923		T2	48		T4	41
auto[0]	auto[1]	auto[0]	380652	1			T3	512		T10	2464		T13	6752
auto[0]	auto[1]	auto[1]	4869	1			T13	2		T212	7		T46	1
auto[1]	auto[0]	auto[0]	24341	1			T10	52		T13	108		T36	93
auto[1]	auto[0]	auto[1]	533	1			T13	11		T36	10		T37	12
auto[1]	auto[1]	auto[0]	5903	1			T10	12		T13	22		T36	9
auto[1]	auto[1]	auto[1]	125	1			T13	3		T36	2		T42	1