Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2573732	1			T1	1		T2	1		T3	6683
all_pins[1]	2573732	1			T1	1		T2	1		T3	6683
all_pins[2]	2573732	1			T1	1		T2	1		T3	6683
all_pins[3]	2573732	1			T1	1		T2	1		T3	6683
all_pins[4]	2573732	1			T1	1		T2	1		T3	6683
all_pins[5]	2573732	1			T1	1		T2	1		T3	6683
all_pins[6]	2573732	1			T1	1		T2	1		T3	6683
all_pins[7]	2573732	1			T1	1		T2	1		T3	6683

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20516395	1			T1	8		T2	8		T3	53464
values[0x1]	73461	1			T10	23		T15	25		T16	32
transitions[0x0=>0x1]	72797	1			T10	14		T15	18		T16	18
transitions[0x1=>0x0]	72804	1			T10	15		T15	18		T16	18

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2573220	1			T1	1		T2	1		T3	6683
all_pins[0]	values[0x1]	512	1			T10	2		T15	2		T16	1
all_pins[0]	transitions[0x0=>0x1]	364	1			T10	2		T15	2		T16	1
all_pins[0]	transitions[0x1=>0x0]	125	1			T15	4		T16	2		T18	3
all_pins[1]	values[0x0]	2573459	1			T1	1		T2	1		T3	6683
all_pins[1]	values[0x1]	273	1			T15	4		T16	2		T17	1
all_pins[1]	transitions[0x0=>0x1]	229	1			T15	2		T16	2		T17	1
all_pins[1]	transitions[0x1=>0x0]	270	1			T10	2		T15	5		T16	2
all_pins[2]	values[0x0]	2573418	1			T1	1		T2	1		T3	6683
all_pins[2]	values[0x1]	314	1			T10	2		T15	7		T16	2
all_pins[2]	transitions[0x0=>0x1]	269	1			T10	2		T15	5		T16	2
all_pins[2]	transitions[0x1=>0x0]	125	1			T10	5		T15	3		T16	4
all_pins[3]	values[0x0]	2573562	1			T1	1		T2	1		T3	6683
all_pins[3]	values[0x1]	170	1			T10	5		T15	5		T16	4
all_pins[3]	transitions[0x0=>0x1]	118	1			T10	3		T15	3		T16	1
all_pins[3]	transitions[0x1=>0x0]	107	1			T10	1		T16	3		T17	1
all_pins[4]	values[0x0]	2573573	1			T1	1		T2	1		T3	6683
all_pins[4]	values[0x1]	159	1			T10	3		T15	2		T16	6
all_pins[4]	transitions[0x0=>0x1]	125	1			T10	2		T15	2		T16	3
all_pins[4]	transitions[0x1=>0x0]	1236	1			T15	2		T16	2		T17	3
all_pins[5]	values[0x0]	2572462	1			T1	1		T2	1		T3	6683
all_pins[5]	values[0x1]	1270	1			T10	1		T15	2		T16	5
all_pins[5]	transitions[0x0=>0x1]	1031	1			T15	1		T16	1		T17	1
all_pins[5]	transitions[0x1=>0x0]	70358	1			T10	4		T16	5		T17	2
all_pins[6]	values[0x0]	2503135	1			T1	1		T2	1		T3	6683
all_pins[6]	values[0x1]	70597	1			T10	5		T15	1		T16	9
all_pins[6]	transitions[0x0=>0x1]	70547	1			T10	3		T15	1		T16	6
all_pins[6]	transitions[0x1=>0x0]	116	1			T10	3		T15	2		T17	2
all_pins[7]	values[0x0]	2573566	1			T1	1		T2	1		T3	6683
all_pins[7]	values[0x1]	166	1			T10	5		T15	2		T16	3
all_pins[7]	transitions[0x0=>0x1]	114	1			T10	2		T15	2		T16	2
all_pins[7]	transitions[0x1=>0x0]	467	1			T15	2		T17	2		T18	3