Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16265

1

T1

4

T5

2

T10

160

auto[1]

12069

1

T8

14

T10

84

T11

20

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4185	1			T13	131		T37	40		T43	91
values[1]	3387	1			T10	20		T13	52		T25	4
values[2]	3243	1			T10	65		T37	40		T43	20
values[3]	3221	1			T10	20		T11	20		T13	20
values[4]	3862	1			T10	87		T37	40		T80	4
values[5]	3307	1			T8	14		T10	32		T37	40
values[6]	3668	1			T10	20		T13	51		T37	40
values[7]	3461	1			T1	4		T5	2		T12	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3459	1			T10	65		T11	20		T13	102
values[1]	3396	1			T10	56		T13	32		T25	4
values[2]	3844	1			T1	4		T5	2		T10	20
values[3]	3818	1			T43	20		T46	20		T48	187
values[4]	3015	1			T10	52		T13	20		T26	16
values[5]	3536	1			T8	14		T12	8		T13	68
values[6]	3675	1			T43	89		T46	70		T213	10
values[7]	3591	1			T10	51		T13	120		T37	40

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	504	1			T13	20		T44	16		T158	11
auto[0]	values[0]	values[1]	234	1			T37	10		T170	12		T158	9
auto[0]	values[0]	values[2]	278	1			T43	13		T44	13		T182	16
auto[0]	values[0]	values[3]	564	1			T46	13		T48	132		T157	13
auto[0]	values[0]	values[4]	240	1			T46	11		T157	51		T184	11
auto[0]	values[0]	values[5]	220	1			T37	10		T214	2		T172	6
auto[0]	values[0]	values[6]	276	1			T43	55		T46	9		T48	7
auto[0]	values[0]	values[7]	256	1			T13	39		T158	7		T182	14
auto[0]	values[1]	values[0]	189	1			T13	7		T37	3		T49	23
auto[0]	values[1]	values[1]	349	1			T13	16		T25	4		T78	12
auto[0]	values[1]	values[2]	234	1			T10	9		T48	15		T30	18
auto[0]	values[1]	values[3]	231	1			T82	11		T215	22		T152	12
auto[0]	values[1]	values[4]	175	1			T48	11		T49	11		T82	15
auto[0]	values[1]	values[5]	161	1			T171	16		T131	11		T133	14
auto[0]	values[1]	values[6]	400	1			T48	122		T82	11		T182	28
auto[0]	values[1]	values[7]	272	1			T184	2		T82	8		T178	13
auto[0]	values[2]	values[0]	188	1			T10	37		T45	9		T82	9
auto[0]	values[2]	values[1]	200	1			T10	16		T17	61		T158	14
auto[0]	values[2]	values[2]	307	1			T37	10		T47	22		T157	26
auto[0]	values[2]	values[3]	223	1			T43	14		T178	14		T189	8
auto[0]	values[2]	values[4]	85	1			T37	14		T196	12		T126	12
auto[0]	values[2]	values[5]	233	1			T158	15		T191	14		T185	12
auto[0]	values[2]	values[6]	166	1			T47	13		T30	11		T152	21
auto[0]	values[2]	values[7]	242	1			T184	40		T176	17		T216	12
auto[0]	values[3]	values[0]	139	1			T10	13		T46	23		T173	11
auto[0]	values[3]	values[1]	306	1			T43	12		T46	34		T49	14
auto[0]	values[3]	values[2]	131	1			T37	11		T176	13		T83	10
auto[0]	values[3]	values[3]	183	1			T217	8		T83	15		T190	22
auto[0]	values[3]	values[4]	187	1			T218	2		T82	11		T30	5
auto[0]	values[3]	values[5]	309	1			T44	13		T45	17		T46	12
auto[0]	values[3]	values[6]	289	1			T43	17		T213	10		T183	21
auto[0]	values[3]	values[7]	331	1			T13	11		T43	12		T46	10
auto[0]	values[4]	values[0]	329	1			T184	13		T182	24		T176	10
auto[0]	values[4]	values[1]	432	1			T10	28		T158	9		T185	15
auto[0]	values[4]	values[2]	251	1			T157	12		T187	6		T181	17
auto[0]	values[4]	values[3]	324	1			T158	8		T157	9		T184	10
auto[0]	values[4]	values[4]	365	1			T37	10		T80	4		T47	13
auto[0]	values[4]	values[5]	219	1			T158	13		T157	11		T30	13
auto[0]	values[4]	values[6]	257	1			T46	30		T158	22		T184	14
auto[0]	values[4]	values[7]	303	1			T10	31		T37	10		T219	20
auto[0]	values[5]	values[0]	189	1			T37	9		T220	10		T17	7
auto[0]	values[5]	values[1]	156	1			T178	9		T190	11		T133	14
auto[0]	values[5]	values[2]	314	1			T47	11		T49	7		T221	4
auto[0]	values[5]	values[3]	208	1			T48	26		T182	8		T189	18
auto[0]	values[5]	values[4]	213	1			T10	14		T37	9		T93	14
auto[0]	values[5]	values[5]	168	1			T222	2		T83	14		T190	12
auto[0]	values[5]	values[6]	348	1			T48	15		T49	13		T184	24
auto[0]	values[5]	values[7]	178	1			T157	15		T223	18		T184	31
auto[0]	values[6]	values[0]	233	1			T13	29		T37	11		T43	26
auto[0]	values[6]	values[1]	294	1			T224	14		T178	62		T225	11
auto[0]	values[6]	values[2]	207	1			T44	14		T212	10		T158	13
auto[0]	values[6]	values[3]	337	1			T17	17		T177	57		T226	12
auto[0]	values[6]	values[4]	196	1			T10	12		T44	13		T39	8
auto[0]	values[6]	values[5]	184	1			T183	24		T176	12		T178	12
auto[0]	values[6]	values[6]	186	1			T227	4		T228	20		T182	12
auto[0]	values[6]	values[7]	282	1			T37	13		T43	13		T49	11
auto[0]	values[7]	values[0]	164	1			T37	16		T192	28		T171	13
auto[0]	values[7]	values[1]	140	1			T49	19		T178	10		T216	15
auto[0]	values[7]	values[2]	329	1			T1	4		T5	2		T13	34
auto[0]	values[7]	values[3]	378	1			T157	27		T181	52		T229	109
auto[0]	values[7]	values[4]	193	1			T13	7		T46	7		T230	8
auto[0]	values[7]	values[5]	390	1			T12	8		T13	61		T44	6
auto[0]	values[7]	values[6]	172	1			T183	23		T205	6		T83	10
auto[0]	values[7]	values[7]	224	1			T46	49		T157	11		T184	17
auto[1]	values[0]	values[0]	296	1			T13	11		T44	11		T158	9
auto[1]	values[0]	values[1]	103	1			T37	10		T158	11		T189	11
auto[1]	values[0]	values[2]	314	1			T43	11		T44	63		T182	4
auto[1]	values[0]	values[3]	179	1			T46	7		T48	8		T157	7
auto[1]	values[0]	values[4]	206	1			T46	31		T157	5		T184	43
auto[1]	values[0]	values[5]	111	1			T37	10		T231	22		T232	13
auto[1]	values[0]	values[6]	172	1			T43	12		T46	11		T48	13
auto[1]	values[0]	values[7]	232	1			T13	61		T158	13		T182	17
auto[1]	values[1]	values[0]	121	1			T13	13		T37	17		T49	17
auto[1]	values[1]	values[1]	283	1			T13	16		T45	84		T82	7
auto[1]	values[1]	values[2]	192	1			T10	11		T48	63		T30	9
auto[1]	values[1]	values[3]	142	1			T82	9		T152	8		T126	8
auto[1]	values[1]	values[4]	95	1			T48	9		T49	9		T82	5
auto[1]	values[1]	values[5]	241	1			T171	62		T131	102		T133	8
auto[1]	values[1]	values[6]	133	1			T48	8		T82	9		T182	8
auto[1]	values[1]	values[7]	169	1			T184	18		T82	12		T178	17
auto[1]	values[2]	values[0]	118	1			T10	8		T45	11		T82	11
auto[1]	values[2]	values[1]	131	1			T10	4		T17	11		T158	6
auto[1]	values[2]	values[2]	402	1			T37	10		T47	14		T157	8
auto[1]	values[2]	values[3]	135	1			T43	6		T178	6		T189	12
auto[1]	values[2]	values[4]	83	1			T37	6		T196	8		T126	8
auto[1]	values[2]	values[5]	197	1			T158	5		T185	18		T189	7
auto[1]	values[2]	values[6]	295	1			T47	7		T30	46		T152	19
auto[1]	values[2]	values[7]	238	1			T184	58		T233	18		T176	3
auto[1]	values[3]	values[0]	136	1			T10	7		T11	20		T234	6
auto[1]	values[3]	values[1]	179	1			T43	8		T46	7		T49	6
auto[1]	values[3]	values[2]	192	1			T37	9		T176	7		T83	18
auto[1]	values[3]	values[3]	105	1			T83	9		T190	6		T131	9
auto[1]	values[3]	values[4]	108	1			T82	9		T30	20		T152	10
auto[1]	values[3]	values[5]	198	1			T44	7		T45	12		T46	34
auto[1]	values[3]	values[6]	186	1			T43	5		T183	12		T186	16
auto[1]	values[3]	values[7]	242	1			T13	9		T43	55		T46	10
auto[1]	values[4]	values[0]	210	1			T184	7		T182	7		T176	10
auto[1]	values[4]	values[1]	167	1			T10	8		T158	11		T185	5
auto[1]	values[4]	values[2]	124	1			T156	2		T157	8		T181	3
auto[1]	values[4]	values[3]	187	1			T158	12		T157	11		T184	10
auto[1]	values[4]	values[4]	169	1			T37	10		T47	7		T158	11
auto[1]	values[4]	values[5]	109	1			T158	7		T157	19		T30	7
auto[1]	values[4]	values[6]	230	1			T46	20		T158	18		T184	6
auto[1]	values[4]	values[7]	186	1			T10	20		T37	10		T171	10
auto[1]	values[5]	values[0]	189	1			T37	11		T17	13		T182	8
auto[1]	values[5]	values[1]	83	1			T178	11		T190	10		T133	13
auto[1]	values[5]	values[2]	180	1			T47	9		T49	13		T152	6
auto[1]	values[5]	values[3]	138	1			T48	21		T182	12		T189	2
auto[1]	values[5]	values[4]	235	1			T10	18		T37	11		T178	33
auto[1]	values[5]	values[5]	377	1			T8	14		T83	40		T190	12
auto[1]	values[5]	values[6]	197	1			T48	5		T49	7		T184	7
auto[1]	values[5]	values[7]	134	1			T157	25		T184	8		T83	55
auto[1]	values[6]	values[0]	287	1			T13	22		T37	9		T43	10
auto[1]	values[6]	values[1]	190	1			T178	57		T225	9		T235	11
auto[1]	values[6]	values[2]	250	1			T44	6		T158	7		T82	11
auto[1]	values[6]	values[3]	190	1			T17	7		T236	18		T177	16
auto[1]	values[6]	values[4]	247	1			T10	8		T44	7		T49	9
auto[1]	values[6]	values[5]	198	1			T183	23		T176	8		T178	78
auto[1]	values[6]	values[6]	246	1			T182	8		T176	9		T181	125
auto[1]	values[6]	values[7]	141	1			T37	7		T43	7		T49	9
auto[1]	values[7]	values[0]	167	1			T37	4		T171	62		T83	11
auto[1]	values[7]	values[1]	149	1			T49	21		T178	21		T216	29
auto[1]	values[7]	values[2]	139	1			T13	28		T37	4		T49	7
auto[1]	values[7]	values[3]	294	1			T157	8		T181	8		T152	7
auto[1]	values[7]	values[4]	218	1			T13	13		T26	16		T46	77
auto[1]	values[7]	values[5]	221	1			T13	7		T44	17		T176	4
auto[1]	values[7]	values[6]	122	1			T183	20		T83	19		T133	6
auto[1]	values[7]	values[7]	161	1			T46	22		T157	39		T184	39