Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	413	1			T13	9		T37	7		T43	2
auto[ReadAddrCrossIntoMailbox]	289	1			T13	2		T25	2		T37	3
auto[ReadAddrCrossOutOfMailbox]	293	1			T10	3		T13	6		T37	2
auto[ReadAddrCrossAllMailbox]	202	1			T10	2		T13	3		T37	1
auto[ReadAddrOutsideMailbox]	3367	1			T10	28		T11	4		T12	8

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2255

1

T10

17

T11

2

T12

4

auto[1]

2309

1

T10

16

T11

2

T12

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	713	1			T10	4		T13	8		T37	10
read_ops[0x0b]	765	1			T10	5		T13	14		T25	4
read_ops[0x3b]	778	1			T10	12		T12	2		T13	11
read_ops[0x6b]	768	1			T10	5		T13	5		T37	8
read_ops[0xbb]	752	1			T10	4		T12	6		T13	11
read_ops[0xeb]	788	1			T10	3		T11	4		T13	11

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T13	2		T157	2		T193	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T37	2		T44	1		T46	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T46	2		T49	1		T184	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T37	1		T46	1		T183	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T45	1		T184	1		T176	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T43	1		T44	1		T185	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T183	1		T182	2		T171	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	10	1			T196	1		T225	1		T61	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	260	1			T10	2		T13	3		T37	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	274	1			T10	2		T13	3		T37	5
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T46	1		T199	1		T178	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T13	2		T37	1		T46	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T25	1		T46	1		T157	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T13	1		T25	1		T37	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T158	1		T157	1		T184	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T13	2		T37	1		T44	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T13	1		T37	1		T46	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T44	1		T171	1		T83	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	293	1			T10	2		T13	4		T25	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	278	1			T10	3		T13	4		T25	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T13	1		T47	2		T48	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T13	1		T48	1		T49	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T37	1		T43	1		T46	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T43	1		T44	1		T46	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T10	1		T47	2		T183	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T13	2		T49	1		T181	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T189	1		T131	1		T177	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T44	1		T49	2		T185	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	293	1			T10	7		T12	1		T13	6
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	288	1			T10	4		T12	1		T13	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T44	1		T158	1		T182	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T37	2		T43	1		T49	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T43	1		T46	3		T176	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T49	1		T176	1		T30	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T10	1		T13	1		T37	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T43	1		T47	1		T49	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T218	1		T182	1		T181	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T46	1		T218	1		T133	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	280	1			T10	1		T13	1		T43	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	288	1			T10	3		T13	3		T37	5
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T13	1		T37	1		T43	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T13	1		T230	1		T17	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T46	1		T182	1		T30	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T45	1		T46	1		T82	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T48	1		T183	1		T157	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T10	1		T47	1		T17	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T43	1		T185	1		T171	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T10	2		T45	1		T47	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	268	1			T12	3		T13	2		T26	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	281	1			T10	1		T12	3		T13	7
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T13	1		T37	1		T44	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T46	1		T48	1		T49	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T13	1		T183	2		T158	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	34	1			T183	1		T178	1		T83	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	15	1			T184	1		T182	1		T178	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T13	1		T43	1		T48	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T13	2		T48	1		T171	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T43	1		T46	1		T47	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	285	1			T10	3		T11	2		T13	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	279	1			T11	2		T13	3		T26	2