Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3782	1			T13	35		T37	20		T156	2
values[1]	3353	1			T10	56		T13	79		T37	60
values[2]	3816	1			T13	31		T37	40		T43	42
values[3]	3510	1			T13	71		T25	4		T37	40
values[4]	3638	1			T5	2		T10	20		T26	16
values[5]	3682	1			T1	4		T10	103		T13	78
values[6]	3024	1			T8	14		T10	65		T11	20
values[7]	3529	1			T13	110		T37	40		T43	43

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3773	1			T13	104		T37	40		T44	103
values[1]	3467	1			T5	2		T10	65		T13	67
values[2]	3687	1			T10	72		T12	8		T13	88
values[3]	3394	1			T43	36		T45	94		T46	146
values[4]	3265	1			T10	36		T11	20		T13	20
values[5]	3529	1			T10	20		T13	53		T37	40
values[6]	3772	1			T10	51		T13	20		T37	20
values[7]	3447	1			T1	4		T8	14		T13	52

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27561

1

T1

4

T5

2

T8

14

auto[1]

773

1

T10

1

T13

12

T37

6

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	571	1			T178	19		T201	22		T83	20
auto[0]	values[0]	values[1]	448	1			T13	33		T157	20		T178	71
auto[0]	values[0]	values[2]	353	1			T237	8		T238	10		T131	24
auto[0]	values[0]	values[3]	521	1			T183	27		T82	16		T178	88
auto[0]	values[0]	values[4]	502	1			T182	43		T83	27		T177	84
auto[0]	values[0]	values[5]	420	1			T37	20		T47	35		T184	52
auto[0]	values[0]	values[6]	500	1			T185	20		T189	20		T239	8
auto[0]	values[0]	values[7]	376	1			T157	35		T184	20		T82	20
auto[0]	values[1]	values[0]	500	1			T37	20		T44	76		T212	10
auto[0]	values[1]	values[1]	326	1			T13	31		T155	16		T82	20
auto[0]	values[1]	values[2]	310	1			T10	20		T37	20		T199	8
auto[0]	values[1]	values[3]	342	1			T219	20		T227	4		T182	30
auto[0]	values[1]	values[4]	423	1			T10	35		T82	20		T178	124
auto[0]	values[1]	values[5]	436	1			T13	27		T184	31		T176	20
auto[0]	values[1]	values[6]	492	1			T37	20		T48	77		T184	20
auto[0]	values[1]	values[7]	441	1			T13	20		T17	69		T176	20
auto[0]	values[2]	values[0]	278	1			T13	30		T39	8		T157	20
auto[0]	values[2]	values[1]	338	1			T43	22		T49	20		T158	19
auto[0]	values[2]	values[2]	672	1			T46	33		T48	20		T49	17
auto[0]	values[2]	values[3]	651	1			T45	90		T49	19		T17	32
auto[0]	values[2]	values[4]	252	1			T37	20		T233	18		T240	20
auto[0]	values[2]	values[5]	510	1			T37	20		T43	16		T44	23
auto[0]	values[2]	values[6]	664	1			T44	19		T208	12		T181	20
auto[0]	values[2]	values[7]	332	1			T181	20		T83	77		T173	25
auto[0]	values[3]	values[0]	669	1			T13	31		T37	20		T170	12
auto[0]	values[3]	values[1]	417	1			T48	19		T49	16		T30	86
auto[0]	values[3]	values[2]	474	1			T13	20		T25	4		T80	4
auto[0]	values[3]	values[3]	369	1			T46	20		T241	6		T184	25
auto[0]	values[3]	values[4]	512	1			T13	20		T37	16		T157	33
auto[0]	values[3]	values[5]	371	1			T93	14		T185	30		T228	20
auto[0]	values[3]	values[6]	237	1			T174	22		T82	20		T182	22
auto[0]	values[3]	values[7]	388	1			T157	20		T82	20		T83	39
auto[0]	values[4]	values[0]	344	1			T46	20		T49	20		T183	52
auto[0]	values[4]	values[1]	394	1			T5	2		T10	20		T26	16
auto[0]	values[4]	values[2]	325	1			T183	23		T17	20		T221	4
auto[0]	values[4]	values[3]	448	1			T46	126		T48	19		T184	20
auto[0]	values[4]	values[4]	361	1			T183	23		T182	47		T176	20
auto[0]	values[4]	values[5]	480	1			T49	20		T184	56		T178	55
auto[0]	values[4]	values[6]	423	1			T184	72		T176	18		T30	26
auto[0]	values[4]	values[7]	756	1			T214	2		T46	20		T48	167
auto[0]	values[5]	values[0]	466	1			T44	26		T46	41		T230	8
auto[0]	values[5]	values[1]	445	1			T218	2		T158	20		T157	49
auto[0]	values[5]	values[2]	468	1			T10	52		T37	59		T234	6
auto[0]	values[5]	values[3]	358	1			T43	36		T157	30		T83	35
auto[0]	values[5]	values[4]	556	1			T48	125		T158	19		T171	74
auto[0]	values[5]	values[5]	461	1			T10	20		T13	23		T45	29
auto[0]	values[5]	values[6]	440	1			T10	31		T13	20		T43	23
auto[0]	values[5]	values[7]	364	1			T1	4		T13	32		T46	28
auto[0]	values[6]	values[0]	412	1			T184	22		T171	39		T242	16
auto[0]	values[6]	values[1]	490	1			T10	45		T157	20		T185	20
auto[0]	values[6]	values[2]	307	1			T12	8		T43	64		T49	14
auto[0]	values[6]	values[3]	350	1			T183	18		T176	20		T189	20
auto[0]	values[6]	values[4]	319	1			T11	20		T43	20		T45	20
auto[0]	values[6]	values[5]	296	1			T44	20		T49	20		T202	24
auto[0]	values[6]	values[6]	379	1			T10	20		T43	20		T46	45
auto[0]	values[6]	values[7]	389	1			T8	14		T43	22		T78	12
auto[0]	values[7]	values[0]	452	1			T13	41		T48	20		T182	31
auto[0]	values[7]	values[1]	521	1			T49	17		T184	39		T243	12
auto[0]	values[7]	values[2]	650	1			T13	64		T37	39		T43	43
auto[0]	values[7]	values[3]	264	1			T83	20		T225	20		T177	20
auto[0]	values[7]	values[4]	241	1			T220	10		T82	20		T131	35
auto[0]	values[7]	values[5]	447	1			T47	32		T49	18		T157	39
auto[0]	values[7]	values[6]	559	1			T183	20		T158	19		T244	16
auto[0]	values[7]	values[7]	301	1			T182	22		T152	19		T245	16
auto[1]	values[0]	values[0]	8	1			T178	1		T189	3		T246	1
auto[1]	values[0]	values[1]	12	1			T13	2		T156	2		T154	5
auto[1]	values[0]	values[2]	10	1			T131	2		T200	1		T232	1
auto[1]	values[0]	values[3]	8	1			T82	4		T178	2		T189	1
auto[1]	values[0]	values[4]	18	1			T83	2		T177	1		T231	2
auto[1]	values[0]	values[5]	15	1			T47	5		T247	2		T248	4
auto[1]	values[0]	values[6]	5	1			T216	1		T154	1		T180	1
auto[1]	values[0]	values[7]	15	1			T178	2		T30	1		T206	1
auto[1]	values[1]	values[0]	7	1			T47	3		T83	2		T249	2
auto[1]	values[1]	values[1]	4	1			T13	1		T196	2		T56	1
auto[1]	values[1]	values[2]	10	1			T200	1		T194	2		T250	1
auto[1]	values[1]	values[3]	9	1			T182	1		T176	1		T190	1
auto[1]	values[1]	values[4]	11	1			T10	1		T251	1		T252	1
auto[1]	values[1]	values[5]	14	1			T133	3		T225	2		T253	2
auto[1]	values[1]	values[6]	17	1			T48	1		T176	1		T209	1
auto[1]	values[1]	values[7]	11	1			T17	3		T173	2		T131	4
auto[1]	values[2]	values[0]	5	1			T13	1		T152	1		T240	1
auto[1]	values[2]	values[1]	13	1			T158	1		T178	1		T252	6
auto[1]	values[2]	values[2]	25	1			T46	3		T49	3		T171	1
auto[1]	values[2]	values[3]	27	1			T45	4		T49	1		T184	2
auto[1]	values[2]	values[4]	13	1			T240	2		T200	1		T194	2
auto[1]	values[2]	values[5]	15	1			T43	4		T157	4		T196	4
auto[1]	values[2]	values[6]	14	1			T44	1		T126	4		T177	1
auto[1]	values[2]	values[7]	7	1			T240	2		T154	1		T55	2
auto[1]	values[3]	values[0]	9	1			T181	1		T83	2		T177	4
auto[1]	values[3]	values[1]	14	1			T48	1		T49	4		T30	1
auto[1]	values[3]	values[2]	13	1			T152	1		T133	1		T246	1
auto[1]	values[3]	values[3]	9	1			T184	1		T82	2		T206	3
auto[1]	values[3]	values[4]	9	1			T37	4		T157	1		T206	1
auto[1]	values[3]	values[5]	7	1			T171	3		T254	1		T255	3
auto[1]	values[3]	values[6]	1	1			T252	1		-	-		-	-
auto[1]	values[3]	values[7]	11	1			T131	1		T209	1		T256	1
auto[1]	values[4]	values[0]	9	1			T183	1		T176	1		T54	1
auto[1]	values[4]	values[1]	8	1			T30	2		T216	3		T54	1
auto[1]	values[4]	values[2]	23	1			T183	1		T82	3		T210	10
auto[1]	values[4]	values[3]	7	1			T48	1		T178	1		T54	1
auto[1]	values[4]	values[4]	13	1			T190	5		T173	2		T135	1
auto[1]	values[4]	values[5]	19	1			T178	1		T83	2		T206	6
auto[1]	values[4]	values[6]	12	1			T184	2		T176	2		T30	1
auto[1]	values[4]	values[7]	16	1			T176	1		T257	5		T258	1
auto[1]	values[5]	values[0]	18	1			T44	1		T236	8		T177	1
auto[1]	values[5]	values[1]	17	1			T157	1		T190	4		T240	3
auto[1]	values[5]	values[2]	18	1			T37	1		T82	2		T83	3
auto[1]	values[5]	values[3]	11	1			T83	2		T189	4		T246	1
auto[1]	values[5]	values[4]	23	1			T48	5		T158	1		T171	1
auto[1]	values[5]	values[5]	17	1			T13	3		T196	1		T259	6
auto[1]	values[5]	values[6]	10	1			T43	1		T44	3		T189	1
auto[1]	values[5]	values[7]	10	1			T46	2		T158	2		T82	1
auto[1]	values[6]	values[0]	10	1			T83	1		T216	2		T235	1
auto[1]	values[6]	values[1]	8	1			T30	2		T133	1		T206	3
auto[1]	values[6]	values[2]	11	1			T43	3		T49	6		T260	1
auto[1]	values[6]	values[3]	13	1			T183	2		T209	1		T256	1
auto[1]	values[6]	values[4]	9	1			T250	1		T258	2		T261	1
auto[1]	values[6]	values[5]	7	1			T262	4		T263	1		T264	2
auto[1]	values[6]	values[6]	6	1			T46	1		T235	3		T256	1
auto[1]	values[6]	values[7]	18	1			T43	2		T158	1		T82	3
auto[1]	values[7]	values[0]	15	1			T13	1		T182	5		T176	2
auto[1]	values[7]	values[1]	12	1			T49	3		T152	1		T126	3
auto[1]	values[7]	values[2]	18	1			T13	4		T37	1		T158	1
auto[1]	values[7]	values[3]	7	1			T265	2		T266	2		T267	3
auto[1]	values[7]	values[4]	3	1			T131	1		T209	1		T268	1
auto[1]	values[7]	values[5]	14	1			T47	4		T49	2		T157	1
auto[1]	values[7]	values[6]	13	1			T158	1		T244	4		T152	1
auto[1]	values[7]	values[7]	12	1			T182	2		T152	1		T245	4