Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	727	1			T10	11		T15	17		T16	17
all_values[1]	727	1			T10	11		T15	17		T16	17
all_values[2]	727	1			T10	11		T15	17		T16	17
all_values[3]	727	1			T10	11		T15	17		T16	17
all_values[4]	727	1			T10	11		T15	17		T16	17
all_values[5]	727	1			T10	11		T15	17		T16	17
all_values[6]	727	1			T10	11		T15	17		T16	17
all_values[7]	727	1			T10	11		T15	17		T16	17

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3112

1

T10

50

T15

83

T16

78

auto[1]

2704

1

T10

38

T15

53

T16

58

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2369

1

T10

27

T15

48

T16

53

auto[1]

3447

1

T10

61

T15

88

T16

83

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3354

1

T10

44

T15

75

T16

74

auto[1]

2462

1

T10

44

T15

61

T16

62

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	154	1			T15	3		T16	8		T17	1
all_values[0]	auto[0]	auto[0]	auto[1]	65	1			T10	1		T15	5		T16	1
all_values[0]	auto[0]	auto[1]	auto[0]	116	1			T10	1		T15	1		T16	1
all_values[0]	auto[0]	auto[1]	auto[1]	72	1			T10	1		T17	1		T18	2
all_values[0]	auto[1]	auto[0]	auto[1]	172	1			T10	5		T15	6		T16	6
all_values[0]	auto[1]	auto[1]	auto[1]	148	1			T10	3		T15	2		T16	1
all_values[1]	auto[0]	auto[0]	auto[0]	172	1			T10	4		T15	3		T16	9
all_values[1]	auto[0]	auto[0]	auto[1]	58	1			T10	1		T15	1		T16	1
all_values[1]	auto[0]	auto[1]	auto[0]	134	1			T10	2		T15	4		T16	2
all_values[1]	auto[0]	auto[1]	auto[1]	67	1			T15	3		T18	2		T30	2
all_values[1]	auto[1]	auto[0]	auto[1]	154	1			T10	3		T15	3		T16	2
all_values[1]	auto[1]	auto[1]	auto[1]	142	1			T10	1		T15	3		T16	3
all_values[2]	auto[0]	auto[0]	auto[0]	161	1			T10	1		T15	2		T16	4
all_values[2]	auto[0]	auto[0]	auto[1]	77	1			T15	4		T16	1		T17	3
all_values[2]	auto[0]	auto[1]	auto[0]	111	1			T10	4		T16	3		T17	2
all_values[2]	auto[0]	auto[1]	auto[1]	63	1			T10	1		T15	3		T16	1
all_values[2]	auto[1]	auto[0]	auto[1]	168	1			T10	4		T15	5		T16	6
all_values[2]	auto[1]	auto[1]	auto[1]	147	1			T10	1		T15	3		T16	2
all_values[3]	auto[0]	auto[0]	auto[0]	141	1			T10	1		T15	4		T16	1
all_values[3]	auto[0]	auto[0]	auto[1]	59	1			T10	1		T15	2		T16	1
all_values[3]	auto[0]	auto[1]	auto[0]	136	1			T10	1		T15	1		T16	5
all_values[3]	auto[0]	auto[1]	auto[1]	81	1			T10	3		T15	1		T16	1
all_values[3]	auto[1]	auto[0]	auto[1]	172	1			T10	3		T15	5		T16	2
all_values[3]	auto[1]	auto[1]	auto[1]	138	1			T10	2		T15	4		T16	7
all_values[4]	auto[0]	auto[0]	auto[0]	164	1			T10	1		T15	5		T16	4
all_values[4]	auto[0]	auto[0]	auto[1]	82	1			T10	2		T15	2		T16	3
all_values[4]	auto[0]	auto[1]	auto[0]	107	1			T10	1		T15	2		T16	1
all_values[4]	auto[0]	auto[1]	auto[1]	66	1			T15	1		T16	3		T17	1
all_values[4]	auto[1]	auto[0]	auto[1]	165	1			T10	3		T15	3		T16	2
all_values[4]	auto[1]	auto[1]	auto[1]	143	1			T10	4		T15	4		T16	4
all_values[5]	auto[0]	auto[0]	auto[0]	242	1			T10	4		T15	6		T16	4
all_values[5]	auto[0]	auto[1]	auto[0]	188	1			T10	3		T15	4		T16	3
all_values[5]	auto[1]	auto[0]	auto[1]	168	1			T10	4		T15	4		T16	4
all_values[5]	auto[1]	auto[1]	auto[1]	129	1			T15	3		T16	6		T17	2
all_values[6]	auto[0]	auto[0]	auto[0]	132	1			T10	2		T15	3		T16	1
all_values[6]	auto[0]	auto[0]	auto[1]	77	1			T10	1		T15	2		T16	2
all_values[6]	auto[0]	auto[1]	auto[0]	128	1			T15	4		T16	2		T18	4
all_values[6]	auto[0]	auto[1]	auto[1]	78	1			T10	3		T16	5		T17	2
all_values[6]	auto[1]	auto[0]	auto[1]	166	1			T10	4		T15	6		T16	3
all_values[6]	auto[1]	auto[1]	auto[1]	146	1			T10	1		T15	2		T16	4
all_values[7]	auto[0]	auto[0]	auto[0]	135	1			T15	3		T16	3		T17	1
all_values[7]	auto[0]	auto[0]	auto[1]	64	1			T10	1		T15	3		T16	2
all_values[7]	auto[0]	auto[1]	auto[0]	148	1			T10	2		T15	3		T16	2
all_values[7]	auto[0]	auto[1]	auto[1]	76	1			T10	2		T17	1		T19	2
all_values[7]	auto[1]	auto[0]	auto[1]	164	1			T10	4		T15	3		T16	8
all_values[7]	auto[1]	auto[1]	auto[1]	140	1			T10	2		T15	5		T16	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal