Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1851

1

T3

11

T6

3

T9

1

auto[1]

1926

1

T3

16

T6

7

T9

1

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2004

1

T3

27

T9

2

T10

11

auto[1]

1773

1

T6

10

T10

7

T23

12

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2994

1

T3

16

T6

10

T9

2

auto[1]

783

1

T3

11

T10

5

T24

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	765	1			T3	7		T6	1		T10	4
valid[1]	762	1			T3	5		T6	2		T10	4
valid[2]	756	1			T3	3		T6	3		T10	2
valid[3]	702	1			T3	3		T6	2		T9	1
valid[4]	792	1			T3	9		T6	2		T9	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	119	1			T3	1		T10	1		T43	1
auto[0]	auto[0]	valid[0]	auto[1]	190	1			T6	1		T23	2		T28	2
auto[0]	auto[0]	valid[1]	auto[0]	120	1			T3	2		T10	2		T89	2
auto[0]	auto[0]	valid[1]	auto[1]	179	1			T10	1		T23	1		T50	1
auto[0]	auto[0]	valid[2]	auto[0]	108	1			T44	1		T89	1		T183	1
auto[0]	auto[0]	valid[2]	auto[1]	165	1			T6	1		T10	1		T28	1
auto[0]	auto[0]	valid[3]	auto[0]	116	1			T3	2		T9	1		T10	2
auto[0]	auto[0]	valid[3]	auto[1]	153	1			T10	1		T24	1		T91	2
auto[0]	auto[0]	valid[4]	auto[0]	123	1			T3	1		T24	1		T42	1
auto[0]	auto[0]	valid[4]	auto[1]	188	1			T6	1		T28	1		T42	1
auto[0]	auto[1]	valid[0]	auto[0]	103	1			T3	2		T44	1		T89	1
auto[0]	auto[1]	valid[0]	auto[1]	179	1			T10	2		T23	4		T50	1
auto[0]	auto[1]	valid[1]	auto[0]	118	1			T3	2		T24	1		T50	1
auto[0]	auto[1]	valid[1]	auto[1]	200	1			T6	2		T23	1		T28	2
auto[0]	auto[1]	valid[2]	auto[0]	152	1			T89	2		T47	2		T183	1
auto[0]	auto[1]	valid[2]	auto[1]	172	1			T6	2		T23	3		T24	1
auto[0]	auto[1]	valid[3]	auto[0]	130	1			T3	1		T22	1		T89	2
auto[0]	auto[1]	valid[3]	auto[1]	158	1			T6	2		T10	1		T28	3
auto[0]	auto[1]	valid[4]	auto[0]	132	1			T3	5		T9	1		T10	1
auto[0]	auto[1]	valid[4]	auto[1]	189	1			T6	1		T10	1		T23	1
auto[1]	auto[0]	valid[0]	auto[0]	86	1			T3	1		T18	2		T31	1
auto[1]	auto[0]	valid[1]	auto[0]	73	1			T3	1		T10	1		T43	1
auto[1]	auto[0]	valid[2]	auto[0]	80	1			T3	2		T44	1		T89	2
auto[1]	auto[0]	valid[3]	auto[0]	65	1			T182	1		T31	1		T283	1
auto[1]	auto[0]	valid[4]	auto[0]	86	1			T3	1		T10	1		T90	1
auto[1]	auto[1]	valid[0]	auto[0]	88	1			T3	3		T10	1		T89	1
auto[1]	auto[1]	valid[1]	auto[0]	72	1			T47	1		T283	2		T83	1
auto[1]	auto[1]	valid[2]	auto[0]	79	1			T3	1		T10	1		T42	1
auto[1]	auto[1]	valid[3]	auto[0]	80	1			T10	1		T160	1		T18	1
auto[1]	auto[1]	valid[4]	auto[0]	74	1			T3	2		T24	2		T42	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal