Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49474

1

T3

440

T7

12

T9

35

auto[1]

18075

1

T6

10

T10

84

T22

7

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49479

1

T3

286

T6

10

T7

7

auto[1]

18070

1

T3

154

T7

5

T9

11

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34720	1			T3	224		T6	10		T7	5
others[1]	5657	1			T3	42		T7	1		T9	2
others[2]	5618	1			T3	33		T7	3		T9	6
others[3]	6591	1			T3	37		T9	4		T10	43
interest[1]	3775	1			T3	28		T9	3		T10	16
interest[4]	22878	1			T3	157		T6	10		T7	1
interest[64]	11188	1			T3	76		T7	3		T9	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16073	1			T3	146		T7	3		T9	10
auto[0]	auto[0]	others[1]	2678	1			T3	33		T7	1		T9	1
auto[0]	auto[0]	others[2]	2605	1			T3	20		T7	1		T9	6
auto[0]	auto[0]	others[3]	3084	1			T3	24		T9	2		T10	22
auto[0]	auto[0]	interest[1]	1750	1			T3	18		T9	2		T10	7
auto[0]	auto[0]	interest[4]	10546	1			T3	96		T7	1		T9	6
auto[0]	auto[0]	interest[64]	5214	1			T3	45		T7	2		T9	3
auto[0]	auto[1]	others[0]	9341	1			T6	10		T10	38		T22	3
auto[0]	auto[1]	others[1]	1469	1			T10	8		T22	2		T23	13
auto[0]	auto[1]	others[2]	1483	1			T10	6		T22	1		T23	14
auto[0]	auto[1]	others[3]	1747	1			T10	8		T23	14		T24	2
auto[0]	auto[1]	interest[1]	989	1			T10	7		T23	11		T29	3
auto[0]	auto[1]	interest[4]	6235	1			T6	10		T10	26		T22	2
auto[0]	auto[1]	interest[64]	3046	1			T10	17		T22	1		T23	28
auto[1]	auto[0]	others[0]	9306	1			T3	78		T7	2		T9	6
auto[1]	auto[0]	others[1]	1510	1			T3	9		T9	1		T10	7
auto[1]	auto[0]	others[2]	1530	1			T3	13		T7	2		T10	8
auto[1]	auto[0]	others[3]	1760	1			T3	13		T9	2		T10	13
auto[1]	auto[0]	interest[1]	1036	1			T3	10		T9	1		T10	2
auto[1]	auto[0]	interest[4]	6097	1			T3	61		T9	2		T10	44
auto[1]	auto[0]	interest[64]	2928	1			T3	31		T7	1		T9	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal