Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.29 95.43 99.26


Total test records in report: 1149
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T1031 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.430721379 Jun 27 04:40:30 PM PDT 24 Jun 27 04:40:46 PM PDT 24 657589685 ps
T108 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3878884484 Jun 27 04:41:19 PM PDT 24 Jun 27 04:41:23 PM PDT 24 215468124 ps
T102 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1527003719 Jun 27 04:41:02 PM PDT 24 Jun 27 04:41:05 PM PDT 24 72755841 ps
T1032 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2765760867 Jun 27 04:41:03 PM PDT 24 Jun 27 04:41:05 PM PDT 24 33232819 ps
T140 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3170776565 Jun 27 04:40:40 PM PDT 24 Jun 27 04:40:43 PM PDT 24 118396999 ps
T1033 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.623274923 Jun 27 04:41:04 PM PDT 24 Jun 27 04:41:05 PM PDT 24 30928469 ps
T1034 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1457358220 Jun 27 04:40:53 PM PDT 24 Jun 27 04:40:55 PM PDT 24 54009550 ps
T118 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.521945462 Jun 27 04:40:55 PM PDT 24 Jun 27 04:41:00 PM PDT 24 74982258 ps
T1035 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3257130361 Jun 27 04:40:31 PM PDT 24 Jun 27 04:40:36 PM PDT 24 28892435 ps
T119 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.128205471 Jun 27 04:40:45 PM PDT 24 Jun 27 04:40:48 PM PDT 24 57831905 ps
T1036 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2945666729 Jun 27 04:41:18 PM PDT 24 Jun 27 04:41:20 PM PDT 24 21032127 ps
T1037 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2252174477 Jun 27 04:40:54 PM PDT 24 Jun 27 04:40:58 PM PDT 24 16040217 ps
T1038 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1631941813 Jun 27 04:41:22 PM PDT 24 Jun 27 04:41:28 PM PDT 24 11319268 ps
T85 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2626466263 Jun 27 04:40:31 PM PDT 24 Jun 27 04:40:35 PM PDT 24 82422212 ps
T1039 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3535385502 Jun 27 04:41:21 PM PDT 24 Jun 27 04:41:26 PM PDT 24 14576465 ps
T150 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.501883831 Jun 27 04:40:55 PM PDT 24 Jun 27 04:41:23 PM PDT 24 4018937715 ps
T107 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4264041697 Jun 27 04:40:54 PM PDT 24 Jun 27 04:40:59 PM PDT 24 496246836 ps
T165 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2415128044 Jun 27 04:40:52 PM PDT 24 Jun 27 04:41:09 PM PDT 24 567090285 ps
T167 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2415291642 Jun 27 04:40:55 PM PDT 24 Jun 27 04:41:22 PM PDT 24 2144497714 ps
T103 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2711493688 Jun 27 04:41:19 PM PDT 24 Jun 27 04:41:25 PM PDT 24 318078428 ps
T109 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3100756540 Jun 27 04:40:57 PM PDT 24 Jun 27 04:41:03 PM PDT 24 135890084 ps
T120 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3597765724 Jun 27 04:41:25 PM PDT 24 Jun 27 04:41:32 PM PDT 24 88427837 ps
T86 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1190957629 Jun 27 04:40:32 PM PDT 24 Jun 27 04:40:36 PM PDT 24 22551126 ps
T1040 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2111899195 Jun 27 04:41:21 PM PDT 24 Jun 27 04:41:26 PM PDT 24 297992728 ps
T1041 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2742259600 Jun 27 04:41:24 PM PDT 24 Jun 27 04:41:29 PM PDT 24 23119578 ps
T1042 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.549520307 Jun 27 04:40:45 PM PDT 24 Jun 27 04:40:47 PM PDT 24 34831103 ps
T104 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.850720483 Jun 27 04:40:43 PM PDT 24 Jun 27 04:40:49 PM PDT 24 802944601 ps
T121 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1258882251 Jun 27 04:40:59 PM PDT 24 Jun 27 04:41:03 PM PDT 24 352803301 ps
T1043 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3845482550 Jun 27 04:40:40 PM PDT 24 Jun 27 04:40:42 PM PDT 24 41374657 ps
T105 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.622681648 Jun 27 04:41:03 PM PDT 24 Jun 27 04:41:09 PM PDT 24 281431490 ps
T122 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2840521164 Jun 27 04:40:28 PM PDT 24 Jun 27 04:40:45 PM PDT 24 715344351 ps
T1044 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2319011718 Jun 27 04:40:55 PM PDT 24 Jun 27 04:41:02 PM PDT 24 236828464 ps
T106 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3914875192 Jun 27 04:40:30 PM PDT 24 Jun 27 04:40:37 PM PDT 24 413435952 ps
T1045 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.989622597 Jun 27 04:40:54 PM PDT 24 Jun 27 04:40:59 PM PDT 24 302340780 ps
T1046 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3354932443 Jun 27 04:40:32 PM PDT 24 Jun 27 04:40:38 PM PDT 24 53707175 ps
T1047 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4229039131 Jun 27 04:41:00 PM PDT 24 Jun 27 04:41:04 PM PDT 24 834425328 ps
T1048 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3771742557 Jun 27 04:41:20 PM PDT 24 Jun 27 04:41:22 PM PDT 24 25418023 ps
T123 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.872800395 Jun 27 04:40:32 PM PDT 24 Jun 27 04:40:36 PM PDT 24 129942070 ps
T1049 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2762829043 Jun 27 04:41:23 PM PDT 24 Jun 27 04:41:28 PM PDT 24 24440440 ps
T1050 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2203603399 Jun 27 04:40:29 PM PDT 24 Jun 27 04:40:37 PM PDT 24 1432323505 ps
T1051 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1599501573 Jun 27 04:40:55 PM PDT 24 Jun 27 04:40:59 PM PDT 24 63925033 ps
T1052 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3045251658 Jun 27 04:40:56 PM PDT 24 Jun 27 04:41:00 PM PDT 24 28928684 ps
T163 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.418786559 Jun 27 04:41:21 PM PDT 24 Jun 27 04:41:45 PM PDT 24 3349137449 ps
T1053 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3991299359 Jun 27 04:41:00 PM PDT 24 Jun 27 04:41:08 PM PDT 24 115442482 ps
T1054 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1185939281 Jun 27 04:41:20 PM PDT 24 Jun 27 04:41:22 PM PDT 24 52081232 ps
T110 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2962289415 Jun 27 04:40:28 PM PDT 24 Jun 27 04:40:33 PM PDT 24 47867349 ps
T1055 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2392442217 Jun 27 04:40:55 PM PDT 24 Jun 27 04:40:59 PM PDT 24 68463467 ps
T1056 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2208384788 Jun 27 04:41:19 PM PDT 24 Jun 27 04:41:21 PM PDT 24 11677142 ps
T1057 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1024356669 Jun 27 04:40:30 PM PDT 24 Jun 27 04:40:33 PM PDT 24 50651045 ps
T124 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.80784254 Jun 27 04:40:57 PM PDT 24 Jun 27 04:41:02 PM PDT 24 36338815 ps
T1058 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1550066169 Jun 27 04:41:20 PM PDT 24 Jun 27 04:41:22 PM PDT 24 59066642 ps
T1059 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2721555945 Jun 27 04:40:51 PM PDT 24 Jun 27 04:40:55 PM PDT 24 798004559 ps
T1060 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2443034297 Jun 27 04:41:22 PM PDT 24 Jun 27 04:41:30 PM PDT 24 409376893 ps
T1061 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2900656918 Jun 27 04:41:20 PM PDT 24 Jun 27 04:41:22 PM PDT 24 18173878 ps
T125 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3343049894 Jun 27 04:40:56 PM PDT 24 Jun 27 04:41:01 PM PDT 24 134523138 ps
T1062 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1983032230 Jun 27 04:40:55 PM PDT 24 Jun 27 04:40:59 PM PDT 24 49381538 ps
T1063 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2808908857 Jun 27 04:40:53 PM PDT 24 Jun 27 04:40:59 PM PDT 24 110428555 ps
T1064 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2892251947 Jun 27 04:40:41 PM PDT 24 Jun 27 04:40:44 PM PDT 24 111893273 ps
T1065 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1111071128 Jun 27 04:40:53 PM PDT 24 Jun 27 04:41:04 PM PDT 24 360712826 ps
T1066 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2599976680 Jun 27 04:40:32 PM PDT 24 Jun 27 04:40:38 PM PDT 24 90944524 ps
T1067 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1427325913 Jun 27 04:40:45 PM PDT 24 Jun 27 04:41:18 PM PDT 24 524468338 ps
T1068 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.165963559 Jun 27 04:40:55 PM PDT 24 Jun 27 04:41:01 PM PDT 24 120903166 ps
T164 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3856167260 Jun 27 04:40:54 PM PDT 24 Jun 27 04:41:22 PM PDT 24 1103768525 ps
T1069 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3552577340 Jun 27 04:41:23 PM PDT 24 Jun 27 04:41:28 PM PDT 24 13061807 ps
T1070 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2038886432 Jun 27 04:40:32 PM PDT 24 Jun 27 04:40:39 PM PDT 24 59609729 ps
T1071 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.693182325 Jun 27 04:40:56 PM PDT 24 Jun 27 04:41:02 PM PDT 24 185626084 ps
T1072 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.890152078 Jun 27 04:41:00 PM PDT 24 Jun 27 04:41:02 PM PDT 24 14157659 ps
T1073 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.60315670 Jun 27 04:40:41 PM PDT 24 Jun 27 04:40:43 PM PDT 24 19508931 ps
T1074 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1441005900 Jun 27 04:40:54 PM PDT 24 Jun 27 04:41:01 PM PDT 24 736316060 ps
T1075 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1636646348 Jun 27 04:40:31 PM PDT 24 Jun 27 04:40:35 PM PDT 24 62828987 ps
T1076 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2023090636 Jun 27 04:41:00 PM PDT 24 Jun 27 04:41:05 PM PDT 24 160579450 ps
T1077 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1161971182 Jun 27 04:40:30 PM PDT 24 Jun 27 04:40:34 PM PDT 24 103166534 ps
T1078 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.461452038 Jun 27 04:41:22 PM PDT 24 Jun 27 04:41:26 PM PDT 24 67534791 ps
T1079 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.296815838 Jun 27 04:41:22 PM PDT 24 Jun 27 04:41:28 PM PDT 24 15275142 ps
T1080 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1359937141 Jun 27 04:40:41 PM PDT 24 Jun 27 04:40:44 PM PDT 24 51844355 ps
T1081 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1633133489 Jun 27 04:40:30 PM PDT 24 Jun 27 04:40:34 PM PDT 24 477915174 ps
T1082 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2102876148 Jun 27 04:41:24 PM PDT 24 Jun 27 04:41:30 PM PDT 24 12772697 ps
T1083 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4222759762 Jun 27 04:41:20 PM PDT 24 Jun 27 04:41:22 PM PDT 24 68201368 ps
T1084 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3731162901 Jun 27 04:41:05 PM PDT 24 Jun 27 04:41:09 PM PDT 24 212046373 ps
T1085 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1850930727 Jun 27 04:40:28 PM PDT 24 Jun 27 04:40:34 PM PDT 24 667247215 ps
T1086 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1091527557 Jun 27 04:41:21 PM PDT 24 Jun 27 04:41:24 PM PDT 24 18484042 ps
T1087 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3731445336 Jun 27 04:40:41 PM PDT 24 Jun 27 04:40:45 PM PDT 24 377665300 ps
T1088 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1012726555 Jun 27 04:41:03 PM PDT 24 Jun 27 04:41:24 PM PDT 24 816369555 ps
T1089 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.633299058 Jun 27 04:41:26 PM PDT 24 Jun 27 04:41:31 PM PDT 24 25101069 ps
T1090 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3215082728 Jun 27 04:40:32 PM PDT 24 Jun 27 04:40:35 PM PDT 24 10528148 ps
T1091 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1985819542 Jun 27 04:40:54 PM PDT 24 Jun 27 04:40:57 PM PDT 24 466576246 ps
T1092 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2517742382 Jun 27 04:41:21 PM PDT 24 Jun 27 04:41:25 PM PDT 24 44360209 ps
T162 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1434178511 Jun 27 04:40:31 PM PDT 24 Jun 27 04:40:37 PM PDT 24 1147603513 ps
T1093 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.842214507 Jun 27 04:40:55 PM PDT 24 Jun 27 04:41:00 PM PDT 24 218002089 ps
T1094 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1227424261 Jun 27 04:41:24 PM PDT 24 Jun 27 04:41:31 PM PDT 24 28879047 ps
T1095 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1339819647 Jun 27 04:40:54 PM PDT 24 Jun 27 04:40:57 PM PDT 24 62071403 ps
T1096 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.84623291 Jun 27 04:40:45 PM PDT 24 Jun 27 04:40:49 PM PDT 24 78150111 ps
T168 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1829875788 Jun 27 04:40:33 PM PDT 24 Jun 27 04:40:53 PM PDT 24 1228586116 ps
T1097 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.921471989 Jun 27 04:40:33 PM PDT 24 Jun 27 04:40:58 PM PDT 24 319046468 ps
T1098 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.328077984 Jun 27 04:40:45 PM PDT 24 Jun 27 04:40:47 PM PDT 24 16549670 ps
T1099 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.222787294 Jun 27 04:41:20 PM PDT 24 Jun 27 04:41:23 PM PDT 24 33546237 ps
T1100 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.4033481711 Jun 27 04:40:40 PM PDT 24 Jun 27 04:40:43 PM PDT 24 263447004 ps
T1101 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.115383284 Jun 27 04:40:41 PM PDT 24 Jun 27 04:40:51 PM PDT 24 1267405112 ps
T1102 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1234920686 Jun 27 04:41:02 PM PDT 24 Jun 27 04:41:08 PM PDT 24 199301214 ps
T1103 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3885332294 Jun 27 04:40:41 PM PDT 24 Jun 27 04:40:44 PM PDT 24 17153638 ps
T1104 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2984524182 Jun 27 04:40:33 PM PDT 24 Jun 27 04:40:39 PM PDT 24 559125927 ps
T1105 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2690367913 Jun 27 04:41:21 PM PDT 24 Jun 27 04:41:25 PM PDT 24 29004396 ps
T1106 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3348768605 Jun 27 04:40:56 PM PDT 24 Jun 27 04:41:00 PM PDT 24 26351816 ps
T1107 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3393183512 Jun 27 04:40:52 PM PDT 24 Jun 27 04:40:57 PM PDT 24 449191768 ps
T1108 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3021031919 Jun 27 04:41:22 PM PDT 24 Jun 27 04:41:27 PM PDT 24 40650591 ps
T1109 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1985062980 Jun 27 04:41:22 PM PDT 24 Jun 27 04:41:29 PM PDT 24 93607162 ps
T1110 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3558016224 Jun 27 04:40:54 PM PDT 24 Jun 27 04:40:59 PM PDT 24 88648973 ps
T1111 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1038933726 Jun 27 04:41:20 PM PDT 24 Jun 27 04:41:23 PM PDT 24 15245282 ps
T1112 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2978199476 Jun 27 04:40:42 PM PDT 24 Jun 27 04:41:02 PM PDT 24 843879679 ps
T1113 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2520894006 Jun 27 04:40:41 PM PDT 24 Jun 27 04:41:05 PM PDT 24 2628615536 ps
T1114 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1223546008 Jun 27 04:40:34 PM PDT 24 Jun 27 04:40:39 PM PDT 24 215348934 ps
T1115 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.291669081 Jun 27 04:40:31 PM PDT 24 Jun 27 04:41:05 PM PDT 24 2082405863 ps
T1116 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2360707588 Jun 27 04:40:55 PM PDT 24 Jun 27 04:41:00 PM PDT 24 22675428 ps
T1117 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3108467341 Jun 27 04:40:31 PM PDT 24 Jun 27 04:40:38 PM PDT 24 3315143907 ps
T1118 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1703769865 Jun 27 04:40:41 PM PDT 24 Jun 27 04:40:44 PM PDT 24 41829455 ps
T1119 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3475034268 Jun 27 04:40:56 PM PDT 24 Jun 27 04:40:59 PM PDT 24 11240548 ps
T1120 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3367939076 Jun 27 04:40:57 PM PDT 24 Jun 27 04:41:04 PM PDT 24 163106765 ps
T166 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.4222161550 Jun 27 04:40:56 PM PDT 24 Jun 27 04:41:21 PM PDT 24 3788840704 ps
T1121 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.329768022 Jun 27 04:40:56 PM PDT 24 Jun 27 04:41:01 PM PDT 24 90701075 ps
T1122 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3010734184 Jun 27 04:41:20 PM PDT 24 Jun 27 04:41:22 PM PDT 24 13972208 ps
T1123 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3074040408 Jun 27 04:40:32 PM PDT 24 Jun 27 04:40:51 PM PDT 24 217032350 ps
T1124 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3769754226 Jun 27 04:41:05 PM PDT 24 Jun 27 04:41:07 PM PDT 24 83264814 ps
T1125 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2943290400 Jun 27 04:40:53 PM PDT 24 Jun 27 04:40:58 PM PDT 24 56858414 ps
T1126 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2657729912 Jun 27 04:40:31 PM PDT 24 Jun 27 04:40:34 PM PDT 24 12504108 ps
T1127 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.236958386 Jun 27 04:41:23 PM PDT 24 Jun 27 04:41:29 PM PDT 24 14483632 ps
T87 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.4138370731 Jun 27 04:40:30 PM PDT 24 Jun 27 04:40:33 PM PDT 24 143586522 ps
T1128 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1895982466 Jun 27 04:40:55 PM PDT 24 Jun 27 04:41:02 PM PDT 24 635587100 ps
T1129 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.983351291 Jun 27 04:40:55 PM PDT 24 Jun 27 04:40:58 PM PDT 24 59048848 ps
T1130 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1578723393 Jun 27 04:40:31 PM PDT 24 Jun 27 04:40:59 PM PDT 24 2516245646 ps
T1131 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1207031970 Jun 27 04:40:58 PM PDT 24 Jun 27 04:41:03 PM PDT 24 352445559 ps
T1132 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1802181791 Jun 27 04:40:52 PM PDT 24 Jun 27 04:40:55 PM PDT 24 99715378 ps
T88 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3271589762 Jun 27 04:40:45 PM PDT 24 Jun 27 04:40:48 PM PDT 24 400963375 ps
T1133 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3541969154 Jun 27 04:40:31 PM PDT 24 Jun 27 04:40:35 PM PDT 24 16554212 ps
T1134 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4150855880 Jun 27 04:40:40 PM PDT 24 Jun 27 04:40:45 PM PDT 24 56556513 ps
T1135 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3184190311 Jun 27 04:40:53 PM PDT 24 Jun 27 04:40:57 PM PDT 24 472834327 ps
T1136 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1791189447 Jun 27 04:40:45 PM PDT 24 Jun 27 04:40:48 PM PDT 24 90825017 ps
T1137 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.932068796 Jun 27 04:41:24 PM PDT 24 Jun 27 04:41:47 PM PDT 24 1204709541 ps
T1138 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2642933642 Jun 27 04:41:20 PM PDT 24 Jun 27 04:41:22 PM PDT 24 17218210 ps
T1139 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3802560451 Jun 27 04:40:59 PM PDT 24 Jun 27 04:41:04 PM PDT 24 135722035 ps
T1140 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2457182280 Jun 27 04:41:26 PM PDT 24 Jun 27 04:41:31 PM PDT 24 56489351 ps
T1141 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3961271660 Jun 27 04:40:57 PM PDT 24 Jun 27 04:41:02 PM PDT 24 346030513 ps
T1142 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.198347124 Jun 27 04:40:29 PM PDT 24 Jun 27 04:40:53 PM PDT 24 443076525 ps
T1143 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3956161367 Jun 27 04:40:54 PM PDT 24 Jun 27 04:40:58 PM PDT 24 17813217 ps
T1144 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3959057189 Jun 27 04:41:18 PM PDT 24 Jun 27 04:41:20 PM PDT 24 15167774 ps
T1145 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1948667667 Jun 27 04:40:53 PM PDT 24 Jun 27 04:40:58 PM PDT 24 203496706 ps
T1146 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1968732313 Jun 27 04:41:04 PM PDT 24 Jun 27 04:41:08 PM PDT 24 502443817 ps
T1147 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1864154292 Jun 27 04:40:53 PM PDT 24 Jun 27 04:40:58 PM PDT 24 399668955 ps
T1148 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1033152101 Jun 27 04:41:20 PM PDT 24 Jun 27 04:41:22 PM PDT 24 16251250 ps
T1149 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1568042789 Jun 27 04:40:31 PM PDT 24 Jun 27 04:40:35 PM PDT 24 234350869 ps

Test location /workspace/coverage/default/3.spi_device_stress_all.1354639991
Short name T10
Test name
Test status
Simulation time 20623389004 ps
CPU time 94.33 seconds
Started Jun 27 04:41:37 PM PDT 24
Finished Jun 27 04:43:13 PM PDT 24
Peak memory 251856 kb
Host smart-3ebadd58-491a-40f9-b8e7-8f04941f7e87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354639991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1354639991
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.442755123
Short name T89
Test name
Test status
Simulation time 6628877492 ps
CPU time 79.5 seconds
Started Jun 27 04:41:22 PM PDT 24
Finished Jun 27 04:42:45 PM PDT 24
Peak memory 249124 kb
Host smart-61d1f548-2a02-4041-baae-a9733e25904b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442755123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.442755123
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.418669318
Short name T13
Test name
Test status
Simulation time 125934945556 ps
CPU time 440.61 seconds
Started Jun 27 04:41:41 PM PDT 24
Finished Jun 27 04:49:05 PM PDT 24
Peak memory 265404 kb
Host smart-b262aafe-b446-4f37-ae13-a827020462a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418669318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.418669318
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2063182955
Short name T94
Test name
Test status
Simulation time 1749654816 ps
CPU time 16 seconds
Started Jun 27 04:41:06 PM PDT 24
Finished Jun 27 04:41:23 PM PDT 24
Peak memory 215556 kb
Host smart-3fef6237-9b5a-4234-9177-19a37fc9cc9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063182955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2063182955
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.662825558
Short name T152
Test name
Test status
Simulation time 56828470393 ps
CPU time 556.54 seconds
Started Jun 27 04:41:57 PM PDT 24
Finished Jun 27 04:51:17 PM PDT 24
Peak memory 257376 kb
Host smart-93ef428a-bea3-4107-b769-873839eeda2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662825558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.662825558
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2536768919
Short name T83
Test name
Test status
Simulation time 50949810803 ps
CPU time 513.66 seconds
Started Jun 27 04:42:43 PM PDT 24
Finished Jun 27 04:51:22 PM PDT 24
Peak memory 281976 kb
Host smart-763b070d-cfcf-475d-8c27-1351372d0612
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536768919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2536768919
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1610097413
Short name T71
Test name
Test status
Simulation time 157310107 ps
CPU time 0.71 seconds
Started Jun 27 04:41:23 PM PDT 24
Finished Jun 27 04:41:28 PM PDT 24
Peak memory 216080 kb
Host smart-315d2b25-39b8-4e4a-ad1a-0d163d52765d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610097413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1610097413
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2079722731
Short name T183
Test name
Test status
Simulation time 3719984512 ps
CPU time 71.76 seconds
Started Jun 27 04:42:11 PM PDT 24
Finished Jun 27 04:43:26 PM PDT 24
Peak memory 255280 kb
Host smart-a94fe84a-04f9-4384-8366-b6cec354f021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079722731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2079722731
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.973726948
Short name T95
Test name
Test status
Simulation time 121237367 ps
CPU time 3.9 seconds
Started Jun 27 04:40:31 PM PDT 24
Finished Jun 27 04:40:37 PM PDT 24
Peak memory 215484 kb
Host smart-708ea5b9-a80a-478e-a86d-e66aa55c804c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973726948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.973726948
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1948812258
Short name T189
Test name
Test status
Simulation time 23216711359 ps
CPU time 249.84 seconds
Started Jun 27 04:43:05 PM PDT 24
Finished Jun 27 04:47:21 PM PDT 24
Peak memory 266384 kb
Host smart-2624ed5f-705d-48f8-932b-c367e02dd5b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948812258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1948812258
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1420022647
Short name T240
Test name
Test status
Simulation time 68741878052 ps
CPU time 673.57 seconds
Started Jun 27 04:43:08 PM PDT 24
Finished Jun 27 04:54:25 PM PDT 24
Peak memory 267024 kb
Host smart-ea1b5b5d-6c5c-4f78-834f-a64644a1de5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420022647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1420022647
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.4189695391
Short name T82
Test name
Test status
Simulation time 73759489161 ps
CPU time 186.53 seconds
Started Jun 27 04:43:31 PM PDT 24
Finished Jun 27 04:46:41 PM PDT 24
Peak memory 266060 kb
Host smart-115fb4ec-63c9-43f7-a38f-74965f2589a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189695391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.4189695391
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1880341717
Short name T14
Test name
Test status
Simulation time 296664994 ps
CPU time 0.96 seconds
Started Jun 27 04:41:40 PM PDT 24
Finished Jun 27 04:41:44 PM PDT 24
Peak memory 235436 kb
Host smart-1d48a9c5-aaae-4748-aac6-9164fc593561
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880341717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1880341717
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.897316357
Short name T143
Test name
Test status
Simulation time 1554386511 ps
CPU time 27.09 seconds
Started Jun 27 04:43:04 PM PDT 24
Finished Jun 27 04:43:36 PM PDT 24
Peak memory 240724 kb
Host smart-8071b6a4-1324-4acb-9b5e-0e52b57fe0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897316357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.897316357
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3708925369
Short name T18
Test name
Test status
Simulation time 281329605735 ps
CPU time 370.57 seconds
Started Jun 27 04:41:49 PM PDT 24
Finished Jun 27 04:48:04 PM PDT 24
Peak memory 256108 kb
Host smart-cf36b01b-764d-475b-91aa-a8068808fe10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708925369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3708925369
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2724552960
Short name T117
Test name
Test status
Simulation time 123997126 ps
CPU time 2.8 seconds
Started Jun 27 04:40:32 PM PDT 24
Finished Jun 27 04:40:37 PM PDT 24
Peak memory 215156 kb
Host smart-ac8cfd94-2c46-4431-b64e-40df13a70f4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724552960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
724552960
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.64764409
Short name T46
Test name
Test status
Simulation time 66539502353 ps
CPU time 398.33 seconds
Started Jun 27 04:42:45 PM PDT 24
Finished Jun 27 04:49:29 PM PDT 24
Peak memory 254648 kb
Host smart-04e12364-2fca-4139-aa40-a88b8d1f0dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64764409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.64764409
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1358567316
Short name T177
Test name
Test status
Simulation time 3138259447 ps
CPU time 74.02 seconds
Started Jun 27 04:43:52 PM PDT 24
Finished Jun 27 04:45:14 PM PDT 24
Peak memory 265256 kb
Host smart-f06ba56e-2051-4ddb-b13c-be9b8589e661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358567316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1358567316
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3073100327
Short name T53
Test name
Test status
Simulation time 43521783868 ps
CPU time 218.41 seconds
Started Jun 27 04:43:35 PM PDT 24
Finished Jun 27 04:47:21 PM PDT 24
Peak memory 281980 kb
Host smart-b659f209-425d-4c92-814d-7d52aa277000
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073100327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3073100327
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3948192626
Short name T35
Test name
Test status
Simulation time 51664453 ps
CPU time 1.01 seconds
Started Jun 27 04:41:56 PM PDT 24
Finished Jun 27 04:42:01 PM PDT 24
Peak memory 217860 kb
Host smart-d07b2897-a333-4021-bf14-20fff7fc144c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948192626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3948192626
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.2246003529
Short name T126
Test name
Test status
Simulation time 22787423220 ps
CPU time 73.73 seconds
Started Jun 27 04:41:40 PM PDT 24
Finished Jun 27 04:42:58 PM PDT 24
Peak memory 249016 kb
Host smart-ed9e0868-67aa-4584-aa71-b9e20357105c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246003529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.2246003529
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.728633344
Short name T23
Test name
Test status
Simulation time 2886803461 ps
CPU time 8.63 seconds
Started Jun 27 04:42:06 PM PDT 24
Finished Jun 27 04:42:19 PM PDT 24
Peak memory 216148 kb
Host smart-e7b75780-1a11-41bb-8959-ae19f36d1c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728633344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.728633344
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1948437779
Short name T256
Test name
Test status
Simulation time 301549752143 ps
CPU time 492.75 seconds
Started Jun 27 04:41:24 PM PDT 24
Finished Jun 27 04:49:41 PM PDT 24
Peak memory 265044 kb
Host smart-b9fd249f-9db1-43a8-a265-396d857226d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948437779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1948437779
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2376376427
Short name T43
Test name
Test status
Simulation time 100913058780 ps
CPU time 220.49 seconds
Started Jun 27 04:42:22 PM PDT 24
Finished Jun 27 04:46:05 PM PDT 24
Peak memory 268852 kb
Host smart-4abc3b28-84cf-4765-8363-559e8fcd4aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376376427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2376376427
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3366014968
Short name T30
Test name
Test status
Simulation time 36585919002 ps
CPU time 322.23 seconds
Started Jun 27 04:41:26 PM PDT 24
Finished Jun 27 04:46:53 PM PDT 24
Peak memory 268960 kb
Host smart-301f4bd9-00db-4c3b-ac1e-f92d4f4c7ea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366014968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3366014968
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3324162511
Short name T323
Test name
Test status
Simulation time 14083503 ps
CPU time 0.67 seconds
Started Jun 27 04:42:06 PM PDT 24
Finished Jun 27 04:42:11 PM PDT 24
Peak memory 204628 kb
Host smart-456bef49-ff72-4768-ab50-6b2885de16c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324162511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3324162511
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1240198287
Short name T44
Test name
Test status
Simulation time 2968942656 ps
CPU time 39.95 seconds
Started Jun 27 04:41:22 PM PDT 24
Finished Jun 27 04:42:06 PM PDT 24
Peak memory 249184 kb
Host smart-b7995ac6-93db-4dd0-9364-49aac8b974d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240198287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1240198287
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3903889649
Short name T252
Test name
Test status
Simulation time 5579040312 ps
CPU time 72.62 seconds
Started Jun 27 04:42:20 PM PDT 24
Finished Jun 27 04:43:36 PM PDT 24
Peak memory 265496 kb
Host smart-047646af-fe77-4db1-803b-a19443f758f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903889649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3903889649
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.465148607
Short name T250
Test name
Test status
Simulation time 483412214315 ps
CPU time 281.1 seconds
Started Jun 27 04:42:41 PM PDT 24
Finished Jun 27 04:47:25 PM PDT 24
Peak memory 252308 kb
Host smart-81a8c874-0ab4-446c-b698-f44a7e7ab56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465148607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.465148607
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3914875192
Short name T106
Test name
Test status
Simulation time 413435952 ps
CPU time 4.76 seconds
Started Jun 27 04:40:30 PM PDT 24
Finished Jun 27 04:40:37 PM PDT 24
Peak memory 215536 kb
Host smart-7943b2bd-44dc-44ae-b680-0b85bfcdf407
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914875192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
914875192
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1829875788
Short name T168
Test name
Test status
Simulation time 1228586116 ps
CPU time 17.51 seconds
Started Jun 27 04:40:33 PM PDT 24
Finished Jun 27 04:40:53 PM PDT 24
Peak memory 215724 kb
Host smart-325fb1b7-33d7-410c-b762-3fd0c78d15cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829875788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1829875788
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.277707773
Short name T890
Test name
Test status
Simulation time 249979431043 ps
CPU time 284.99 seconds
Started Jun 27 04:42:47 PM PDT 24
Finished Jun 27 04:47:38 PM PDT 24
Peak memory 288924 kb
Host smart-3b65aba5-cc7e-40a5-9d4f-417765c9007c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277707773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.277707773
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.947345817
Short name T36
Test name
Test status
Simulation time 23612057174 ps
CPU time 84.9 seconds
Started Jun 27 04:43:33 PM PDT 24
Finished Jun 27 04:45:03 PM PDT 24
Peak memory 255768 kb
Host smart-56702115-5949-4a71-b9f6-7f4130738297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947345817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds
.947345817
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.501883831
Short name T150
Test name
Test status
Simulation time 4018937715 ps
CPU time 24.95 seconds
Started Jun 27 04:40:55 PM PDT 24
Finished Jun 27 04:41:23 PM PDT 24
Peak memory 215380 kb
Host smart-85a0ad8b-1c4c-4d94-94bf-29f1d0a71514
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501883831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.501883831
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.3081704709
Short name T209
Test name
Test status
Simulation time 53715170411 ps
CPU time 390.31 seconds
Started Jun 27 04:42:15 PM PDT 24
Finished Jun 27 04:48:50 PM PDT 24
Peak memory 264524 kb
Host smart-17159cd5-5f83-4ae7-917e-e2ead51b9e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081704709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.3081704709
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2626321973
Short name T273
Test name
Test status
Simulation time 2955377380 ps
CPU time 42.62 seconds
Started Jun 27 04:42:39 PM PDT 24
Finished Jun 27 04:43:23 PM PDT 24
Peak memory 233696 kb
Host smart-597ee7e8-153e-4b6d-9898-cec49045563b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626321973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2626321973
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3063075128
Short name T247
Test name
Test status
Simulation time 12156420729 ps
CPU time 141.04 seconds
Started Jun 27 04:42:45 PM PDT 24
Finished Jun 27 04:45:13 PM PDT 24
Peak memory 273716 kb
Host smart-12cf6220-b0ad-46a8-a920-2118928abf30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063075128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3063075128
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1757345846
Short name T180
Test name
Test status
Simulation time 153829978326 ps
CPU time 760.63 seconds
Started Jun 27 04:42:42 PM PDT 24
Finished Jun 27 04:55:25 PM PDT 24
Peak memory 300084 kb
Host smart-80aab4cc-81b2-4d68-ad31-96f749273463
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757345846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1757345846
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3135096262
Short name T178
Test name
Test status
Simulation time 73742915916 ps
CPU time 232 seconds
Started Jun 27 04:43:37 PM PDT 24
Finished Jun 27 04:47:36 PM PDT 24
Peak memory 262072 kb
Host smart-e4326c13-cf73-4d7c-bc65-f381e7a86fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135096262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3135096262
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3445132054
Short name T6
Test name
Test status
Simulation time 95771090 ps
CPU time 0.86 seconds
Started Jun 27 04:43:34 PM PDT 24
Finished Jun 27 04:43:42 PM PDT 24
Peak memory 205792 kb
Host smart-8c32b2d8-9df4-496f-8d1f-cba49c42e936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445132054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3445132054
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2931909773
Short name T114
Test name
Test status
Simulation time 312814943 ps
CPU time 19.38 seconds
Started Jun 27 04:40:31 PM PDT 24
Finished Jun 27 04:40:53 PM PDT 24
Peak memory 215424 kb
Host smart-a2f563be-3c21-432d-b24b-37890774204e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931909773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2931909773
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.544483457
Short name T113
Test name
Test status
Simulation time 329986787 ps
CPU time 7.45 seconds
Started Jun 27 04:40:41 PM PDT 24
Finished Jun 27 04:40:50 PM PDT 24
Peak memory 215336 kb
Host smart-38a3b0e5-7848-49af-8590-47cd070b1e64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544483457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.544483457
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.4166812941
Short name T171
Test name
Test status
Simulation time 27391077223 ps
CPU time 91.26 seconds
Started Jun 27 04:41:21 PM PDT 24
Finished Jun 27 04:42:56 PM PDT 24
Peak memory 252368 kb
Host smart-29415138-adbf-41a8-8d79-8d88af0abd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166812941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.4166812941
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3672213239
Short name T265
Test name
Test status
Simulation time 4480919188 ps
CPU time 81.04 seconds
Started Jun 27 04:41:23 PM PDT 24
Finished Jun 27 04:42:49 PM PDT 24
Peak memory 250976 kb
Host smart-e263c9e6-3088-4a3a-8e4c-d33aa93a2343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672213239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3672213239
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2482972415
Short name T173
Test name
Test status
Simulation time 14356040248 ps
CPU time 153.97 seconds
Started Jun 27 04:42:03 PM PDT 24
Finished Jun 27 04:44:42 PM PDT 24
Peak memory 254260 kb
Host smart-f756c5ba-6887-4683-8d94-13e206128f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482972415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2482972415
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1891328017
Short name T190
Test name
Test status
Simulation time 52257246196 ps
CPU time 472.83 seconds
Started Jun 27 04:42:00 PM PDT 24
Finished Jun 27 04:49:57 PM PDT 24
Peak memory 254164 kb
Host smart-81ebba05-2192-42e4-9abf-e7cf44bebb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891328017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1891328017
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1835592795
Short name T270
Test name
Test status
Simulation time 59357322 ps
CPU time 4.9 seconds
Started Jun 27 04:43:00 PM PDT 24
Finished Jun 27 04:43:07 PM PDT 24
Peak memory 232596 kb
Host smart-0b0054c5-1c37-41c2-a4df-f921c4fddc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835592795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1835592795
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2775356668
Short name T264
Test name
Test status
Simulation time 173677556591 ps
CPU time 774.4 seconds
Started Jun 27 04:43:38 PM PDT 24
Finished Jun 27 04:56:41 PM PDT 24
Peak memory 273340 kb
Host smart-3025ad77-84e3-4899-abb0-201aabd23141
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775356668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2775356668
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1359214208
Short name T272
Test name
Test status
Simulation time 994189137 ps
CPU time 8.41 seconds
Started Jun 27 04:43:53 PM PDT 24
Finished Jun 27 04:44:08 PM PDT 24
Peak memory 248968 kb
Host smart-c342513c-8a0d-49fa-9dcc-67adecf56e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359214208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1359214208
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.557706593
Short name T1
Test name
Test status
Simulation time 1567161437 ps
CPU time 8.67 seconds
Started Jun 27 04:42:29 PM PDT 24
Finished Jun 27 04:42:41 PM PDT 24
Peak memory 239472 kb
Host smart-e9790b2c-fbb2-40a4-927e-fd3142970a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557706593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.557706593
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.4138370731
Short name T87
Test name
Test status
Simulation time 143586522 ps
CPU time 1.39 seconds
Started Jun 27 04:40:30 PM PDT 24
Finished Jun 27 04:40:33 PM PDT 24
Peak memory 207112 kb
Host smart-145cbd62-7fee-4a1b-842a-b8fd261a392c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138370731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.4138370731
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1895982466
Short name T1128
Test name
Test status
Simulation time 635587100 ps
CPU time 4.28 seconds
Started Jun 27 04:40:55 PM PDT 24
Finished Jun 27 04:41:02 PM PDT 24
Peak memory 215504 kb
Host smart-2215bc69-85d4-4b22-bfda-2ed2ab7aba2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895982466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1895982466
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.198347124
Short name T1142
Test name
Test status
Simulation time 443076525 ps
CPU time 21.73 seconds
Started Jun 27 04:40:29 PM PDT 24
Finished Jun 27 04:40:53 PM PDT 24
Peak memory 206956 kb
Host smart-76500f8c-2799-4a6a-aed0-93d34cc6dd6a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198347124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.198347124
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1578723393
Short name T1130
Test name
Test status
Simulation time 2516245646 ps
CPU time 25.18 seconds
Started Jun 27 04:40:31 PM PDT 24
Finished Jun 27 04:40:59 PM PDT 24
Peak memory 207188 kb
Host smart-98f68121-5570-4e25-9dfd-21833306d056
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578723393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1578723393
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2626466263
Short name T85
Test name
Test status
Simulation time 82422212 ps
CPU time 0.95 seconds
Started Jun 27 04:40:31 PM PDT 24
Finished Jun 27 04:40:35 PM PDT 24
Peak memory 206720 kb
Host smart-44d744eb-a110-49da-9279-039ed8aa0ff2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626466263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2626466263
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3270164616
Short name T149
Test name
Test status
Simulation time 225296157 ps
CPU time 1.75 seconds
Started Jun 27 04:40:28 PM PDT 24
Finished Jun 27 04:40:31 PM PDT 24
Peak memory 215348 kb
Host smart-a6ed027d-acbf-4fcb-a823-6bc04bfd9b51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270164616 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3270164616
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3541969154
Short name T1133
Test name
Test status
Simulation time 16554212 ps
CPU time 0.75 seconds
Started Jun 27 04:40:31 PM PDT 24
Finished Jun 27 04:40:35 PM PDT 24
Peak memory 204284 kb
Host smart-ab11bfdc-2870-46e8-8880-fdda208ef4c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541969154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
541969154
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1636646348
Short name T1075
Test name
Test status
Simulation time 62828987 ps
CPU time 1.21 seconds
Started Jun 27 04:40:31 PM PDT 24
Finished Jun 27 04:40:35 PM PDT 24
Peak memory 215284 kb
Host smart-f5dcde18-8b58-44ec-80b7-c4b3fd36f694
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636646348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1636646348
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2657729912
Short name T1126
Test name
Test status
Simulation time 12504108 ps
CPU time 0.7 seconds
Started Jun 27 04:40:31 PM PDT 24
Finished Jun 27 04:40:34 PM PDT 24
Peak memory 203528 kb
Host smart-cf7b6554-86d5-429f-b408-6107c4194231
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657729912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2657729912
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3257130361
Short name T1035
Test name
Test status
Simulation time 28892435 ps
CPU time 1.96 seconds
Started Jun 27 04:40:31 PM PDT 24
Finished Jun 27 04:40:36 PM PDT 24
Peak memory 215304 kb
Host smart-f2620ba0-c4ed-427f-acfb-71c35cd29696
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257130361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3257130361
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2962289415
Short name T110
Test name
Test status
Simulation time 47867349 ps
CPU time 2.69 seconds
Started Jun 27 04:40:28 PM PDT 24
Finished Jun 27 04:40:33 PM PDT 24
Peak memory 215432 kb
Host smart-35f81229-0b75-4975-8d6d-82774db9d96c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962289415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
962289415
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.115383284
Short name T1101
Test name
Test status
Simulation time 1267405112 ps
CPU time 8.29 seconds
Started Jun 27 04:40:41 PM PDT 24
Finished Jun 27 04:40:51 PM PDT 24
Peak memory 207120 kb
Host smart-527503d1-18f0-4804-aebc-c71f83d9d3e2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115383284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.115383284
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.430721379
Short name T1031
Test name
Test status
Simulation time 657589685 ps
CPU time 13.24 seconds
Started Jun 27 04:40:30 PM PDT 24
Finished Jun 27 04:40:46 PM PDT 24
Peak memory 206648 kb
Host smart-5463b28f-26f3-460c-9476-113d7fecfa2a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430721379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.430721379
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3354932443
Short name T1046
Test name
Test status
Simulation time 53707175 ps
CPU time 3.78 seconds
Started Jun 27 04:40:32 PM PDT 24
Finished Jun 27 04:40:38 PM PDT 24
Peak memory 217524 kb
Host smart-f53b4bcc-769c-44b0-87f4-6c9559572171
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354932443 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3354932443
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1633133489
Short name T1081
Test name
Test status
Simulation time 477915174 ps
CPU time 2.14 seconds
Started Jun 27 04:40:30 PM PDT 24
Finished Jun 27 04:40:34 PM PDT 24
Peak memory 214800 kb
Host smart-3b3561b6-e986-43b5-a94b-0fee17229be9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633133489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
633133489
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3215082728
Short name T1090
Test name
Test status
Simulation time 10528148 ps
CPU time 0.69 seconds
Started Jun 27 04:40:32 PM PDT 24
Finished Jun 27 04:40:35 PM PDT 24
Peak memory 203956 kb
Host smart-9cd0a4c1-67bf-43ea-b994-0a1081e3fe82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215082728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
215082728
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3885332294
Short name T1103
Test name
Test status
Simulation time 17153638 ps
CPU time 1.29 seconds
Started Jun 27 04:40:41 PM PDT 24
Finished Jun 27 04:40:44 PM PDT 24
Peak memory 215332 kb
Host smart-6421b2d8-04af-4794-a703-8ec885ae8acf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885332294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3885332294
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.303737832
Short name T1028
Test name
Test status
Simulation time 43024166 ps
CPU time 0.65 seconds
Started Jun 27 04:40:27 PM PDT 24
Finished Jun 27 04:40:28 PM PDT 24
Peak memory 203908 kb
Host smart-ab723b71-084d-4f5a-9ac9-177e458b9db6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303737832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.303737832
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2038886432
Short name T1070
Test name
Test status
Simulation time 59609729 ps
CPU time 3.98 seconds
Started Jun 27 04:40:32 PM PDT 24
Finished Jun 27 04:40:39 PM PDT 24
Peak memory 215384 kb
Host smart-8a391231-52f1-429d-af0a-46a4eb5fa0d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038886432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2038886432
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2808908857
Short name T1063
Test name
Test status
Simulation time 110428555 ps
CPU time 3.73 seconds
Started Jun 27 04:40:53 PM PDT 24
Finished Jun 27 04:40:59 PM PDT 24
Peak memory 217360 kb
Host smart-bb81d63e-3b77-4685-8f51-9155841e97fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808908857 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2808908857
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1258882251
Short name T121
Test name
Test status
Simulation time 352803301 ps
CPU time 2.16 seconds
Started Jun 27 04:40:59 PM PDT 24
Finished Jun 27 04:41:03 PM PDT 24
Peak memory 215328 kb
Host smart-72faecbc-22c7-46c9-966e-286f0d380ea5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258882251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1258882251
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1599501573
Short name T1051
Test name
Test status
Simulation time 63925033 ps
CPU time 0.73 seconds
Started Jun 27 04:40:55 PM PDT 24
Finished Jun 27 04:40:59 PM PDT 24
Peak memory 203696 kb
Host smart-45e174a7-f198-42d4-95b7-25334a9455d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599501573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1599501573
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1441005900
Short name T1074
Test name
Test status
Simulation time 736316060 ps
CPU time 3.9 seconds
Started Jun 27 04:40:54 PM PDT 24
Finished Jun 27 04:41:01 PM PDT 24
Peak memory 215216 kb
Host smart-8a112121-46e1-4352-9642-06b0a35d75c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441005900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1441005900
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3177432015
Short name T112
Test name
Test status
Simulation time 1495870365 ps
CPU time 16.57 seconds
Started Jun 27 04:40:53 PM PDT 24
Finished Jun 27 04:41:12 PM PDT 24
Peak memory 215276 kb
Host smart-fb5a70c1-25c5-4afa-af48-dbe93a4606c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177432015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3177432015
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.842214507
Short name T1093
Test name
Test status
Simulation time 218002089 ps
CPU time 1.74 seconds
Started Jun 27 04:40:55 PM PDT 24
Finished Jun 27 04:41:00 PM PDT 24
Peak memory 215380 kb
Host smart-2644e349-bedb-4d29-9e17-9168527d344e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842214507 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.842214507
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.80784254
Short name T124
Test name
Test status
Simulation time 36338815 ps
CPU time 2.51 seconds
Started Jun 27 04:40:57 PM PDT 24
Finished Jun 27 04:41:02 PM PDT 24
Peak memory 215196 kb
Host smart-58bb3d71-50b9-4eb4-9e4d-51667f931242
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80784254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.80784254
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3045251658
Short name T1052
Test name
Test status
Simulation time 28928684 ps
CPU time 0.7 seconds
Started Jun 27 04:40:56 PM PDT 24
Finished Jun 27 04:41:00 PM PDT 24
Peak memory 204036 kb
Host smart-af914127-86b0-47ed-a3f7-eae8646d355b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045251658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3045251658
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3184190311
Short name T1135
Test name
Test status
Simulation time 472834327 ps
CPU time 1.96 seconds
Started Jun 27 04:40:53 PM PDT 24
Finished Jun 27 04:40:57 PM PDT 24
Peak memory 207108 kb
Host smart-706a26d0-c741-4583-9297-03a290f46a1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184190311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3184190311
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1527003719
Short name T102
Test name
Test status
Simulation time 72755841 ps
CPU time 2.02 seconds
Started Jun 27 04:41:02 PM PDT 24
Finished Jun 27 04:41:05 PM PDT 24
Peak memory 215688 kb
Host smart-a395abaa-2bb9-4643-bc6b-bc3f7c91630d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527003719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1527003719
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2415291642
Short name T167
Test name
Test status
Simulation time 2144497714 ps
CPU time 24.08 seconds
Started Jun 27 04:40:55 PM PDT 24
Finished Jun 27 04:41:22 PM PDT 24
Peak memory 215748 kb
Host smart-75945b77-1af5-405e-b2cd-ed5069ce0214
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415291642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2415291642
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4264041697
Short name T107
Test name
Test status
Simulation time 496246836 ps
CPU time 2.97 seconds
Started Jun 27 04:40:54 PM PDT 24
Finished Jun 27 04:40:59 PM PDT 24
Peak memory 216712 kb
Host smart-91dcc2e5-4a0f-440e-812a-0dd8f2ef4452
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264041697 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.4264041697
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3558016224
Short name T1110
Test name
Test status
Simulation time 88648973 ps
CPU time 2.27 seconds
Started Jun 27 04:40:54 PM PDT 24
Finished Jun 27 04:40:59 PM PDT 24
Peak memory 206956 kb
Host smart-0e382814-d2c9-4f47-90bc-c3eacb619432
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558016224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3558016224
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.983351291
Short name T1129
Test name
Test status
Simulation time 59048848 ps
CPU time 0.8 seconds
Started Jun 27 04:40:55 PM PDT 24
Finished Jun 27 04:40:58 PM PDT 24
Peak memory 203936 kb
Host smart-ab7f1f50-6993-495e-a8da-d671c0634a55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983351291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.983351291
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4229039131
Short name T1047
Test name
Test status
Simulation time 834425328 ps
CPU time 2.87 seconds
Started Jun 27 04:41:00 PM PDT 24
Finished Jun 27 04:41:04 PM PDT 24
Peak memory 215388 kb
Host smart-8fe23e78-fd08-4a4f-b267-bd093bb2a48f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229039131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.4229039131
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3769754226
Short name T1124
Test name
Test status
Simulation time 83264814 ps
CPU time 1.48 seconds
Started Jun 27 04:41:05 PM PDT 24
Finished Jun 27 04:41:07 PM PDT 24
Peak memory 215356 kb
Host smart-b88c49a7-7e6f-487a-8338-fee7f9e6e488
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769754226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3769754226
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3991299359
Short name T1053
Test name
Test status
Simulation time 115442482 ps
CPU time 6.62 seconds
Started Jun 27 04:41:00 PM PDT 24
Finished Jun 27 04:41:08 PM PDT 24
Peak memory 215336 kb
Host smart-4c2042b3-7a47-4660-9a29-913496cc4bd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991299359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3991299359
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2682798382
Short name T99
Test name
Test status
Simulation time 279227510 ps
CPU time 3.89 seconds
Started Jun 27 04:40:52 PM PDT 24
Finished Jun 27 04:40:58 PM PDT 24
Peak memory 217184 kb
Host smart-46e66d1b-c6ee-43d0-afc9-b65429e0af1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682798382 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2682798382
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3956161367
Short name T1143
Test name
Test status
Simulation time 17813217 ps
CPU time 1.25 seconds
Started Jun 27 04:40:54 PM PDT 24
Finished Jun 27 04:40:58 PM PDT 24
Peak memory 207040 kb
Host smart-b1367d37-88f5-4e0f-a681-93fd70a456a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956161367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3956161367
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2252174477
Short name T1037
Test name
Test status
Simulation time 16040217 ps
CPU time 0.72 seconds
Started Jun 27 04:40:54 PM PDT 24
Finished Jun 27 04:40:58 PM PDT 24
Peak memory 203644 kb
Host smart-9b721ce6-23f4-498c-8820-47d88f8dd6a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252174477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2252174477
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1985819542
Short name T1091
Test name
Test status
Simulation time 466576246 ps
CPU time 1.7 seconds
Started Jun 27 04:40:54 PM PDT 24
Finished Jun 27 04:40:57 PM PDT 24
Peak memory 215272 kb
Host smart-c89c6054-b1e1-4e56-9994-be8a9c3e2af6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985819542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1985819542
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3393183512
Short name T1107
Test name
Test status
Simulation time 449191768 ps
CPU time 3.16 seconds
Started Jun 27 04:40:52 PM PDT 24
Finished Jun 27 04:40:57 PM PDT 24
Peak memory 215408 kb
Host smart-82ccfede-3385-4905-9bf4-476add4c582a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393183512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3393183512
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3856167260
Short name T164
Test name
Test status
Simulation time 1103768525 ps
CPU time 25.54 seconds
Started Jun 27 04:40:54 PM PDT 24
Finished Jun 27 04:41:22 PM PDT 24
Peak memory 215352 kb
Host smart-6cf64411-4800-43fa-afe5-d12a11640593
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856167260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3856167260
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.989622597
Short name T1045
Test name
Test status
Simulation time 302340780 ps
CPU time 3.31 seconds
Started Jun 27 04:40:54 PM PDT 24
Finished Jun 27 04:40:59 PM PDT 24
Peak memory 217564 kb
Host smart-dab91bd8-245b-4231-99c2-125d96731e8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989622597 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.989622597
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1339819647
Short name T1095
Test name
Test status
Simulation time 62071403 ps
CPU time 1.24 seconds
Started Jun 27 04:40:54 PM PDT 24
Finished Jun 27 04:40:57 PM PDT 24
Peak memory 215244 kb
Host smart-ccd34c5c-5eb2-4239-bd8a-04e09271a36c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339819647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1339819647
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.890152078
Short name T1072
Test name
Test status
Simulation time 14157659 ps
CPU time 0.68 seconds
Started Jun 27 04:41:00 PM PDT 24
Finished Jun 27 04:41:02 PM PDT 24
Peak memory 203716 kb
Host smart-9182bc68-3242-4b48-ad06-cadca8cc332b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890152078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.890152078
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3367939076
Short name T1120
Test name
Test status
Simulation time 163106765 ps
CPU time 4.41 seconds
Started Jun 27 04:40:57 PM PDT 24
Finished Jun 27 04:41:04 PM PDT 24
Peak memory 215324 kb
Host smart-8724bda2-903b-471b-b496-434bbe3a5d3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367939076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3367939076
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.622681648
Short name T105
Test name
Test status
Simulation time 281431490 ps
CPU time 5.18 seconds
Started Jun 27 04:41:03 PM PDT 24
Finished Jun 27 04:41:09 PM PDT 24
Peak memory 215504 kb
Host smart-a5806036-ed2c-459f-8eb0-962570dcd3b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622681648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.622681648
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.329768022
Short name T1121
Test name
Test status
Simulation time 90701075 ps
CPU time 1.82 seconds
Started Jun 27 04:40:56 PM PDT 24
Finished Jun 27 04:41:01 PM PDT 24
Peak memory 215696 kb
Host smart-96a1c271-8822-4c7a-9c11-ff79e2b7b48d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329768022 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.329768022
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2360707588
Short name T1116
Test name
Test status
Simulation time 22675428 ps
CPU time 1.38 seconds
Started Jun 27 04:40:55 PM PDT 24
Finished Jun 27 04:41:00 PM PDT 24
Peak memory 207000 kb
Host smart-0ddaf34a-da9b-46e2-adbd-6055f8fee573
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360707588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2360707588
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1983032230
Short name T1062
Test name
Test status
Simulation time 49381538 ps
CPU time 0.75 seconds
Started Jun 27 04:40:55 PM PDT 24
Finished Jun 27 04:40:59 PM PDT 24
Peak memory 203676 kb
Host smart-c66b58de-afdc-4efd-a097-9de3ed97c568
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983032230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1983032230
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1948667667
Short name T1145
Test name
Test status
Simulation time 203496706 ps
CPU time 3.9 seconds
Started Jun 27 04:40:53 PM PDT 24
Finished Jun 27 04:40:58 PM PDT 24
Peak memory 215348 kb
Host smart-d481966c-bc98-46be-8d95-0b3d6bf0a38f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948667667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1948667667
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3207372497
Short name T100
Test name
Test status
Simulation time 620067657 ps
CPU time 3.68 seconds
Started Jun 27 04:40:54 PM PDT 24
Finished Jun 27 04:41:00 PM PDT 24
Peak memory 215440 kb
Host smart-ca19907c-0572-4239-b39f-8c1cd19ff21f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207372497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3207372497
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1012726555
Short name T1088
Test name
Test status
Simulation time 816369555 ps
CPU time 20.43 seconds
Started Jun 27 04:41:03 PM PDT 24
Finished Jun 27 04:41:24 PM PDT 24
Peak memory 215324 kb
Host smart-c2aab912-60fe-40c4-82f1-09cbc8e391d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012726555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1012726555
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2113087864
Short name T111
Test name
Test status
Simulation time 334047285 ps
CPU time 2.49 seconds
Started Jun 27 04:40:55 PM PDT 24
Finished Jun 27 04:41:01 PM PDT 24
Peak memory 216304 kb
Host smart-18b42c0d-9e5d-41b1-95e5-4d3ddcb12165
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113087864 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2113087864
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1207031970
Short name T1131
Test name
Test status
Simulation time 352445559 ps
CPU time 2.52 seconds
Started Jun 27 04:40:58 PM PDT 24
Finished Jun 27 04:41:03 PM PDT 24
Peak memory 207108 kb
Host smart-138f9ec1-b217-4915-8475-dceed3f09292
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207031970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1207031970
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2765760867
Short name T1032
Test name
Test status
Simulation time 33232819 ps
CPU time 0.71 seconds
Started Jun 27 04:41:03 PM PDT 24
Finished Jun 27 04:41:05 PM PDT 24
Peak memory 203932 kb
Host smart-b6cf368d-11f2-4804-9729-63ec26f0bbc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765760867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2765760867
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3802560451
Short name T1139
Test name
Test status
Simulation time 135722035 ps
CPU time 2.96 seconds
Started Jun 27 04:40:59 PM PDT 24
Finished Jun 27 04:41:04 PM PDT 24
Peak memory 215256 kb
Host smart-f66ca3af-ff58-456d-a9d4-a25ff859534e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802560451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3802560451
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1234920686
Short name T1102
Test name
Test status
Simulation time 199301214 ps
CPU time 4.69 seconds
Started Jun 27 04:41:02 PM PDT 24
Finished Jun 27 04:41:08 PM PDT 24
Peak memory 216576 kb
Host smart-dbc98d5c-0685-41d5-b738-14f2fce9464a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234920686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1234920686
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1111071128
Short name T1065
Test name
Test status
Simulation time 360712826 ps
CPU time 9.34 seconds
Started Jun 27 04:40:53 PM PDT 24
Finished Jun 27 04:41:04 PM PDT 24
Peak memory 215404 kb
Host smart-b59afd01-cbb0-4808-8fbd-590c642ed7a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111071128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1111071128
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2443034297
Short name T1060
Test name
Test status
Simulation time 409376893 ps
CPU time 3.15 seconds
Started Jun 27 04:41:22 PM PDT 24
Finished Jun 27 04:41:30 PM PDT 24
Peak memory 217884 kb
Host smart-fdcb59f9-cbc8-4e60-8f1e-48f2340648d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443034297 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2443034297
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3343049894
Short name T125
Test name
Test status
Simulation time 134523138 ps
CPU time 2 seconds
Started Jun 27 04:40:56 PM PDT 24
Finished Jun 27 04:41:01 PM PDT 24
Peak memory 207076 kb
Host smart-03c505f3-1db4-4d72-b25a-af22365b6b7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343049894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3343049894
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.623274923
Short name T1033
Test name
Test status
Simulation time 30928469 ps
CPU time 0.74 seconds
Started Jun 27 04:41:04 PM PDT 24
Finished Jun 27 04:41:05 PM PDT 24
Peak memory 203612 kb
Host smart-1e464583-731f-464d-bae8-5a864972f1f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623274923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.623274923
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1864154292
Short name T1147
Test name
Test status
Simulation time 399668955 ps
CPU time 3.98 seconds
Started Jun 27 04:40:53 PM PDT 24
Finished Jun 27 04:40:58 PM PDT 24
Peak memory 215344 kb
Host smart-d9e932d1-a27a-489e-9ba0-f643765b24c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864154292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1864154292
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.693182325
Short name T1071
Test name
Test status
Simulation time 185626084 ps
CPU time 3.46 seconds
Started Jun 27 04:40:56 PM PDT 24
Finished Jun 27 04:41:02 PM PDT 24
Peak memory 215496 kb
Host smart-87f74fb7-aa9a-40d4-b293-b0b50f4b2b0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693182325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.693182325
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.4222161550
Short name T166
Test name
Test status
Simulation time 3788840704 ps
CPU time 22.06 seconds
Started Jun 27 04:40:56 PM PDT 24
Finished Jun 27 04:41:21 PM PDT 24
Peak memory 215708 kb
Host smart-04e83488-6ab2-47a6-935f-80461aeddd70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222161550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.4222161550
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3878884484
Short name T108
Test name
Test status
Simulation time 215468124 ps
CPU time 2.7 seconds
Started Jun 27 04:41:19 PM PDT 24
Finished Jun 27 04:41:23 PM PDT 24
Peak memory 217788 kb
Host smart-28bf66ac-b7a5-48e5-84f5-123020ff8046
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878884484 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3878884484
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3597765724
Short name T120
Test name
Test status
Simulation time 88427837 ps
CPU time 2.62 seconds
Started Jun 27 04:41:25 PM PDT 24
Finished Jun 27 04:41:32 PM PDT 24
Peak memory 215156 kb
Host smart-fc0c916f-55a6-4da4-b04c-ce15c54def66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597765724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3597765724
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3535385502
Short name T1039
Test name
Test status
Simulation time 14576465 ps
CPU time 0.69 seconds
Started Jun 27 04:41:21 PM PDT 24
Finished Jun 27 04:41:26 PM PDT 24
Peak memory 203620 kb
Host smart-c99c46e3-fbc9-40ec-9d6b-b91624ba18f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535385502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3535385502
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1227424261
Short name T1094
Test name
Test status
Simulation time 28879047 ps
CPU time 1.76 seconds
Started Jun 27 04:41:24 PM PDT 24
Finished Jun 27 04:41:31 PM PDT 24
Peak memory 215148 kb
Host smart-52a7176e-a32c-45af-bea6-3ca53b85dd65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227424261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1227424261
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2711493688
Short name T103
Test name
Test status
Simulation time 318078428 ps
CPU time 4.4 seconds
Started Jun 27 04:41:19 PM PDT 24
Finished Jun 27 04:41:25 PM PDT 24
Peak memory 215428 kb
Host smart-1e91dfeb-de0c-4894-90d6-1cfdd484d53f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711493688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2711493688
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.418786559
Short name T163
Test name
Test status
Simulation time 3349137449 ps
CPU time 20.24 seconds
Started Jun 27 04:41:21 PM PDT 24
Finished Jun 27 04:41:45 PM PDT 24
Peak memory 215628 kb
Host smart-d25cf326-c7e5-4317-b06b-6e7d7012cef8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418786559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.418786559
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2256668643
Short name T98
Test name
Test status
Simulation time 50193350 ps
CPU time 3.14 seconds
Started Jun 27 04:41:25 PM PDT 24
Finished Jun 27 04:41:33 PM PDT 24
Peak memory 218416 kb
Host smart-035c638f-e944-4853-bf27-71940928bb52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256668643 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2256668643
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1985062980
Short name T1109
Test name
Test status
Simulation time 93607162 ps
CPU time 2.84 seconds
Started Jun 27 04:41:22 PM PDT 24
Finished Jun 27 04:41:29 PM PDT 24
Peak memory 215140 kb
Host smart-2a99e418-2793-46af-982f-d6678c23ab8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985062980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1985062980
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3959057189
Short name T1144
Test name
Test status
Simulation time 15167774 ps
CPU time 0.71 seconds
Started Jun 27 04:41:18 PM PDT 24
Finished Jun 27 04:41:20 PM PDT 24
Peak memory 203604 kb
Host smart-22dd2e1f-6cb4-4edf-b9d8-11b31db25db6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959057189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3959057189
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2111899195
Short name T1040
Test name
Test status
Simulation time 297992728 ps
CPU time 2.11 seconds
Started Jun 27 04:41:21 PM PDT 24
Finished Jun 27 04:41:26 PM PDT 24
Peak memory 215268 kb
Host smart-745081cb-56fe-4acd-90dc-bc5159d7bcf7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111899195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2111899195
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1875822605
Short name T101
Test name
Test status
Simulation time 930189082 ps
CPU time 1.65 seconds
Started Jun 27 04:41:22 PM PDT 24
Finished Jun 27 04:41:28 PM PDT 24
Peak memory 215396 kb
Host smart-0876516f-5155-47cd-a452-f64607d223cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875822605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1875822605
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.932068796
Short name T1137
Test name
Test status
Simulation time 1204709541 ps
CPU time 18.77 seconds
Started Jun 27 04:41:24 PM PDT 24
Finished Jun 27 04:41:47 PM PDT 24
Peak memory 215888 kb
Host smart-49d35652-8962-49ff-8e05-eb53590747b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932068796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.932068796
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3074040408
Short name T1123
Test name
Test status
Simulation time 217032350 ps
CPU time 15.95 seconds
Started Jun 27 04:40:32 PM PDT 24
Finished Jun 27 04:40:51 PM PDT 24
Peak memory 215208 kb
Host smart-1cb948d4-8cd7-49ad-a866-1ba794f5cb2a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074040408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3074040408
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2520894006
Short name T1113
Test name
Test status
Simulation time 2628615536 ps
CPU time 22.18 seconds
Started Jun 27 04:40:41 PM PDT 24
Finished Jun 27 04:41:05 PM PDT 24
Peak memory 207084 kb
Host smart-42a73ef8-b3e4-4eba-8be6-b65d5a5e45ca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520894006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2520894006
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3208198934
Short name T84
Test name
Test status
Simulation time 179506399 ps
CPU time 1.47 seconds
Started Jun 27 04:40:30 PM PDT 24
Finished Jun 27 04:40:35 PM PDT 24
Peak memory 206948 kb
Host smart-f0f1b89c-42a2-41b8-a448-b44a02246fda
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208198934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3208198934
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1359937141
Short name T1080
Test name
Test status
Simulation time 51844355 ps
CPU time 1.68 seconds
Started Jun 27 04:40:41 PM PDT 24
Finished Jun 27 04:40:44 PM PDT 24
Peak memory 216456 kb
Host smart-25d64800-dfbd-4d90-b090-c16c6a4ffa8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359937141 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1359937141
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2599976680
Short name T1066
Test name
Test status
Simulation time 90944524 ps
CPU time 2.62 seconds
Started Jun 27 04:40:32 PM PDT 24
Finished Jun 27 04:40:38 PM PDT 24
Peak memory 215212 kb
Host smart-ef5fa4d8-0ecd-40f4-83cf-ee327f3fa250
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599976680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
599976680
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1703769865
Short name T1118
Test name
Test status
Simulation time 41829455 ps
CPU time 0.77 seconds
Started Jun 27 04:40:41 PM PDT 24
Finished Jun 27 04:40:44 PM PDT 24
Peak memory 203788 kb
Host smart-ed177f68-16a4-43e6-bc47-c0a94bb670ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703769865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
703769865
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2892251947
Short name T1064
Test name
Test status
Simulation time 111893273 ps
CPU time 2.11 seconds
Started Jun 27 04:40:41 PM PDT 24
Finished Jun 27 04:40:44 PM PDT 24
Peak memory 215368 kb
Host smart-69f4277b-aceb-4a1a-b233-3a840aa04ab6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892251947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2892251947
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1018469977
Short name T1027
Test name
Test status
Simulation time 13675476 ps
CPU time 0.67 seconds
Started Jun 27 04:40:31 PM PDT 24
Finished Jun 27 04:40:34 PM PDT 24
Peak memory 203524 kb
Host smart-defbdd5f-0568-492a-8275-5be6a93872f8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018469977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1018469977
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3170776565
Short name T140
Test name
Test status
Simulation time 118396999 ps
CPU time 1.86 seconds
Started Jun 27 04:40:40 PM PDT 24
Finished Jun 27 04:40:43 PM PDT 24
Peak memory 215352 kb
Host smart-2607f7ba-31c2-445a-9faa-ce373db876e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170776565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3170776565
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1434178511
Short name T162
Test name
Test status
Simulation time 1147603513 ps
CPU time 3.2 seconds
Started Jun 27 04:40:31 PM PDT 24
Finished Jun 27 04:40:37 PM PDT 24
Peak memory 215520 kb
Host smart-8c5c70e5-41cb-4d1a-be3f-2200f85b46f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434178511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
434178511
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2102876148
Short name T1082
Test name
Test status
Simulation time 12772697 ps
CPU time 0.75 seconds
Started Jun 27 04:41:24 PM PDT 24
Finished Jun 27 04:41:30 PM PDT 24
Peak memory 203648 kb
Host smart-57584cc0-5fe0-42d2-89cd-99281965a93b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102876148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2102876148
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2642933642
Short name T1138
Test name
Test status
Simulation time 17218210 ps
CPU time 0.72 seconds
Started Jun 27 04:41:20 PM PDT 24
Finished Jun 27 04:41:22 PM PDT 24
Peak memory 203764 kb
Host smart-bd577d8c-0260-4a65-9ea9-6fa4efd479db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642933642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2642933642
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2945666729
Short name T1036
Test name
Test status
Simulation time 21032127 ps
CPU time 0.75 seconds
Started Jun 27 04:41:18 PM PDT 24
Finished Jun 27 04:41:20 PM PDT 24
Peak memory 203696 kb
Host smart-00c79655-054f-4c4a-9afd-108a5c90e98a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945666729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2945666729
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3010734184
Short name T1122
Test name
Test status
Simulation time 13972208 ps
CPU time 0.76 seconds
Started Jun 27 04:41:20 PM PDT 24
Finished Jun 27 04:41:22 PM PDT 24
Peak memory 203708 kb
Host smart-ba8406ba-20a6-48e9-a4a1-89b9801ee6fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010734184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3010734184
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2762829043
Short name T1049
Test name
Test status
Simulation time 24440440 ps
CPU time 0.75 seconds
Started Jun 27 04:41:23 PM PDT 24
Finished Jun 27 04:41:28 PM PDT 24
Peak memory 204044 kb
Host smart-c85a8dab-e9f9-4a0c-994d-e94bf017f9c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762829043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2762829043
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2208384788
Short name T1056
Test name
Test status
Simulation time 11677142 ps
CPU time 0.73 seconds
Started Jun 27 04:41:19 PM PDT 24
Finished Jun 27 04:41:21 PM PDT 24
Peak memory 203680 kb
Host smart-b50840e1-86d0-420b-8c09-99b613cf541d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208384788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2208384788
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.296815838
Short name T1079
Test name
Test status
Simulation time 15275142 ps
CPU time 0.7 seconds
Started Jun 27 04:41:22 PM PDT 24
Finished Jun 27 04:41:28 PM PDT 24
Peak memory 203584 kb
Host smart-16b1cdee-3ba7-436b-922c-efa7b025bb9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296815838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.296815838
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2457182280
Short name T1140
Test name
Test status
Simulation time 56489351 ps
CPU time 0.77 seconds
Started Jun 27 04:41:26 PM PDT 24
Finished Jun 27 04:41:31 PM PDT 24
Peak memory 203660 kb
Host smart-f6b4edbd-3332-4e27-89c2-9c1c8fad4225
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457182280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2457182280
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.569065808
Short name T1025
Test name
Test status
Simulation time 42859702 ps
CPU time 0.73 seconds
Started Jun 27 04:41:20 PM PDT 24
Finished Jun 27 04:41:23 PM PDT 24
Peak memory 204056 kb
Host smart-7e5e4c4c-1e82-4546-ac6d-ce3cc51463f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569065808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.569065808
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1185939281
Short name T1054
Test name
Test status
Simulation time 52081232 ps
CPU time 0.72 seconds
Started Jun 27 04:41:20 PM PDT 24
Finished Jun 27 04:41:22 PM PDT 24
Peak memory 203640 kb
Host smart-b46b0491-7a8b-4673-9cbd-af5f5cdfbf33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185939281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1185939281
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.921471989
Short name T1097
Test name
Test status
Simulation time 319046468 ps
CPU time 22.1 seconds
Started Jun 27 04:40:33 PM PDT 24
Finished Jun 27 04:40:58 PM PDT 24
Peak memory 215240 kb
Host smart-7b4464e2-84df-48db-8cb8-281652ada85e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921471989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.921471989
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.291669081
Short name T1115
Test name
Test status
Simulation time 2082405863 ps
CPU time 30.94 seconds
Started Jun 27 04:40:31 PM PDT 24
Finished Jun 27 04:41:05 PM PDT 24
Peak memory 207056 kb
Host smart-1471edaa-e183-4a1a-89dc-1509457cd5e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291669081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.291669081
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3271589762
Short name T88
Test name
Test status
Simulation time 400963375 ps
CPU time 1.34 seconds
Started Jun 27 04:40:45 PM PDT 24
Finished Jun 27 04:40:48 PM PDT 24
Peak memory 206964 kb
Host smart-75981f79-66e7-4c46-ae88-60a81f650a5a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271589762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3271589762
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.84623291
Short name T1096
Test name
Test status
Simulation time 78150111 ps
CPU time 2.79 seconds
Started Jun 27 04:40:45 PM PDT 24
Finished Jun 27 04:40:49 PM PDT 24
Peak memory 217408 kb
Host smart-1559f43f-3aba-4ceb-97a7-f609f929db55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84623291 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.84623291
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1791189447
Short name T1136
Test name
Test status
Simulation time 90825017 ps
CPU time 2.47 seconds
Started Jun 27 04:40:45 PM PDT 24
Finished Jun 27 04:40:48 PM PDT 24
Peak memory 215168 kb
Host smart-37fb19b1-0ea1-457c-9c64-23d303ec8906
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791189447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
791189447
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1024356669
Short name T1057
Test name
Test status
Simulation time 50651045 ps
CPU time 0.74 seconds
Started Jun 27 04:40:30 PM PDT 24
Finished Jun 27 04:40:33 PM PDT 24
Peak memory 203712 kb
Host smart-d2eea33e-29b3-4dcf-93e2-8eb952bbb968
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024356669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
024356669
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.872800395
Short name T123
Test name
Test status
Simulation time 129942070 ps
CPU time 1.41 seconds
Started Jun 27 04:40:32 PM PDT 24
Finished Jun 27 04:40:36 PM PDT 24
Peak memory 215276 kb
Host smart-e3471d09-2a3a-4994-bbe4-6e3fe76abe48
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872800395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.872800395
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.549520307
Short name T1042
Test name
Test status
Simulation time 34831103 ps
CPU time 0.64 seconds
Started Jun 27 04:40:45 PM PDT 24
Finished Jun 27 04:40:47 PM PDT 24
Peak memory 203464 kb
Host smart-3bb47713-52c5-4aa5-bec7-38158fb9437b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549520307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.549520307
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2984524182
Short name T1104
Test name
Test status
Simulation time 559125927 ps
CPU time 3.38 seconds
Started Jun 27 04:40:33 PM PDT 24
Finished Jun 27 04:40:39 PM PDT 24
Peak memory 215360 kb
Host smart-558d1106-fde1-44de-b858-cd3f563699c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984524182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2984524182
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2203603399
Short name T1050
Test name
Test status
Simulation time 1432323505 ps
CPU time 5.08 seconds
Started Jun 27 04:40:29 PM PDT 24
Finished Jun 27 04:40:37 PM PDT 24
Peak memory 215472 kb
Host smart-230d426d-fba0-4153-a109-3e89ad1ae370
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203603399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
203603399
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3119682615
Short name T115
Test name
Test status
Simulation time 138013616 ps
CPU time 5.76 seconds
Started Jun 27 04:40:41 PM PDT 24
Finished Jun 27 04:40:48 PM PDT 24
Peak memory 215432 kb
Host smart-c6aa6f67-c1e8-417f-a49f-1dcd7ebb8e9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119682615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3119682615
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.633299058
Short name T1089
Test name
Test status
Simulation time 25101069 ps
CPU time 0.73 seconds
Started Jun 27 04:41:26 PM PDT 24
Finished Jun 27 04:41:31 PM PDT 24
Peak memory 203668 kb
Host smart-dc60dc40-0a76-47f3-a0fe-92e68918f955
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633299058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.633299058
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.222787294
Short name T1099
Test name
Test status
Simulation time 33546237 ps
CPU time 0.68 seconds
Started Jun 27 04:41:20 PM PDT 24
Finished Jun 27 04:41:23 PM PDT 24
Peak memory 203708 kb
Host smart-7b48a7d8-f9bb-49bc-86bd-d05d1e39ef8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222787294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.222787294
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3552577340
Short name T1069
Test name
Test status
Simulation time 13061807 ps
CPU time 0.74 seconds
Started Jun 27 04:41:23 PM PDT 24
Finished Jun 27 04:41:28 PM PDT 24
Peak memory 203696 kb
Host smart-e5abaca2-a878-42e7-8818-8afc940650ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552577340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3552577340
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2690367913
Short name T1105
Test name
Test status
Simulation time 29004396 ps
CPU time 0.71 seconds
Started Jun 27 04:41:21 PM PDT 24
Finished Jun 27 04:41:25 PM PDT 24
Peak memory 203788 kb
Host smart-f70123c6-b7d0-4698-b355-3a2557520c33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690367913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2690367913
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4222759762
Short name T1083
Test name
Test status
Simulation time 68201368 ps
CPU time 0.7 seconds
Started Jun 27 04:41:20 PM PDT 24
Finished Jun 27 04:41:22 PM PDT 24
Peak memory 203672 kb
Host smart-5c93001c-abe5-4c63-ade7-c61508e3fac5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222759762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
4222759762
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2517742382
Short name T1092
Test name
Test status
Simulation time 44360209 ps
CPU time 0.69 seconds
Started Jun 27 04:41:21 PM PDT 24
Finished Jun 27 04:41:25 PM PDT 24
Peak memory 203716 kb
Host smart-65b8ffb2-464e-4a79-9ccc-619f346b42ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517742382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2517742382
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1550066169
Short name T1058
Test name
Test status
Simulation time 59066642 ps
CPU time 0.76 seconds
Started Jun 27 04:41:20 PM PDT 24
Finished Jun 27 04:41:22 PM PDT 24
Peak memory 203652 kb
Host smart-866ef08c-53b3-4283-bd0e-6177e945eb28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550066169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1550066169
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.194146183
Short name T1026
Test name
Test status
Simulation time 48966953 ps
CPU time 0.69 seconds
Started Jun 27 04:41:22 PM PDT 24
Finished Jun 27 04:41:26 PM PDT 24
Peak memory 204052 kb
Host smart-17bfe6ee-3c33-4fa1-8fe9-9277e31ca011
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194146183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.194146183
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1203658418
Short name T1030
Test name
Test status
Simulation time 14582904 ps
CPU time 0.73 seconds
Started Jun 27 04:41:22 PM PDT 24
Finished Jun 27 04:41:26 PM PDT 24
Peak memory 203708 kb
Host smart-8624dcf6-a7cf-49d6-ba28-9c1c61761fed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203658418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1203658418
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2742259600
Short name T1041
Test name
Test status
Simulation time 23119578 ps
CPU time 0.68 seconds
Started Jun 27 04:41:24 PM PDT 24
Finished Jun 27 04:41:29 PM PDT 24
Peak memory 203904 kb
Host smart-f9d34402-a759-40b0-9a6e-942e85bbce30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742259600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2742259600
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2840521164
Short name T122
Test name
Test status
Simulation time 715344351 ps
CPU time 15.88 seconds
Started Jun 27 04:40:28 PM PDT 24
Finished Jun 27 04:40:45 PM PDT 24
Peak memory 215320 kb
Host smart-aa31f78c-6ba6-4e39-bb1d-fb9c308877dd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840521164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2840521164
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1427325913
Short name T1067
Test name
Test status
Simulation time 524468338 ps
CPU time 31.54 seconds
Started Jun 27 04:40:45 PM PDT 24
Finished Jun 27 04:41:18 PM PDT 24
Peak memory 206400 kb
Host smart-5ae2c278-9a73-42b5-8aed-7d2172a8e146
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427325913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1427325913
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1190957629
Short name T86
Test name
Test status
Simulation time 22551126 ps
CPU time 0.95 seconds
Started Jun 27 04:40:32 PM PDT 24
Finished Jun 27 04:40:36 PM PDT 24
Peak memory 206864 kb
Host smart-26e12cee-4961-4059-83d8-9f9ff9facd71
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190957629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1190957629
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1568042789
Short name T1149
Test name
Test status
Simulation time 234350869 ps
CPU time 1.68 seconds
Started Jun 27 04:40:31 PM PDT 24
Finished Jun 27 04:40:35 PM PDT 24
Peak memory 215404 kb
Host smart-9dee4550-5dbf-4cf9-8fe4-b82270a757f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568042789 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1568042789
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1161971182
Short name T1077
Test name
Test status
Simulation time 103166534 ps
CPU time 1.52 seconds
Started Jun 27 04:40:30 PM PDT 24
Finished Jun 27 04:40:34 PM PDT 24
Peak memory 207012 kb
Host smart-04376c5b-4450-42b3-b819-0b90c6e00b9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161971182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
161971182
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.328077984
Short name T1098
Test name
Test status
Simulation time 16549670 ps
CPU time 0.73 seconds
Started Jun 27 04:40:45 PM PDT 24
Finished Jun 27 04:40:47 PM PDT 24
Peak memory 203908 kb
Host smart-6bac7d01-536c-4bdb-9367-00568adff40a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328077984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.328077984
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.128205471
Short name T119
Test name
Test status
Simulation time 57831905 ps
CPU time 2.12 seconds
Started Jun 27 04:40:45 PM PDT 24
Finished Jun 27 04:40:48 PM PDT 24
Peak memory 214812 kb
Host smart-3dbfecce-8b53-43af-884e-d534fd239e17
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128205471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.128205471
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3761988074
Short name T1029
Test name
Test status
Simulation time 12312974 ps
CPU time 0.64 seconds
Started Jun 27 04:40:30 PM PDT 24
Finished Jun 27 04:40:34 PM PDT 24
Peak memory 203868 kb
Host smart-e149ffd5-a5ab-4af7-808d-8c78a2130b2b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761988074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3761988074
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1223546008
Short name T1114
Test name
Test status
Simulation time 215348934 ps
CPU time 2.94 seconds
Started Jun 27 04:40:34 PM PDT 24
Finished Jun 27 04:40:39 PM PDT 24
Peak memory 215164 kb
Host smart-68e3f0e6-8cc7-48d8-bde3-dfdd3e6c3c1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223546008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1223546008
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.850720483
Short name T104
Test name
Test status
Simulation time 802944601 ps
CPU time 4.76 seconds
Started Jun 27 04:40:43 PM PDT 24
Finished Jun 27 04:40:49 PM PDT 24
Peak memory 215388 kb
Host smart-a5edd19b-038a-4b98-8223-682a32d5a1a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850720483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.850720483
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2444266871
Short name T97
Test name
Test status
Simulation time 2212712495 ps
CPU time 13.55 seconds
Started Jun 27 04:40:45 PM PDT 24
Finished Jun 27 04:41:00 PM PDT 24
Peak memory 215580 kb
Host smart-8b469774-ab8e-487e-ba10-4e644e0fce6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444266871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2444266871
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.236958386
Short name T1127
Test name
Test status
Simulation time 14483632 ps
CPU time 0.79 seconds
Started Jun 27 04:41:23 PM PDT 24
Finished Jun 27 04:41:29 PM PDT 24
Peak memory 203620 kb
Host smart-2ed9ed5a-63f4-4e2f-b6f7-dcc768bf4733
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236958386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.236958386
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1038933726
Short name T1111
Test name
Test status
Simulation time 15245282 ps
CPU time 0.75 seconds
Started Jun 27 04:41:20 PM PDT 24
Finished Jun 27 04:41:23 PM PDT 24
Peak memory 203704 kb
Host smart-94304460-1671-4ed2-aed2-9f572b293f5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038933726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1038933726
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2575771066
Short name T1024
Test name
Test status
Simulation time 17571329 ps
CPU time 0.71 seconds
Started Jun 27 04:41:24 PM PDT 24
Finished Jun 27 04:41:29 PM PDT 24
Peak memory 203772 kb
Host smart-7ec02d5c-4632-4d72-9731-c5fce8e198ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575771066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2575771066
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1033152101
Short name T1148
Test name
Test status
Simulation time 16251250 ps
CPU time 0.73 seconds
Started Jun 27 04:41:20 PM PDT 24
Finished Jun 27 04:41:22 PM PDT 24
Peak memory 203688 kb
Host smart-82976d56-4370-4d4e-b66d-6e3bfc465e12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033152101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1033152101
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.461452038
Short name T1078
Test name
Test status
Simulation time 67534791 ps
CPU time 0.76 seconds
Started Jun 27 04:41:22 PM PDT 24
Finished Jun 27 04:41:26 PM PDT 24
Peak memory 203712 kb
Host smart-fcf0332b-0bbc-4449-8025-bb7114c7db77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461452038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.461452038
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1091527557
Short name T1086
Test name
Test status
Simulation time 18484042 ps
CPU time 0.74 seconds
Started Jun 27 04:41:21 PM PDT 24
Finished Jun 27 04:41:24 PM PDT 24
Peak memory 203780 kb
Host smart-854400ff-027c-46d6-9d1b-8ebe6377e220
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091527557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1091527557
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2900656918
Short name T1061
Test name
Test status
Simulation time 18173878 ps
CPU time 0.71 seconds
Started Jun 27 04:41:20 PM PDT 24
Finished Jun 27 04:41:22 PM PDT 24
Peak memory 203972 kb
Host smart-5d32f318-6667-4160-904e-911757e779bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900656918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2900656918
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3021031919
Short name T1108
Test name
Test status
Simulation time 40650591 ps
CPU time 0.75 seconds
Started Jun 27 04:41:22 PM PDT 24
Finished Jun 27 04:41:27 PM PDT 24
Peak memory 203676 kb
Host smart-0243c7ba-6b97-4cdf-983e-1cb26fc4966b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021031919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3021031919
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3771742557
Short name T1048
Test name
Test status
Simulation time 25418023 ps
CPU time 0.76 seconds
Started Jun 27 04:41:20 PM PDT 24
Finished Jun 27 04:41:22 PM PDT 24
Peak memory 204052 kb
Host smart-2b286a1c-4c01-46ae-af27-807082a63f13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771742557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3771742557
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1631941813
Short name T1038
Test name
Test status
Simulation time 11319268 ps
CPU time 0.72 seconds
Started Jun 27 04:41:22 PM PDT 24
Finished Jun 27 04:41:28 PM PDT 24
Peak memory 203972 kb
Host smart-86ce46cc-4136-4a46-8e5a-de5bbbd7a9b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631941813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1631941813
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4150855880
Short name T1134
Test name
Test status
Simulation time 56556513 ps
CPU time 3.42 seconds
Started Jun 27 04:40:40 PM PDT 24
Finished Jun 27 04:40:45 PM PDT 24
Peak memory 216844 kb
Host smart-e24dc3ec-389a-49b1-8437-8e89098599e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150855880 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.4150855880
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.4033481711
Short name T1100
Test name
Test status
Simulation time 263447004 ps
CPU time 1.93 seconds
Started Jun 27 04:40:40 PM PDT 24
Finished Jun 27 04:40:43 PM PDT 24
Peak memory 215224 kb
Host smart-d30ae1b8-0a0b-47f1-83e4-f405ac911134
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033481711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.4
033481711
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.60315670
Short name T1073
Test name
Test status
Simulation time 19508931 ps
CPU time 0.76 seconds
Started Jun 27 04:40:41 PM PDT 24
Finished Jun 27 04:40:43 PM PDT 24
Peak memory 203704 kb
Host smart-6a5f2774-2039-4693-99ed-b7449e2924e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60315670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.60315670
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1446367780
Short name T138
Test name
Test status
Simulation time 168410807 ps
CPU time 2.59 seconds
Started Jun 27 04:40:41 PM PDT 24
Finished Jun 27 04:40:46 PM PDT 24
Peak memory 215232 kb
Host smart-92250331-290d-4227-a09f-03fa92449aee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446367780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1446367780
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2978199476
Short name T1112
Test name
Test status
Simulation time 843879679 ps
CPU time 18.41 seconds
Started Jun 27 04:40:42 PM PDT 24
Finished Jun 27 04:41:02 PM PDT 24
Peak memory 215264 kb
Host smart-527b5548-af83-4e7d-991f-9126597b6e7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978199476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2978199476
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2023090636
Short name T1076
Test name
Test status
Simulation time 160579450 ps
CPU time 3.22 seconds
Started Jun 27 04:41:00 PM PDT 24
Finished Jun 27 04:41:05 PM PDT 24
Peak memory 217712 kb
Host smart-db22329c-618d-441a-bcb1-da9423114162
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023090636 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2023090636
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3731445336
Short name T1087
Test name
Test status
Simulation time 377665300 ps
CPU time 2.36 seconds
Started Jun 27 04:40:41 PM PDT 24
Finished Jun 27 04:40:45 PM PDT 24
Peak memory 215228 kb
Host smart-392e90b5-79cd-4b4d-a2d7-955632e93b86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731445336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
731445336
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3845482550
Short name T1043
Test name
Test status
Simulation time 41374657 ps
CPU time 0.7 seconds
Started Jun 27 04:40:40 PM PDT 24
Finished Jun 27 04:40:42 PM PDT 24
Peak memory 203956 kb
Host smart-58679506-0f8a-48a6-aec7-f98f1d9f9c13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845482550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
845482550
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3108467341
Short name T1117
Test name
Test status
Simulation time 3315143907 ps
CPU time 3.71 seconds
Started Jun 27 04:40:31 PM PDT 24
Finished Jun 27 04:40:38 PM PDT 24
Peak memory 215392 kb
Host smart-07f1fda8-ded9-4739-95e5-eb6758c66ece
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108467341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3108467341
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1850930727
Short name T1085
Test name
Test status
Simulation time 667247215 ps
CPU time 3.95 seconds
Started Jun 27 04:40:28 PM PDT 24
Finished Jun 27 04:40:34 PM PDT 24
Peak memory 216428 kb
Host smart-cd3611fe-0c08-49ba-9a4b-b5a9edeeff46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850930727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
850930727
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2601770724
Short name T96
Test name
Test status
Simulation time 568226947 ps
CPU time 16.65 seconds
Started Jun 27 04:40:42 PM PDT 24
Finished Jun 27 04:41:00 PM PDT 24
Peak memory 215296 kb
Host smart-3dba7343-11f5-4be9-bcbb-5210c97daa41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601770724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2601770724
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3100756540
Short name T109
Test name
Test status
Simulation time 135890084 ps
CPU time 3.5 seconds
Started Jun 27 04:40:57 PM PDT 24
Finished Jun 27 04:41:03 PM PDT 24
Peak memory 217784 kb
Host smart-a691904e-b69c-4992-a2d6-256fa16a70a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100756540 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3100756540
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.521945462
Short name T118
Test name
Test status
Simulation time 74982258 ps
CPU time 1.48 seconds
Started Jun 27 04:40:55 PM PDT 24
Finished Jun 27 04:41:00 PM PDT 24
Peak memory 215148 kb
Host smart-b1fed507-d206-4961-a458-bdfd62eb9a59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521945462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.521945462
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3475034268
Short name T1119
Test name
Test status
Simulation time 11240548 ps
CPU time 0.79 seconds
Started Jun 27 04:40:56 PM PDT 24
Finished Jun 27 04:40:59 PM PDT 24
Peak memory 203668 kb
Host smart-f2fa5bc4-1c12-4f8c-ace3-c7889c58e7ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475034268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
475034268
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2319011718
Short name T1044
Test name
Test status
Simulation time 236828464 ps
CPU time 3.94 seconds
Started Jun 27 04:40:55 PM PDT 24
Finished Jun 27 04:41:02 PM PDT 24
Peak memory 215296 kb
Host smart-731205d5-8ebb-4244-b840-42d468f0abe9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319011718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2319011718
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2392442217
Short name T1055
Test name
Test status
Simulation time 68463467 ps
CPU time 1.71 seconds
Started Jun 27 04:40:55 PM PDT 24
Finished Jun 27 04:40:59 PM PDT 24
Peak memory 215420 kb
Host smart-e743f543-0498-4712-9bab-cb768f54bf1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392442217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
392442217
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2415128044
Short name T165
Test name
Test status
Simulation time 567090285 ps
CPU time 14.94 seconds
Started Jun 27 04:40:52 PM PDT 24
Finished Jun 27 04:41:09 PM PDT 24
Peak memory 215212 kb
Host smart-4a46d581-6a82-4521-894a-89aeb270c6cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415128044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2415128044
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2943290400
Short name T1125
Test name
Test status
Simulation time 56858414 ps
CPU time 3.68 seconds
Started Jun 27 04:40:53 PM PDT 24
Finished Jun 27 04:40:58 PM PDT 24
Peak memory 217108 kb
Host smart-1657db0b-b297-446a-8b32-164940ed5974
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943290400 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2943290400
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3961271660
Short name T1141
Test name
Test status
Simulation time 346030513 ps
CPU time 2.21 seconds
Started Jun 27 04:40:57 PM PDT 24
Finished Jun 27 04:41:02 PM PDT 24
Peak memory 215336 kb
Host smart-a2a97b75-e295-496f-a2cb-615590d36074
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961271660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
961271660
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1457358220
Short name T1034
Test name
Test status
Simulation time 54009550 ps
CPU time 0.71 seconds
Started Jun 27 04:40:53 PM PDT 24
Finished Jun 27 04:40:55 PM PDT 24
Peak memory 203728 kb
Host smart-8efba2ce-8c55-48f2-aecf-eafd63000c12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457358220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
457358220
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2721555945
Short name T1059
Test name
Test status
Simulation time 798004559 ps
CPU time 2.82 seconds
Started Jun 27 04:40:51 PM PDT 24
Finished Jun 27 04:40:55 PM PDT 24
Peak memory 215268 kb
Host smart-c2e0bd1b-9215-4b09-962a-21814df28085
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721555945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2721555945
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.165963559
Short name T1068
Test name
Test status
Simulation time 120903166 ps
CPU time 3.21 seconds
Started Jun 27 04:40:55 PM PDT 24
Finished Jun 27 04:41:01 PM PDT 24
Peak memory 215480 kb
Host smart-3a2a528b-d8c2-482d-82af-36fccca37d8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165963559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.165963559
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2211030777
Short name T116
Test name
Test status
Simulation time 379428233 ps
CPU time 20.37 seconds
Started Jun 27 04:40:55 PM PDT 24
Finished Jun 27 04:41:18 PM PDT 24
Peak memory 215288 kb
Host smart-3d9d9a98-0cac-450f-b0d6-507726cf5af5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211030777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2211030777
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1968732313
Short name T1146
Test name
Test status
Simulation time 502443817 ps
CPU time 3.64 seconds
Started Jun 27 04:41:04 PM PDT 24
Finished Jun 27 04:41:08 PM PDT 24
Peak memory 217016 kb
Host smart-1c19f6a3-f96a-430a-8055-152ade77c08b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968732313 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1968732313
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1802181791
Short name T1132
Test name
Test status
Simulation time 99715378 ps
CPU time 1.81 seconds
Started Jun 27 04:40:52 PM PDT 24
Finished Jun 27 04:40:55 PM PDT 24
Peak memory 206916 kb
Host smart-00c5d3bf-0002-4d73-a8d6-6c936d89d5c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802181791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
802181791
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3348768605
Short name T1106
Test name
Test status
Simulation time 26351816 ps
CPU time 0.72 seconds
Started Jun 27 04:40:56 PM PDT 24
Finished Jun 27 04:41:00 PM PDT 24
Peak memory 203944 kb
Host smart-f2ec9e6d-9be5-4686-93df-97c4a111581c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348768605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
348768605
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4288426097
Short name T139
Test name
Test status
Simulation time 167414870 ps
CPU time 2.77 seconds
Started Jun 27 04:40:56 PM PDT 24
Finished Jun 27 04:41:02 PM PDT 24
Peak memory 215308 kb
Host smart-a2b3b438-24f9-41a9-b369-e3c8fe58c45d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288426097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.4288426097
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3731162901
Short name T1084
Test name
Test status
Simulation time 212046373 ps
CPU time 3.04 seconds
Started Jun 27 04:41:05 PM PDT 24
Finished Jun 27 04:41:09 PM PDT 24
Peak memory 215368 kb
Host smart-65e524a2-ff40-4fc1-880e-22da38635a91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731162901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
731162901
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3130512714
Short name T959
Test name
Test status
Simulation time 45167368 ps
CPU time 0.75 seconds
Started Jun 27 04:41:22 PM PDT 24
Finished Jun 27 04:41:26 PM PDT 24
Peak memory 205228 kb
Host smart-c56b3b0f-4d08-4226-b63c-914c1645688a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130512714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
130512714
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3503440135
Short name T582
Test name
Test status
Simulation time 2852671564 ps
CPU time 4.63 seconds
Started Jun 27 04:41:24 PM PDT 24
Finished Jun 27 04:41:34 PM PDT 24
Peak memory 232656 kb
Host smart-bb0a2d8c-fbff-43ed-822a-795e6cc70ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503440135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3503440135
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.932053957
Short name T855
Test name
Test status
Simulation time 31319919 ps
CPU time 0.78 seconds
Started Jun 27 04:41:21 PM PDT 24
Finished Jun 27 04:41:24 PM PDT 24
Peak memory 206388 kb
Host smart-72791de7-5d79-4e74-bf9f-0c0ee4e00994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932053957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.932053957
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.769562098
Short name T917
Test name
Test status
Simulation time 46734497923 ps
CPU time 419.6 seconds
Started Jun 27 04:41:24 PM PDT 24
Finished Jun 27 04:48:29 PM PDT 24
Peak memory 255860 kb
Host smart-3c7e419b-70c6-46ef-ba81-d5dcf705d286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769562098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
769562098
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1441636853
Short name T278
Test name
Test status
Simulation time 208305686 ps
CPU time 3.23 seconds
Started Jun 27 04:41:20 PM PDT 24
Finished Jun 27 04:41:26 PM PDT 24
Peak memory 224364 kb
Host smart-c1c1ec00-30d9-4b18-90fe-bd75a607cf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441636853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1441636853
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.1807394643
Short name T397
Test name
Test status
Simulation time 20478201 ps
CPU time 0.79 seconds
Started Jun 27 04:41:24 PM PDT 24
Finished Jun 27 04:41:30 PM PDT 24
Peak memory 215700 kb
Host smart-06a54247-3e5b-4292-a1f9-2d569f661666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807394643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.1807394643
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3327999388
Short name T729
Test name
Test status
Simulation time 3268144268 ps
CPU time 32.45 seconds
Started Jun 27 04:41:23 PM PDT 24
Finished Jun 27 04:42:00 PM PDT 24
Peak memory 224536 kb
Host smart-0ca0248b-29cd-4159-90aa-183522d3c8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327999388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3327999388
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.346606051
Short name T219
Test name
Test status
Simulation time 4727510624 ps
CPU time 38.9 seconds
Started Jun 27 04:41:20 PM PDT 24
Finished Jun 27 04:42:01 PM PDT 24
Peak memory 232708 kb
Host smart-30ea9315-c7f5-4d3f-b0d1-12869c637166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346606051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.346606051
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.1238978438
Short name T938
Test name
Test status
Simulation time 68530691 ps
CPU time 0.98 seconds
Started Jun 27 04:41:22 PM PDT 24
Finished Jun 27 04:41:27 PM PDT 24
Peak memory 217860 kb
Host smart-74a15eb1-35e5-495a-8588-0ec926a90192
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238978438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.1238978438
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3575873157
Short name T481
Test name
Test status
Simulation time 5108759243 ps
CPU time 8.74 seconds
Started Jun 27 04:41:24 PM PDT 24
Finished Jun 27 04:41:38 PM PDT 24
Peak memory 232620 kb
Host smart-c9a66b4d-7d1b-402e-abf6-36da99bf6fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575873157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3575873157
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.374036000
Short name T221
Test name
Test status
Simulation time 4990971070 ps
CPU time 9 seconds
Started Jun 27 04:41:24 PM PDT 24
Finished Jun 27 04:41:38 PM PDT 24
Peak memory 224492 kb
Host smart-ec72443e-1beb-4fb4-a132-29c803ac69c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374036000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.374036000
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1158235417
Short name T40
Test name
Test status
Simulation time 78320455 ps
CPU time 3.2 seconds
Started Jun 27 04:41:46 PM PDT 24
Finished Jun 27 04:41:56 PM PDT 24
Peak memory 219252 kb
Host smart-d6e871cf-d32f-4381-b64d-720a58b635c9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1158235417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1158235417
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1044042407
Short name T75
Test name
Test status
Simulation time 110798810 ps
CPU time 1.25 seconds
Started Jun 27 04:41:21 PM PDT 24
Finished Jun 27 04:41:26 PM PDT 24
Peak memory 236496 kb
Host smart-ac60ddcf-2f31-4f2f-9088-14338692523a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044042407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1044042407
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2889382908
Short name T248
Test name
Test status
Simulation time 50419374497 ps
CPU time 425.55 seconds
Started Jun 27 04:41:25 PM PDT 24
Finished Jun 27 04:48:35 PM PDT 24
Peak memory 272712 kb
Host smart-d7c26ba6-b73c-41d9-bf2a-90d4a437d4a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889382908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2889382908
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3973490657
Short name T501
Test name
Test status
Simulation time 2055183764 ps
CPU time 17.52 seconds
Started Jun 27 04:41:25 PM PDT 24
Finished Jun 27 04:41:47 PM PDT 24
Peak memory 216104 kb
Host smart-c743f346-7876-49bf-866b-9155cf19ba2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973490657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3973490657
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3725849600
Short name T29
Test name
Test status
Simulation time 2136397875 ps
CPU time 2.24 seconds
Started Jun 27 04:41:22 PM PDT 24
Finished Jun 27 04:41:28 PM PDT 24
Peak memory 207740 kb
Host smart-48da852a-b4cf-481e-a435-d2569c9f269a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725849600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3725849600
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2093952041
Short name T669
Test name
Test status
Simulation time 80931411 ps
CPU time 1.54 seconds
Started Jun 27 04:41:20 PM PDT 24
Finished Jun 27 04:41:23 PM PDT 24
Peak memory 215972 kb
Host smart-a5585c9b-1c71-4334-b808-5a01de66a4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093952041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2093952041
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1731696747
Short name T734
Test name
Test status
Simulation time 21739818 ps
CPU time 0.71 seconds
Started Jun 27 04:41:22 PM PDT 24
Finished Jun 27 04:41:26 PM PDT 24
Peak memory 205796 kb
Host smart-a6c64447-9897-40b8-8d1d-28a99f6bb635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731696747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1731696747
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.537794249
Short name T607
Test name
Test status
Simulation time 113210891 ps
CPU time 3.52 seconds
Started Jun 27 04:41:19 PM PDT 24
Finished Jun 27 04:41:24 PM PDT 24
Peak memory 240596 kb
Host smart-4b5ce140-f3ec-4e9f-b684-853334fae4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537794249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.537794249
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1945172351
Short name T859
Test name
Test status
Simulation time 111593424 ps
CPU time 0.72 seconds
Started Jun 27 04:41:25 PM PDT 24
Finished Jun 27 04:41:31 PM PDT 24
Peak memory 204700 kb
Host smart-4011873d-870f-43b5-bc98-c2c2a98f70d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945172351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
945172351
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.4021757665
Short name T980
Test name
Test status
Simulation time 140181327 ps
CPU time 2.03 seconds
Started Jun 27 04:41:23 PM PDT 24
Finished Jun 27 04:41:30 PM PDT 24
Peak memory 224628 kb
Host smart-187f8ca4-cf14-4f1a-898c-953972a65d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021757665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.4021757665
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2220950592
Short name T994
Test name
Test status
Simulation time 66688695 ps
CPU time 0.79 seconds
Started Jun 27 04:41:23 PM PDT 24
Finished Jun 27 04:41:28 PM PDT 24
Peak memory 206488 kb
Host smart-918dcf70-b8ec-4159-b73a-530d53c1a70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220950592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2220950592
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.964544167
Short name T516
Test name
Test status
Simulation time 394814291 ps
CPU time 11.27 seconds
Started Jun 27 04:41:22 PM PDT 24
Finished Jun 27 04:41:38 PM PDT 24
Peak memory 226832 kb
Host smart-f0c805cc-17d2-4c20-86c7-cf49495ab957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964544167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.964544167
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.867583852
Short name T66
Test name
Test status
Simulation time 1585232885 ps
CPU time 29.17 seconds
Started Jun 27 04:41:22 PM PDT 24
Finished Jun 27 04:41:56 PM PDT 24
Peak memory 252960 kb
Host smart-b46e4fd7-cd87-4019-8e54-4a9ccac6cbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867583852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.
867583852
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3613997234
Short name T982
Test name
Test status
Simulation time 216449083 ps
CPU time 5.12 seconds
Started Jun 27 04:41:22 PM PDT 24
Finished Jun 27 04:41:32 PM PDT 24
Peak memory 232520 kb
Host smart-9474a6e5-9f70-46da-a9c3-5175cd612ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613997234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3613997234
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3762146585
Short name T188
Test name
Test status
Simulation time 7730659215 ps
CPU time 63.66 seconds
Started Jun 27 04:41:21 PM PDT 24
Finished Jun 27 04:42:28 PM PDT 24
Peak memory 240564 kb
Host smart-65fb7ebe-cf53-4e4c-b5b7-2e1b7bdf90dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762146585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3762146585
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.34850271
Short name T771
Test name
Test status
Simulation time 165630521 ps
CPU time 1.08 seconds
Started Jun 27 04:41:23 PM PDT 24
Finished Jun 27 04:41:28 PM PDT 24
Peak memory 216624 kb
Host smart-95dd6cc3-0fa4-4040-ba38-67f50fda1d56
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34850271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.34850271
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3671294076
Short name T953
Test name
Test status
Simulation time 1024576578 ps
CPU time 8.58 seconds
Started Jun 27 04:41:22 PM PDT 24
Finished Jun 27 04:41:35 PM PDT 24
Peak memory 239940 kb
Host smart-38483a55-abb5-46ed-9649-7a419230a70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671294076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3671294076
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1325944061
Short name T521
Test name
Test status
Simulation time 1748083413 ps
CPU time 6.14 seconds
Started Jun 27 04:41:18 PM PDT 24
Finished Jun 27 04:41:25 PM PDT 24
Peak memory 232592 kb
Host smart-eb8a83e9-df22-4976-b933-b6e63a785d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325944061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1325944061
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2201698267
Short name T144
Test name
Test status
Simulation time 5941807147 ps
CPU time 11.25 seconds
Started Jun 27 04:41:22 PM PDT 24
Finished Jun 27 04:41:39 PM PDT 24
Peak memory 222964 kb
Host smart-48f38290-b543-4c2a-9958-a2d2370f137c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2201698267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2201698267
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.252773472
Short name T72
Test name
Test status
Simulation time 173386900 ps
CPU time 0.99 seconds
Started Jun 27 04:41:23 PM PDT 24
Finished Jun 27 04:41:29 PM PDT 24
Peak memory 235692 kb
Host smart-bb9489ad-f832-43e0-911b-5dff23989c31
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252773472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.252773472
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.231631793
Short name T978
Test name
Test status
Simulation time 36274545 ps
CPU time 0.97 seconds
Started Jun 27 04:41:24 PM PDT 24
Finished Jun 27 04:41:29 PM PDT 24
Peak memory 205204 kb
Host smart-9cc668d6-5643-491f-9eb3-f4a2a0ae8f0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231631793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.231631793
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2707396514
Short name T713
Test name
Test status
Simulation time 4150518607 ps
CPU time 17.2 seconds
Started Jun 27 04:41:22 PM PDT 24
Finished Jun 27 04:41:43 PM PDT 24
Peak memory 216252 kb
Host smart-e9724cea-ffef-4eb3-bca8-48e180d33c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707396514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2707396514
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3626982360
Short name T1003
Test name
Test status
Simulation time 1008467974 ps
CPU time 2.66 seconds
Started Jun 27 04:41:24 PM PDT 24
Finished Jun 27 04:41:32 PM PDT 24
Peak memory 216068 kb
Host smart-fc2e4dc8-b271-4ff9-a9eb-ae0d7d920062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626982360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3626982360
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.79768644
Short name T823
Test name
Test status
Simulation time 253828721 ps
CPU time 2.83 seconds
Started Jun 27 04:41:26 PM PDT 24
Finished Jun 27 04:41:33 PM PDT 24
Peak memory 216028 kb
Host smart-64bd53c8-c041-4bdb-94da-9282ca38f0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79768644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.79768644
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3679459289
Short name T438
Test name
Test status
Simulation time 15994479 ps
CPU time 0.68 seconds
Started Jun 27 04:41:21 PM PDT 24
Finished Jun 27 04:41:25 PM PDT 24
Peak memory 205496 kb
Host smart-8bb87353-80b2-49ea-a372-a233e614849b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679459289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3679459289
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1190314140
Short name T792
Test name
Test status
Simulation time 301364291 ps
CPU time 3.22 seconds
Started Jun 27 04:41:23 PM PDT 24
Finished Jun 27 04:41:31 PM PDT 24
Peak memory 224360 kb
Host smart-0eb867a9-4f2b-4b41-b97f-8664c3895470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190314140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1190314140
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2921734098
Short name T778
Test name
Test status
Simulation time 43957535 ps
CPU time 0.72 seconds
Started Jun 27 04:42:00 PM PDT 24
Finished Jun 27 04:42:06 PM PDT 24
Peak memory 205320 kb
Host smart-4f65dbf1-ac14-4e19-9c28-2e45bbcac5d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921734098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2921734098
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1260367288
Short name T698
Test name
Test status
Simulation time 1421766008 ps
CPU time 13.6 seconds
Started Jun 27 04:41:56 PM PDT 24
Finished Jun 27 04:42:13 PM PDT 24
Peak memory 232468 kb
Host smart-92f9ac3f-ef6b-4847-a0ac-26c0a73ba7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260367288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1260367288
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3305422521
Short name T666
Test name
Test status
Simulation time 32905626 ps
CPU time 0.79 seconds
Started Jun 27 04:41:47 PM PDT 24
Finished Jun 27 04:41:54 PM PDT 24
Peak memory 206420 kb
Host smart-d9b2a9c9-973c-4004-a55c-e805fa5c73be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305422521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3305422521
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2498866725
Short name T498
Test name
Test status
Simulation time 4822880493 ps
CPU time 31.26 seconds
Started Jun 27 04:41:58 PM PDT 24
Finished Jun 27 04:42:32 PM PDT 24
Peak memory 250048 kb
Host smart-66aa75a0-825e-4939-b90e-36695ca05f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498866725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2498866725
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1734670370
Short name T712
Test name
Test status
Simulation time 55424042955 ps
CPU time 98.81 seconds
Started Jun 27 04:41:58 PM PDT 24
Finished Jun 27 04:43:40 PM PDT 24
Peak memory 249168 kb
Host smart-6f630f20-0df4-4e8c-9e58-e48bd450a170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734670370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1734670370
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1878043146
Short name T696
Test name
Test status
Simulation time 14399350308 ps
CPU time 78.26 seconds
Started Jun 27 04:42:02 PM PDT 24
Finished Jun 27 04:43:25 PM PDT 24
Peak memory 249896 kb
Host smart-c43dd60e-4a5d-4504-a7a5-f79f1b0fd23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878043146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1878043146
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2693699717
Short name T595
Test name
Test status
Simulation time 1365330284 ps
CPU time 9.39 seconds
Started Jun 27 04:41:59 PM PDT 24
Finished Jun 27 04:42:13 PM PDT 24
Peak memory 224280 kb
Host smart-db87834f-142c-474e-9808-c11cacf95206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693699717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2693699717
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.2866516735
Short name T49
Test name
Test status
Simulation time 12547609874 ps
CPU time 81.77 seconds
Started Jun 27 04:41:57 PM PDT 24
Finished Jun 27 04:43:22 PM PDT 24
Peak memory 265336 kb
Host smart-a36b5e13-5ad8-4f07-a444-100f2d80ad65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866516735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.2866516735
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1398568000
Short name T795
Test name
Test status
Simulation time 2074489837 ps
CPU time 22.75 seconds
Started Jun 27 04:41:56 PM PDT 24
Finished Jun 27 04:42:22 PM PDT 24
Peak memory 232528 kb
Host smart-bbed094d-ca91-4f05-b090-a55a3cdf800b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398568000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1398568000
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1480595014
Short name T328
Test name
Test status
Simulation time 221909117 ps
CPU time 3.55 seconds
Started Jun 27 04:42:01 PM PDT 24
Finished Jun 27 04:42:10 PM PDT 24
Peak memory 232520 kb
Host smart-499accbb-d1d4-43bf-b251-5ba36041af93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480595014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1480595014
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1874088547
Short name T556
Test name
Test status
Simulation time 1349377802 ps
CPU time 7.72 seconds
Started Jun 27 04:41:56 PM PDT 24
Finished Jun 27 04:42:06 PM PDT 24
Peak memory 224296 kb
Host smart-46aeaf28-a8b1-46c0-9dfd-ba05adf56869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874088547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1874088547
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3417958416
Short name T885
Test name
Test status
Simulation time 1663224251 ps
CPU time 6.11 seconds
Started Jun 27 04:41:56 PM PDT 24
Finished Jun 27 04:42:06 PM PDT 24
Peak memory 232528 kb
Host smart-6e61d8d8-80f5-4f3b-96cb-49f9366ec47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417958416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3417958416
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2298658353
Short name T652
Test name
Test status
Simulation time 2418085679 ps
CPU time 9.23 seconds
Started Jun 27 04:41:57 PM PDT 24
Finished Jun 27 04:42:10 PM PDT 24
Peak memory 221956 kb
Host smart-3b47426e-2d2e-4014-b113-cbbbedcfaf07
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2298658353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2298658353
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.946881689
Short name T528
Test name
Test status
Simulation time 2438551034 ps
CPU time 6.77 seconds
Started Jun 27 04:42:03 PM PDT 24
Finished Jun 27 04:42:15 PM PDT 24
Peak memory 216520 kb
Host smart-e578a298-52aa-4a6d-9365-39ba1a2bea14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946881689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.946881689
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3635775403
Short name T750
Test name
Test status
Simulation time 31301841130 ps
CPU time 18.85 seconds
Started Jun 27 04:41:57 PM PDT 24
Finished Jun 27 04:42:19 PM PDT 24
Peak memory 217300 kb
Host smart-112333e9-bd45-48d6-a50d-1fc9ac7d733b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635775403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3635775403
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2215134428
Short name T949
Test name
Test status
Simulation time 124125143 ps
CPU time 1.34 seconds
Started Jun 27 04:41:59 PM PDT 24
Finished Jun 27 04:42:04 PM PDT 24
Peak memory 207884 kb
Host smart-5dcae2ca-3eee-402c-a188-f52cb7931f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215134428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2215134428
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3816288324
Short name T28
Test name
Test status
Simulation time 130082032 ps
CPU time 0.95 seconds
Started Jun 27 04:42:06 PM PDT 24
Finished Jun 27 04:42:11 PM PDT 24
Peak memory 205780 kb
Host smart-89e33c32-46e0-4bce-b063-0d7ad859fba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816288324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3816288324
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2813473051
Short name T637
Test name
Test status
Simulation time 288025891 ps
CPU time 2.75 seconds
Started Jun 27 04:41:58 PM PDT 24
Finished Jun 27 04:42:05 PM PDT 24
Peak memory 232548 kb
Host smart-5b4aa4ae-2e32-4c16-b692-4bd23791b3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813473051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2813473051
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.618365078
Short name T957
Test name
Test status
Simulation time 50814103 ps
CPU time 0.7 seconds
Started Jun 27 04:41:55 PM PDT 24
Finished Jun 27 04:41:58 PM PDT 24
Peak memory 205324 kb
Host smart-93d06871-a308-4c3f-9196-780e1d344b0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618365078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.618365078
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3295112841
Short name T916
Test name
Test status
Simulation time 672574994 ps
CPU time 2.57 seconds
Started Jun 27 04:41:57 PM PDT 24
Finished Jun 27 04:42:03 PM PDT 24
Peak memory 224344 kb
Host smart-3cf7c76c-a01f-4809-aed0-c5c1b1c4aa7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295112841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3295112841
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.65390682
Short name T781
Test name
Test status
Simulation time 147629224 ps
CPU time 0.73 seconds
Started Jun 27 04:41:56 PM PDT 24
Finished Jun 27 04:42:00 PM PDT 24
Peak memory 205392 kb
Host smart-df476e1a-cf7d-4d42-b201-a9a536185a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65390682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.65390682
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3904599613
Short name T700
Test name
Test status
Simulation time 6729853337 ps
CPU time 24.04 seconds
Started Jun 27 04:42:01 PM PDT 24
Finished Jun 27 04:42:31 PM PDT 24
Peak memory 238616 kb
Host smart-a797f165-7ffe-49d0-a121-3ab44f223797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904599613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3904599613
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1902539916
Short name T443
Test name
Test status
Simulation time 88477348852 ps
CPU time 86.62 seconds
Started Jun 27 04:41:57 PM PDT 24
Finished Jun 27 04:43:27 PM PDT 24
Peak memory 254120 kb
Host smart-b3b97ed1-e8f9-423e-a83b-a3a2deb521df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902539916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1902539916
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2532218096
Short name T779
Test name
Test status
Simulation time 193981818 ps
CPU time 9.89 seconds
Started Jun 27 04:41:58 PM PDT 24
Finished Jun 27 04:42:12 PM PDT 24
Peak memory 240780 kb
Host smart-19cde8de-6d10-4296-9665-a3deda082dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532218096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2532218096
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.330008045
Short name T200
Test name
Test status
Simulation time 2626998231 ps
CPU time 68.69 seconds
Started Jun 27 04:41:59 PM PDT 24
Finished Jun 27 04:43:12 PM PDT 24
Peak memory 263292 kb
Host smart-ed56a44e-2562-459b-bf33-6587f31e1a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330008045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds
.330008045
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1802342014
Short name T466
Test name
Test status
Simulation time 4151470710 ps
CPU time 32.07 seconds
Started Jun 27 04:41:59 PM PDT 24
Finished Jun 27 04:42:35 PM PDT 24
Peak memory 224400 kb
Host smart-d15ef062-f487-49d5-ba4d-776dfe532f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802342014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1802342014
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.823991050
Short name T593
Test name
Test status
Simulation time 62449931 ps
CPU time 2.65 seconds
Started Jun 27 04:42:03 PM PDT 24
Finished Jun 27 04:42:10 PM PDT 24
Peak memory 232332 kb
Host smart-833352c9-4472-46af-b2fc-7703f62d8b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823991050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.823991050
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.3256117761
Short name T339
Test name
Test status
Simulation time 167886543 ps
CPU time 1.08 seconds
Started Jun 27 04:41:58 PM PDT 24
Finished Jun 27 04:42:03 PM PDT 24
Peak memory 216636 kb
Host smart-d4c4bc97-be9f-4761-9f64-77a2c4e908eb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256117761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.3256117761
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.4117917370
Short name T903
Test name
Test status
Simulation time 210304295 ps
CPU time 4.26 seconds
Started Jun 27 04:41:57 PM PDT 24
Finished Jun 27 04:42:05 PM PDT 24
Peak memory 232508 kb
Host smart-5ab58ae3-d3cd-41a3-b733-6ceb86e74de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117917370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.4117917370
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2663447974
Short name T831
Test name
Test status
Simulation time 1249616314 ps
CPU time 6.16 seconds
Started Jun 27 04:41:55 PM PDT 24
Finished Jun 27 04:42:04 PM PDT 24
Peak memory 224340 kb
Host smart-8e0aaa29-339f-4587-bfa4-397001f3bb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663447974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2663447974
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.431812042
Short name T963
Test name
Test status
Simulation time 262194261 ps
CPU time 3.97 seconds
Started Jun 27 04:42:02 PM PDT 24
Finished Jun 27 04:42:11 PM PDT 24
Peak memory 222276 kb
Host smart-d8b9c880-166f-4bdf-9905-19a8b4fa3bfe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=431812042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.431812042
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1177918269
Short name T535
Test name
Test status
Simulation time 69679822016 ps
CPU time 147.45 seconds
Started Jun 27 04:41:58 PM PDT 24
Finished Jun 27 04:44:30 PM PDT 24
Peak memory 257348 kb
Host smart-ea68b0fb-e2f9-4c23-bedf-26435b6bd5da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177918269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1177918269
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1867952538
Short name T297
Test name
Test status
Simulation time 9495972956 ps
CPU time 11.22 seconds
Started Jun 27 04:41:57 PM PDT 24
Finished Jun 27 04:42:11 PM PDT 24
Peak memory 216192 kb
Host smart-429f0cc6-832d-4c2e-adf8-73e74481b36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867952538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1867952538
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.157542050
Short name T587
Test name
Test status
Simulation time 3648732118 ps
CPU time 8.74 seconds
Started Jun 27 04:41:56 PM PDT 24
Finished Jun 27 04:42:08 PM PDT 24
Peak memory 216176 kb
Host smart-a9d69354-0cbb-4880-997c-5289e15736e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157542050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.157542050
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.4082159757
Short name T488
Test name
Test status
Simulation time 54672165 ps
CPU time 1.43 seconds
Started Jun 27 04:41:56 PM PDT 24
Finished Jun 27 04:42:00 PM PDT 24
Peak memory 216012 kb
Host smart-4ba15080-1de7-4b5a-94ad-59724e659470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082159757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.4082159757
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3173821705
Short name T1012
Test name
Test status
Simulation time 437122500 ps
CPU time 0.96 seconds
Started Jun 27 04:42:01 PM PDT 24
Finished Jun 27 04:42:08 PM PDT 24
Peak memory 205736 kb
Host smart-259b69ec-9a7f-44b2-a277-141c5f59c6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173821705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3173821705
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2224599007
Short name T765
Test name
Test status
Simulation time 41603682669 ps
CPU time 12.54 seconds
Started Jun 27 04:41:58 PM PDT 24
Finished Jun 27 04:42:15 PM PDT 24
Peak memory 224524 kb
Host smart-af0f3f53-34df-4106-9e6f-48c0ae998495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224599007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2224599007
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1523561490
Short name T714
Test name
Test status
Simulation time 103856075 ps
CPU time 0.69 seconds
Started Jun 27 04:41:59 PM PDT 24
Finished Jun 27 04:42:04 PM PDT 24
Peak memory 204680 kb
Host smart-be26d02f-3da0-4ce8-a006-196de2c56220
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523561490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1523561490
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1026727888
Short name T220
Test name
Test status
Simulation time 172211099 ps
CPU time 4.33 seconds
Started Jun 27 04:41:58 PM PDT 24
Finished Jun 27 04:42:07 PM PDT 24
Peak memory 224360 kb
Host smart-72b3ef04-f248-4d09-85aa-66907300ebf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026727888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1026727888
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.4014322149
Short name T597
Test name
Test status
Simulation time 53360031 ps
CPU time 0.78 seconds
Started Jun 27 04:41:58 PM PDT 24
Finished Jun 27 04:42:02 PM PDT 24
Peak memory 205432 kb
Host smart-6ff00e87-0568-489b-aa51-cb6591985e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014322149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.4014322149
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3388105779
Short name T640
Test name
Test status
Simulation time 85154728838 ps
CPU time 130.99 seconds
Started Jun 27 04:42:00 PM PDT 24
Finished Jun 27 04:44:16 PM PDT 24
Peak memory 249000 kb
Host smart-7a9f3884-7f74-48e4-9e70-e42f6497b360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388105779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3388105779
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2637887885
Short name T727
Test name
Test status
Simulation time 2858147717 ps
CPU time 37.1 seconds
Started Jun 27 04:42:00 PM PDT 24
Finished Jun 27 04:42:42 PM PDT 24
Peak memory 239580 kb
Host smart-1558bc23-e11a-40b0-bc20-37a43ff880fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637887885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2637887885
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2066392100
Short name T137
Test name
Test status
Simulation time 208430429210 ps
CPU time 440.25 seconds
Started Jun 27 04:42:00 PM PDT 24
Finished Jun 27 04:49:26 PM PDT 24
Peak memory 254620 kb
Host smart-ab310c56-d814-4f41-bbaf-ca8550bed8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066392100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2066392100
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1204108511
Short name T899
Test name
Test status
Simulation time 2762834196 ps
CPU time 10.33 seconds
Started Jun 27 04:41:58 PM PDT 24
Finished Jun 27 04:42:13 PM PDT 24
Peak memory 224500 kb
Host smart-47a98ea7-256e-41b4-9a95-8bb8e8edd098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204108511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1204108511
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.538225268
Short name T496
Test name
Test status
Simulation time 884495142 ps
CPU time 18.59 seconds
Started Jun 27 04:42:06 PM PDT 24
Finished Jun 27 04:42:28 PM PDT 24
Peak memory 248912 kb
Host smart-015668f2-1519-4613-9758-92f74fa6b57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538225268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds
.538225268
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.693461796
Short name T559
Test name
Test status
Simulation time 1988066723 ps
CPU time 7.46 seconds
Started Jun 27 04:41:55 PM PDT 24
Finished Jun 27 04:42:04 PM PDT 24
Peak memory 232480 kb
Host smart-cc1fda9f-dec1-40cf-bde8-cb7374da9adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693461796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.693461796
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2694874920
Short name T490
Test name
Test status
Simulation time 566990695 ps
CPU time 12.24 seconds
Started Jun 27 04:42:01 PM PDT 24
Finished Jun 27 04:42:19 PM PDT 24
Peak memory 250312 kb
Host smart-7e476cc7-4ccc-46eb-8c42-ebdfa42c385e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694874920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2694874920
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.281718787
Short name T305
Test name
Test status
Simulation time 41208974 ps
CPU time 1.04 seconds
Started Jun 27 04:41:59 PM PDT 24
Finished Jun 27 04:42:05 PM PDT 24
Peak memory 216596 kb
Host smart-997e0a20-e658-4e29-b778-3ab7c5698c47
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281718787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.spi_device_mem_parity.281718787
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3274055767
Short name T837
Test name
Test status
Simulation time 275943546 ps
CPU time 2.92 seconds
Started Jun 27 04:42:00 PM PDT 24
Finished Jun 27 04:42:08 PM PDT 24
Peak memory 224356 kb
Host smart-50324fa3-4ef4-4213-bd07-8b011cfeb325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274055767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3274055767
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3374853548
Short name T710
Test name
Test status
Simulation time 8216719766 ps
CPU time 17.84 seconds
Started Jun 27 04:41:57 PM PDT 24
Finished Jun 27 04:42:18 PM PDT 24
Peak memory 224460 kb
Host smart-186b236a-7c1f-4715-9d43-e97865c70e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374853548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3374853548
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1100283874
Short name T841
Test name
Test status
Simulation time 377331406 ps
CPU time 5.29 seconds
Started Jun 27 04:41:58 PM PDT 24
Finished Jun 27 04:42:07 PM PDT 24
Peak memory 222212 kb
Host smart-e8c1ddea-1930-46f6-a517-550bf8ca60e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1100283874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1100283874
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.231091930
Short name T843
Test name
Test status
Simulation time 50443537535 ps
CPU time 449.92 seconds
Started Jun 27 04:42:03 PM PDT 24
Finished Jun 27 04:49:38 PM PDT 24
Peak memory 273028 kb
Host smart-e2df6a86-e7c4-47c6-8d27-894c3dff7976
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231091930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.231091930
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3292887977
Short name T22
Test name
Test status
Simulation time 648140758 ps
CPU time 3.06 seconds
Started Jun 27 04:41:59 PM PDT 24
Finished Jun 27 04:42:06 PM PDT 24
Peak memory 216048 kb
Host smart-24e5e331-ed4e-4ef8-a888-1d00dcb1d045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292887977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3292887977
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.4003952127
Short name T654
Test name
Test status
Simulation time 918369510 ps
CPU time 2.26 seconds
Started Jun 27 04:42:00 PM PDT 24
Finished Jun 27 04:42:07 PM PDT 24
Peak memory 215892 kb
Host smart-31d76717-12f4-4c8a-a920-bb80cf0ca142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003952127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.4003952127
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.4169783664
Short name T429
Test name
Test status
Simulation time 520866949 ps
CPU time 1.96 seconds
Started Jun 27 04:41:58 PM PDT 24
Finished Jun 27 04:42:05 PM PDT 24
Peak memory 216152 kb
Host smart-4fd7b81d-34ce-4123-833a-9ae64d69b393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169783664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.4169783664
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.230751625
Short name T667
Test name
Test status
Simulation time 151089322 ps
CPU time 0.9 seconds
Started Jun 27 04:41:58 PM PDT 24
Finished Jun 27 04:42:03 PM PDT 24
Peak memory 205748 kb
Host smart-6d21707e-ad8d-47d8-bdbb-914e3566fcbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230751625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.230751625
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.794004986
Short name T515
Test name
Test status
Simulation time 12840854880 ps
CPU time 43.23 seconds
Started Jun 27 04:42:00 PM PDT 24
Finished Jun 27 04:42:49 PM PDT 24
Peak memory 233700 kb
Host smart-bde67c77-32f9-40c0-be84-26709e7ff14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794004986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.794004986
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1294682363
Short name T411
Test name
Test status
Simulation time 108813378 ps
CPU time 0.71 seconds
Started Jun 27 04:42:11 PM PDT 24
Finished Jun 27 04:42:14 PM PDT 24
Peak memory 205200 kb
Host smart-b21e5c2d-e123-4d07-9c38-1ed0b3362937
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294682363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1294682363
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.690734628
Short name T651
Test name
Test status
Simulation time 124018768 ps
CPU time 3.76 seconds
Started Jun 27 04:42:03 PM PDT 24
Finished Jun 27 04:42:12 PM PDT 24
Peak memory 232496 kb
Host smart-207315f9-5586-4249-a935-bd3e1f37b08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690734628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.690734628
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3090983337
Short name T381
Test name
Test status
Simulation time 17313697 ps
CPU time 0.76 seconds
Started Jun 27 04:42:01 PM PDT 24
Finished Jun 27 04:42:06 PM PDT 24
Peak memory 205476 kb
Host smart-3104d09e-8c05-4867-9eac-2a7076f04378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090983337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3090983337
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2773583441
Short name T623
Test name
Test status
Simulation time 887404799 ps
CPU time 12.14 seconds
Started Jun 27 04:42:15 PM PDT 24
Finished Jun 27 04:42:31 PM PDT 24
Peak memory 224364 kb
Host smart-f06b9cd2-3e7b-49bf-8f9f-e2c9428978fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773583441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2773583441
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1166754039
Short name T617
Test name
Test status
Simulation time 44706359398 ps
CPU time 105.71 seconds
Started Jun 27 04:42:11 PM PDT 24
Finished Jun 27 04:43:59 PM PDT 24
Peak memory 240300 kb
Host smart-bcae0646-6bc4-4790-b574-c79090e693eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166754039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1166754039
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3884271466
Short name T275
Test name
Test status
Simulation time 202870087 ps
CPU time 5.45 seconds
Started Jun 27 04:42:10 PM PDT 24
Finished Jun 27 04:42:18 PM PDT 24
Peak memory 232396 kb
Host smart-a6dbcaf5-1b6f-4f74-80b6-551a1585bcf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884271466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3884271466
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3233796495
Short name T861
Test name
Test status
Simulation time 12876064158 ps
CPU time 12.04 seconds
Started Jun 27 04:42:04 PM PDT 24
Finished Jun 27 04:42:21 PM PDT 24
Peak memory 224480 kb
Host smart-175b230b-266c-412b-9c5c-9de02076349d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233796495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3233796495
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3409431625
Short name T590
Test name
Test status
Simulation time 38909457755 ps
CPU time 39.82 seconds
Started Jun 27 04:42:15 PM PDT 24
Finished Jun 27 04:42:59 PM PDT 24
Peak memory 224420 kb
Host smart-fef9cb88-5d01-4987-8679-228e9512bf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409431625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3409431625
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3246446552
Short name T395
Test name
Test status
Simulation time 25254145 ps
CPU time 1.03 seconds
Started Jun 27 04:42:01 PM PDT 24
Finished Jun 27 04:42:07 PM PDT 24
Peak memory 216756 kb
Host smart-8689883a-151d-4bea-9b1a-5d77563d565c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246446552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3246446552
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3596421330
Short name T253
Test name
Test status
Simulation time 2926887009 ps
CPU time 10.53 seconds
Started Jun 27 04:42:04 PM PDT 24
Finished Jun 27 04:42:19 PM PDT 24
Peak memory 232608 kb
Host smart-87b0cf98-3d1a-4197-b7b3-1c27f0e4fa59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596421330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3596421330
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2127508991
Short name T463
Test name
Test status
Simulation time 3625541347 ps
CPU time 5.27 seconds
Started Jun 27 04:42:07 PM PDT 24
Finished Jun 27 04:42:16 PM PDT 24
Peak memory 224484 kb
Host smart-1dd33690-b336-4c17-954a-508a1a25f79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127508991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2127508991
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.600766541
Short name T790
Test name
Test status
Simulation time 230617054 ps
CPU time 5.01 seconds
Started Jun 27 04:42:15 PM PDT 24
Finished Jun 27 04:42:24 PM PDT 24
Peak memory 222392 kb
Host smart-5dc4d30a-4f78-468f-8378-c6ef2cfe9661
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=600766541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.600766541
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1259640596
Short name T151
Test name
Test status
Simulation time 1212078430 ps
CPU time 1.09 seconds
Started Jun 27 04:42:11 PM PDT 24
Finished Jun 27 04:42:14 PM PDT 24
Peak memory 207564 kb
Host smart-58cd6970-8d59-4717-8abb-99943496f399
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259640596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1259640596
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.4232581569
Short name T293
Test name
Test status
Simulation time 1140021511 ps
CPU time 16.88 seconds
Started Jun 27 04:42:00 PM PDT 24
Finished Jun 27 04:42:22 PM PDT 24
Peak memory 216516 kb
Host smart-dbc0ba12-87b8-45e0-81e7-12a9634d330e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232581569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.4232581569
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1244401898
Short name T509
Test name
Test status
Simulation time 35262844419 ps
CPU time 22.48 seconds
Started Jun 27 04:42:04 PM PDT 24
Finished Jun 27 04:42:32 PM PDT 24
Peak memory 216228 kb
Host smart-6801eb3d-3dbe-4173-b0a9-2fc1f9dc4abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244401898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1244401898
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3480848141
Short name T830
Test name
Test status
Simulation time 13512874 ps
CPU time 0.79 seconds
Started Jun 27 04:41:57 PM PDT 24
Finished Jun 27 04:42:01 PM PDT 24
Peak memory 206080 kb
Host smart-0ba4795d-41c7-487c-9a71-521ab8c9f92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480848141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3480848141
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3022159552
Short name T752
Test name
Test status
Simulation time 37779235 ps
CPU time 0.74 seconds
Started Jun 27 04:41:58 PM PDT 24
Finished Jun 27 04:42:03 PM PDT 24
Peak memory 205804 kb
Host smart-38b368e8-7641-41e7-aa22-4d044c56e1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022159552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3022159552
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3952533836
Short name T127
Test name
Test status
Simulation time 16675034059 ps
CPU time 17.8 seconds
Started Jun 27 04:42:00 PM PDT 24
Finished Jun 27 04:42:22 PM PDT 24
Peak memory 232552 kb
Host smart-f01ff271-5e5a-4e52-b18d-3ab4f15439fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952533836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3952533836
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3568706523
Short name T848
Test name
Test status
Simulation time 30402577 ps
CPU time 2.31 seconds
Started Jun 27 04:42:13 PM PDT 24
Finished Jun 27 04:42:20 PM PDT 24
Peak memory 232244 kb
Host smart-483ed657-a11c-45cc-8eec-24d55a1660c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568706523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3568706523
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.492535394
Short name T809
Test name
Test status
Simulation time 14413098 ps
CPU time 0.74 seconds
Started Jun 27 04:42:10 PM PDT 24
Finished Jun 27 04:42:13 PM PDT 24
Peak memory 206356 kb
Host smart-769b256f-37e6-4cfc-b742-c0039daa818e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492535394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.492535394
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2680776847
Short name T196
Test name
Test status
Simulation time 74352567328 ps
CPU time 177.91 seconds
Started Jun 27 04:42:14 PM PDT 24
Finished Jun 27 04:45:16 PM PDT 24
Peak memory 265052 kb
Host smart-45e69b85-d40e-43de-a0ab-0e60a2aed474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680776847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2680776847
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.4082651596
Short name T988
Test name
Test status
Simulation time 11373973408 ps
CPU time 130.9 seconds
Started Jun 27 04:42:12 PM PDT 24
Finished Jun 27 04:44:27 PM PDT 24
Peak memory 257312 kb
Host smart-af973bdb-6b7d-43a0-bdf8-32e6f16a1df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082651596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.4082651596
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.78232652
Short name T3
Test name
Test status
Simulation time 8301990441 ps
CPU time 46.68 seconds
Started Jun 27 04:42:14 PM PDT 24
Finished Jun 27 04:43:05 PM PDT 24
Peak memory 221808 kb
Host smart-86be06e3-49f8-434c-90bd-785a127b7324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78232652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle.78232652
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3835848145
Short name T269
Test name
Test status
Simulation time 2874110364 ps
CPU time 12.21 seconds
Started Jun 27 04:42:12 PM PDT 24
Finished Jun 27 04:42:29 PM PDT 24
Peak memory 235076 kb
Host smart-e84a7826-a10f-4181-a09a-4785bf381759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835848145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3835848145
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.966262841
Short name T524
Test name
Test status
Simulation time 6248172765 ps
CPU time 21.6 seconds
Started Jun 27 04:42:04 PM PDT 24
Finished Jun 27 04:42:31 PM PDT 24
Peak memory 234016 kb
Host smart-e513b009-e10e-4119-8500-ffe613848dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966262841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds
.966262841
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3951968994
Short name T492
Test name
Test status
Simulation time 1155683307 ps
CPU time 4.12 seconds
Started Jun 27 04:42:13 PM PDT 24
Finished Jun 27 04:42:22 PM PDT 24
Peak memory 224288 kb
Host smart-b806cb02-5e75-4b56-96b2-3c3c74b8d70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951968994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3951968994
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3191620173
Short name T195
Test name
Test status
Simulation time 647897024 ps
CPU time 5.83 seconds
Started Jun 27 04:42:14 PM PDT 24
Finished Jun 27 04:42:24 PM PDT 24
Peak memory 238320 kb
Host smart-489eacd7-70be-4bf3-9937-e0881582269e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191620173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3191620173
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.534226372
Short name T34
Test name
Test status
Simulation time 93657987 ps
CPU time 0.97 seconds
Started Jun 27 04:42:13 PM PDT 24
Finished Jun 27 04:42:19 PM PDT 24
Peak memory 217908 kb
Host smart-7169ba77-5196-4bd9-ba4c-a0741e1ca64c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534226372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.534226372
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3680568628
Short name T921
Test name
Test status
Simulation time 2519910343 ps
CPU time 9.43 seconds
Started Jun 27 04:42:13 PM PDT 24
Finished Jun 27 04:42:26 PM PDT 24
Peak memory 224360 kb
Host smart-5c560f33-142a-4326-8d50-3cf79f9ed4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680568628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3680568628
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3541502061
Short name T223
Test name
Test status
Simulation time 18646946198 ps
CPU time 14.57 seconds
Started Jun 27 04:42:13 PM PDT 24
Finished Jun 27 04:42:32 PM PDT 24
Peak memory 224424 kb
Host smart-f65ff6a0-53aa-4597-8f6b-e008227fd6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541502061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3541502061
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1170508837
Short name T604
Test name
Test status
Simulation time 1225718522 ps
CPU time 8.38 seconds
Started Jun 27 04:42:12 PM PDT 24
Finished Jun 27 04:42:24 PM PDT 24
Peak memory 220732 kb
Host smart-dd5bfdbe-ce40-4314-a202-2a500476fca4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1170508837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1170508837
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.693677732
Short name T16
Test name
Test status
Simulation time 273572151 ps
CPU time 1.03 seconds
Started Jun 27 04:42:01 PM PDT 24
Finished Jun 27 04:42:08 PM PDT 24
Peak memory 206832 kb
Host smart-7db3e101-01fb-4677-bd1b-f7ed6d65c4f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693677732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.693677732
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3317166028
Short name T128
Test name
Test status
Simulation time 356113141 ps
CPU time 6.41 seconds
Started Jun 27 04:42:06 PM PDT 24
Finished Jun 27 04:42:17 PM PDT 24
Peak memory 216396 kb
Host smart-5bba3ef1-dafe-488e-a931-52ae3bda18d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317166028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3317166028
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2517804966
Short name T497
Test name
Test status
Simulation time 32440505994 ps
CPU time 8.31 seconds
Started Jun 27 04:42:13 PM PDT 24
Finished Jun 27 04:42:25 PM PDT 24
Peak memory 216148 kb
Host smart-b2583c90-0a54-413f-bb83-2679256625f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517804966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2517804966
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3035887367
Short name T808
Test name
Test status
Simulation time 18348980 ps
CPU time 1.02 seconds
Started Jun 27 04:42:13 PM PDT 24
Finished Jun 27 04:42:18 PM PDT 24
Peak memory 207752 kb
Host smart-6c84ebff-46c1-470e-a69e-258d292de665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035887367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3035887367
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3646397479
Short name T802
Test name
Test status
Simulation time 145728650 ps
CPU time 0.91 seconds
Started Jun 27 04:42:13 PM PDT 24
Finished Jun 27 04:42:18 PM PDT 24
Peak memory 205748 kb
Host smart-da8ad7e6-79ae-4266-b45f-0c0138cb8475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646397479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3646397479
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2273946754
Short name T383
Test name
Test status
Simulation time 906456509 ps
CPU time 5.57 seconds
Started Jun 27 04:41:58 PM PDT 24
Finished Jun 27 04:42:08 PM PDT 24
Peak memory 224364 kb
Host smart-78191eed-2547-42e5-9da0-955bd47e62b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273946754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2273946754
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.484159665
Short name T337
Test name
Test status
Simulation time 14172440 ps
CPU time 0.7 seconds
Started Jun 27 04:42:15 PM PDT 24
Finished Jun 27 04:42:20 PM PDT 24
Peak memory 205628 kb
Host smart-9fd4f914-fb5e-4465-ac72-b5b3a43e5613
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484159665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.484159665
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.4051137605
Short name T737
Test name
Test status
Simulation time 2948438604 ps
CPU time 9.18 seconds
Started Jun 27 04:41:58 PM PDT 24
Finished Jun 27 04:42:12 PM PDT 24
Peak memory 232728 kb
Host smart-c17d4012-1f37-435f-805a-3d29c83a0904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051137605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.4051137605
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2250098638
Short name T970
Test name
Test status
Simulation time 40412623 ps
CPU time 0.73 seconds
Started Jun 27 04:42:04 PM PDT 24
Finished Jun 27 04:42:10 PM PDT 24
Peak memory 205392 kb
Host smart-f651238a-9520-4320-b1f1-bb5bcfd0e8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250098638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2250098638
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.13981999
Short name T417
Test name
Test status
Simulation time 2789551811 ps
CPU time 17.42 seconds
Started Jun 27 04:42:04 PM PDT 24
Finished Jun 27 04:42:26 PM PDT 24
Peak memory 239532 kb
Host smart-1d287801-f463-477a-8978-2aa9bcbd7c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13981999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.13981999
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.886990631
Short name T900
Test name
Test status
Simulation time 359719080 ps
CPU time 2.78 seconds
Started Jun 27 04:42:02 PM PDT 24
Finished Jun 27 04:42:09 PM PDT 24
Peak memory 219360 kb
Host smart-15ddd33b-ea3f-4fb9-9c50-39aeab531921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886990631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.886990631
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2021896812
Short name T948
Test name
Test status
Simulation time 5334371999 ps
CPU time 30.39 seconds
Started Jun 27 04:43:00 PM PDT 24
Finished Jun 27 04:43:33 PM PDT 24
Peak memory 232656 kb
Host smart-4a438f32-33d3-4c6e-a4ab-91a37f5b9070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021896812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2021896812
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.3369125020
Short name T158
Test name
Test status
Simulation time 149033093374 ps
CPU time 526.14 seconds
Started Jun 27 04:42:04 PM PDT 24
Finished Jun 27 04:50:55 PM PDT 24
Peak memory 255852 kb
Host smart-267589ff-888e-4fdf-9dfb-9dfb3a9fd0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369125020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.3369125020
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2434062389
Short name T391
Test name
Test status
Simulation time 255329460 ps
CPU time 3.68 seconds
Started Jun 27 04:42:02 PM PDT 24
Finished Jun 27 04:42:10 PM PDT 24
Peak memory 224124 kb
Host smart-d1ffcb7f-73cf-4a00-bad3-65b05cb62c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434062389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2434062389
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2852488061
Short name T408
Test name
Test status
Simulation time 173244602302 ps
CPU time 104.08 seconds
Started Jun 27 04:41:59 PM PDT 24
Finished Jun 27 04:43:48 PM PDT 24
Peak memory 234504 kb
Host smart-7f28a943-fe3b-49da-b2aa-f1e2bb542a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852488061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2852488061
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.133337626
Short name T342
Test name
Test status
Simulation time 189734935 ps
CPU time 1.16 seconds
Started Jun 27 04:42:02 PM PDT 24
Finished Jun 27 04:42:08 PM PDT 24
Peak memory 216696 kb
Host smart-87644f68-3293-4b57-a9ac-febd0f616981
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133337626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.spi_device_mem_parity.133337626
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.337831586
Short name T800
Test name
Test status
Simulation time 1592248751 ps
CPU time 4.98 seconds
Started Jun 27 04:42:02 PM PDT 24
Finished Jun 27 04:42:12 PM PDT 24
Peak memory 232584 kb
Host smart-c3b2187b-4d49-4673-a21a-025c457b1321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337831586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.337831586
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1770798491
Short name T926
Test name
Test status
Simulation time 892731023 ps
CPU time 4.23 seconds
Started Jun 27 04:42:03 PM PDT 24
Finished Jun 27 04:42:12 PM PDT 24
Peak memory 224356 kb
Host smart-ddf6e090-2eba-4101-b75f-865828e84cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770798491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1770798491
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2040957654
Short name T688
Test name
Test status
Simulation time 4361355021 ps
CPU time 4.81 seconds
Started Jun 27 04:42:08 PM PDT 24
Finished Jun 27 04:42:16 PM PDT 24
Peak memory 220028 kb
Host smart-555f8562-26c0-4f95-99c3-3d9dc176f0ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2040957654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2040957654
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1810225020
Short name T19
Test name
Test status
Simulation time 138451009514 ps
CPU time 328.94 seconds
Started Jun 27 04:42:15 PM PDT 24
Finished Jun 27 04:47:48 PM PDT 24
Peak memory 265460 kb
Host smart-57b03c43-2975-4a2e-891f-744281933b58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810225020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1810225020
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2054580167
Short name T282
Test name
Test status
Simulation time 15088464176 ps
CPU time 25.38 seconds
Started Jun 27 04:42:03 PM PDT 24
Finished Jun 27 04:42:34 PM PDT 24
Peak memory 216244 kb
Host smart-2bd9c2f6-1af8-46a3-845c-43a35518ab2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054580167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2054580167
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1674344740
Short name T506
Test name
Test status
Simulation time 218031701 ps
CPU time 1.54 seconds
Started Jun 27 04:42:07 PM PDT 24
Finished Jun 27 04:42:12 PM PDT 24
Peak memory 216120 kb
Host smart-b906d750-9111-4586-a505-8ba6aa9982df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674344740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1674344740
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.361937575
Short name T550
Test name
Test status
Simulation time 158384873 ps
CPU time 0.81 seconds
Started Jun 27 04:42:08 PM PDT 24
Finished Jun 27 04:42:12 PM PDT 24
Peak memory 205796 kb
Host smart-6a014244-ba69-444a-af3c-4a70762d9955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361937575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.361937575
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2486565680
Short name T238
Test name
Test status
Simulation time 598262380 ps
CPU time 3.71 seconds
Started Jun 27 04:42:04 PM PDT 24
Finished Jun 27 04:42:13 PM PDT 24
Peak memory 232584 kb
Host smart-dfbced31-af55-48a1-82b2-e1eb8f50979e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486565680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2486565680
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.4280781767
Short name T987
Test name
Test status
Simulation time 16391889 ps
CPU time 0.69 seconds
Started Jun 27 04:42:12 PM PDT 24
Finished Jun 27 04:42:17 PM PDT 24
Peak memory 204700 kb
Host smart-e7657cc0-2de0-45e6-a385-2ffb7076685b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280781767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
4280781767
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3126150050
Short name T242
Test name
Test status
Simulation time 1525369620 ps
CPU time 13.39 seconds
Started Jun 27 04:42:12 PM PDT 24
Finished Jun 27 04:42:29 PM PDT 24
Peak memory 232544 kb
Host smart-d482e2cc-6cb0-4afc-b325-499ad58fc550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126150050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3126150050
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2965294485
Short name T510
Test name
Test status
Simulation time 30868310 ps
CPU time 0.87 seconds
Started Jun 27 04:42:15 PM PDT 24
Finished Jun 27 04:42:21 PM PDT 24
Peak memory 206740 kb
Host smart-5aaec361-59c3-4873-b71b-df574fdbda27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965294485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2965294485
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1619136255
Short name T812
Test name
Test status
Simulation time 213962220 ps
CPU time 0.94 seconds
Started Jun 27 04:42:13 PM PDT 24
Finished Jun 27 04:42:18 PM PDT 24
Peak memory 215888 kb
Host smart-8dd64b15-b565-4959-b69c-d8c590e8f239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619136255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1619136255
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3110093990
Short name T780
Test name
Test status
Simulation time 11129742410 ps
CPU time 83.74 seconds
Started Jun 27 04:42:13 PM PDT 24
Finished Jun 27 04:43:42 PM PDT 24
Peak memory 224248 kb
Host smart-1fef43bc-458e-47eb-a448-83a7b36d740a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110093990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3110093990
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.249242211
Short name T906
Test name
Test status
Simulation time 57758518779 ps
CPU time 303.99 seconds
Started Jun 27 04:42:13 PM PDT 24
Finished Jun 27 04:47:21 PM PDT 24
Peak memory 239936 kb
Host smart-4c4bb235-5421-4af2-9178-7ecd7d09854b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249242211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.249242211
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3860881434
Short name T815
Test name
Test status
Simulation time 462434579 ps
CPU time 6.62 seconds
Started Jun 27 04:42:14 PM PDT 24
Finished Jun 27 04:42:25 PM PDT 24
Peak memory 232480 kb
Host smart-4811af96-e67f-4a24-b904-aecfaf38e01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860881434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3860881434
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2948263425
Short name T918
Test name
Test status
Simulation time 23459467642 ps
CPU time 176.69 seconds
Started Jun 27 04:42:12 PM PDT 24
Finished Jun 27 04:45:12 PM PDT 24
Peak memory 251264 kb
Host smart-4854f0a1-a28a-4ce2-8664-4feb5b64a85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948263425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2948263425
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1276787357
Short name T334
Test name
Test status
Simulation time 949736171 ps
CPU time 9.09 seconds
Started Jun 27 04:42:11 PM PDT 24
Finished Jun 27 04:42:24 PM PDT 24
Peak memory 224248 kb
Host smart-a63fbb3b-625c-468f-b956-e92fd74255eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276787357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1276787357
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.424957851
Short name T325
Test name
Test status
Simulation time 3470257544 ps
CPU time 33.44 seconds
Started Jun 27 04:42:10 PM PDT 24
Finished Jun 27 04:42:46 PM PDT 24
Peak memory 232424 kb
Host smart-ac7c3f0b-fb10-4ba8-a046-09659cfbd482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424957851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.424957851
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.946019712
Short name T301
Test name
Test status
Simulation time 31925935 ps
CPU time 1.06 seconds
Started Jun 27 04:42:11 PM PDT 24
Finished Jun 27 04:42:15 PM PDT 24
Peak memory 217900 kb
Host smart-fff218c9-8584-48b3-9184-cb00568935b6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946019712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.946019712
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.948516765
Short name T818
Test name
Test status
Simulation time 1083250161 ps
CPU time 7.61 seconds
Started Jun 27 04:42:12 PM PDT 24
Finished Jun 27 04:42:23 PM PDT 24
Peak memory 232472 kb
Host smart-0af18774-895e-4ca4-ab77-990c7e11ab18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948516765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.948516765
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.158703265
Short name T407
Test name
Test status
Simulation time 28517110 ps
CPU time 1.87 seconds
Started Jun 27 04:42:13 PM PDT 24
Finished Jun 27 04:42:19 PM PDT 24
Peak memory 224016 kb
Host smart-183f9094-0205-4a66-af25-f8030a56e2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158703265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.158703265
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3830916349
Short name T1001
Test name
Test status
Simulation time 1609672267 ps
CPU time 16.33 seconds
Started Jun 27 04:42:13 PM PDT 24
Finished Jun 27 04:42:34 PM PDT 24
Peak memory 220284 kb
Host smart-87dc717d-8616-4d8e-b6f1-b96e4ac39db3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3830916349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3830916349
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1518696955
Short name T615
Test name
Test status
Simulation time 35707876726 ps
CPU time 322.31 seconds
Started Jun 27 04:42:03 PM PDT 24
Finished Jun 27 04:47:31 PM PDT 24
Peak memory 249472 kb
Host smart-33a18d62-6b36-4e52-b1fe-33e0d6475f7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518696955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1518696955
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.710218383
Short name T804
Test name
Test status
Simulation time 2772935739 ps
CPU time 22.65 seconds
Started Jun 27 04:42:15 PM PDT 24
Finished Jun 27 04:42:43 PM PDT 24
Peak memory 215732 kb
Host smart-8737c24f-5bd2-45e6-88e8-1a17dcc5de22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710218383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.710218383
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3157275688
Short name T387
Test name
Test status
Simulation time 5088154167 ps
CPU time 13.76 seconds
Started Jun 27 04:42:15 PM PDT 24
Finished Jun 27 04:42:34 PM PDT 24
Peak memory 216184 kb
Host smart-605dbb0f-f233-41d8-ad1d-1d5842f65a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157275688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3157275688
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.515571970
Short name T295
Test name
Test status
Simulation time 213935141 ps
CPU time 1.47 seconds
Started Jun 27 04:42:03 PM PDT 24
Finished Jun 27 04:42:09 PM PDT 24
Peak memory 216048 kb
Host smart-e994bcd8-f580-4c34-b5d5-289b33adcf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515571970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.515571970
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.828232805
Short name T974
Test name
Test status
Simulation time 77287953 ps
CPU time 0.94 seconds
Started Jun 27 04:42:06 PM PDT 24
Finished Jun 27 04:42:11 PM PDT 24
Peak memory 205752 kb
Host smart-7196543b-8490-495a-8a54-684193379cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828232805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.828232805
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2299817869
Short name T594
Test name
Test status
Simulation time 142341221 ps
CPU time 3.9 seconds
Started Jun 27 04:42:12 PM PDT 24
Finished Jun 27 04:42:19 PM PDT 24
Peak memory 232536 kb
Host smart-1564a28d-12b5-428a-8c39-da32f360ace0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299817869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2299817869
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3199769212
Short name T396
Test name
Test status
Simulation time 23604888 ps
CPU time 0.68 seconds
Started Jun 27 04:42:20 PM PDT 24
Finished Jun 27 04:42:24 PM PDT 24
Peak memory 205588 kb
Host smart-d5a1a959-1b97-4678-a250-4ede8e5a132c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199769212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3199769212
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.4061963579
Short name T344
Test name
Test status
Simulation time 296784350 ps
CPU time 2.1 seconds
Started Jun 27 04:42:02 PM PDT 24
Finished Jun 27 04:42:09 PM PDT 24
Peak memory 223960 kb
Host smart-e70f05e1-e51e-43ad-8c39-367d62ae9cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061963579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.4061963579
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2292359079
Short name T801
Test name
Test status
Simulation time 56972898 ps
CPU time 0.77 seconds
Started Jun 27 04:42:13 PM PDT 24
Finished Jun 27 04:42:18 PM PDT 24
Peak memory 206448 kb
Host smart-09189403-e504-46c6-9a89-5cd4554c863d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292359079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2292359079
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3815386056
Short name T52
Test name
Test status
Simulation time 21193439497 ps
CPU time 63.21 seconds
Started Jun 27 04:42:04 PM PDT 24
Finished Jun 27 04:43:12 PM PDT 24
Peak memory 251184 kb
Host smart-d4cd894f-02db-4174-802f-e12da1660ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815386056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3815386056
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2696405303
Short name T538
Test name
Test status
Simulation time 10447803923 ps
CPU time 73.49 seconds
Started Jun 27 04:42:04 PM PDT 24
Finished Jun 27 04:43:23 PM PDT 24
Peak memory 255640 kb
Host smart-09fa3ad3-5a37-4e06-bfeb-fa061c425d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696405303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2696405303
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1488316256
Short name T531
Test name
Test status
Simulation time 5264586836 ps
CPU time 26.9 seconds
Started Jun 27 04:42:03 PM PDT 24
Finished Jun 27 04:42:35 PM PDT 24
Peak memory 232720 kb
Host smart-4f4c3d99-087c-49d6-af62-6db4629f9f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488316256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1488316256
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.3595335948
Short name T257
Test name
Test status
Simulation time 833285036959 ps
CPU time 426.27 seconds
Started Jun 27 04:42:07 PM PDT 24
Finished Jun 27 04:49:17 PM PDT 24
Peak memory 265352 kb
Host smart-20b56ec4-ec73-4c4b-b395-1b810f000fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595335948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.3595335948
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3400803411
Short name T527
Test name
Test status
Simulation time 3494863643 ps
CPU time 17.46 seconds
Started Jun 27 04:42:02 PM PDT 24
Finished Jun 27 04:42:25 PM PDT 24
Peak memory 224376 kb
Host smart-bb7b9bc6-6123-4631-9940-871a5d0607c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400803411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3400803411
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1695784319
Short name T743
Test name
Test status
Simulation time 181132513 ps
CPU time 2.13 seconds
Started Jun 27 04:42:03 PM PDT 24
Finished Jun 27 04:42:11 PM PDT 24
Peak memory 223752 kb
Host smart-1bac9eb5-d0b1-4fac-8fe9-c737a83de034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695784319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1695784319
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1050429834
Short name T833
Test name
Test status
Simulation time 92907514 ps
CPU time 1.04 seconds
Started Jun 27 04:41:59 PM PDT 24
Finished Jun 27 04:42:06 PM PDT 24
Peak memory 217952 kb
Host smart-6d06e501-eab9-448d-a9f7-537c47840bac
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050429834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1050429834
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1376296366
Short name T132
Test name
Test status
Simulation time 656242062 ps
CPU time 4 seconds
Started Jun 27 04:42:05 PM PDT 24
Finished Jun 27 04:42:13 PM PDT 24
Peak memory 224272 kb
Host smart-f49aa75a-dd6f-469c-9310-17907d801c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376296366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1376296366
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1135864302
Short name T725
Test name
Test status
Simulation time 6862138369 ps
CPU time 10.49 seconds
Started Jun 27 04:42:06 PM PDT 24
Finished Jun 27 04:42:20 PM PDT 24
Peak memory 224424 kb
Host smart-abb8c0c4-390f-4d9f-87e5-7e5e59f7f2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135864302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1135864302
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1461770201
Short name T699
Test name
Test status
Simulation time 752360906 ps
CPU time 8.24 seconds
Started Jun 27 04:42:03 PM PDT 24
Finished Jun 27 04:42:16 PM PDT 24
Peak memory 222096 kb
Host smart-8ec3fab5-252f-4111-9a62-3fa2fbc2351a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1461770201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1461770201
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1763993018
Short name T55
Test name
Test status
Simulation time 71106556609 ps
CPU time 661.97 seconds
Started Jun 27 04:42:24 PM PDT 24
Finished Jun 27 04:53:28 PM PDT 24
Peak memory 265408 kb
Host smart-98aa741c-7ba5-4e5c-81b9-0c4c488d265f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763993018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1763993018
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3166138986
Short name T643
Test name
Test status
Simulation time 1856271862 ps
CPU time 16.78 seconds
Started Jun 27 04:42:03 PM PDT 24
Finished Jun 27 04:42:25 PM PDT 24
Peak memory 216352 kb
Host smart-fb0d1d3a-a87d-4b4d-ac99-97840709982e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166138986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3166138986
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1277614856
Short name T628
Test name
Test status
Simulation time 924123747 ps
CPU time 5.28 seconds
Started Jun 27 04:42:13 PM PDT 24
Finished Jun 27 04:42:23 PM PDT 24
Peak memory 216164 kb
Host smart-f1fd7a6e-a6cd-4e4f-a795-493bfa2ffbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277614856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1277614856
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1198881220
Short name T631
Test name
Test status
Simulation time 79758022 ps
CPU time 0.76 seconds
Started Jun 27 04:42:14 PM PDT 24
Finished Jun 27 04:42:19 PM PDT 24
Peak memory 206568 kb
Host smart-eb361b2c-5bee-435d-9336-92b67341b086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198881220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1198881220
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2770019383
Short name T932
Test name
Test status
Simulation time 77938476 ps
CPU time 0.91 seconds
Started Jun 27 04:42:13 PM PDT 24
Finished Jun 27 04:42:18 PM PDT 24
Peak memory 205812 kb
Host smart-e5832268-60a6-40b1-a49e-36c4d2990e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770019383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2770019383
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3791357886
Short name T834
Test name
Test status
Simulation time 83001775413 ps
CPU time 25.63 seconds
Started Jun 27 04:42:12 PM PDT 24
Finished Jun 27 04:42:42 PM PDT 24
Peak memory 232712 kb
Host smart-cdc089c3-50ff-45cf-9333-9910fdb8caa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791357886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3791357886
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1970003302
Short name T919
Test name
Test status
Simulation time 32364601 ps
CPU time 0.72 seconds
Started Jun 27 04:42:24 PM PDT 24
Finished Jun 27 04:42:27 PM PDT 24
Peak memory 205220 kb
Host smart-ba4a61dd-84ff-4446-8b86-ed0e5613ad46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970003302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1970003302
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.511221342
Short name T920
Test name
Test status
Simulation time 154800692 ps
CPU time 2.87 seconds
Started Jun 27 04:42:16 PM PDT 24
Finished Jun 27 04:42:23 PM PDT 24
Peak memory 224300 kb
Host smart-b2868c94-293f-450e-8591-6f28fde071d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511221342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.511221342
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2948566838
Short name T655
Test name
Test status
Simulation time 22492482 ps
CPU time 0.82 seconds
Started Jun 27 04:42:20 PM PDT 24
Finished Jun 27 04:42:24 PM PDT 24
Peak memory 206392 kb
Host smart-dd9d8538-863d-47fe-94e8-8c56466e47ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948566838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2948566838
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.747510658
Short name T45
Test name
Test status
Simulation time 1039289739 ps
CPU time 22.95 seconds
Started Jun 27 04:42:23 PM PDT 24
Finished Jun 27 04:42:49 PM PDT 24
Peak memory 239476 kb
Host smart-5b0a41e8-5f98-4507-970d-0b17ce49148e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747510658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.747510658
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2942218876
Short name T58
Test name
Test status
Simulation time 21320592056 ps
CPU time 87.78 seconds
Started Jun 27 04:42:19 PM PDT 24
Finished Jun 27 04:43:50 PM PDT 24
Peak memory 251388 kb
Host smart-0a8eab1f-c857-4db9-9c92-29997efd4628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942218876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2942218876
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.4152987219
Short name T934
Test name
Test status
Simulation time 13143689765 ps
CPU time 94.63 seconds
Started Jun 27 04:42:15 PM PDT 24
Finished Jun 27 04:43:54 PM PDT 24
Peak memory 249092 kb
Host smart-5fca5b58-c936-4ebf-8745-5e7e9e908ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152987219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.4152987219
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3480146931
Short name T788
Test name
Test status
Simulation time 124839674 ps
CPU time 2.45 seconds
Started Jun 27 04:42:21 PM PDT 24
Finished Jun 27 04:42:27 PM PDT 24
Peak memory 232572 kb
Host smart-982d5502-652a-441f-bbda-5e02386fd3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480146931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3480146931
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.859545600
Short name T971
Test name
Test status
Simulation time 8015765610 ps
CPU time 46.32 seconds
Started Jun 27 04:42:29 PM PDT 24
Finished Jun 27 04:43:19 PM PDT 24
Peak memory 236376 kb
Host smart-cfcc143e-8182-4ffa-80d9-dfd89c0c2f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859545600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.859545600
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.688258137
Short name T208
Test name
Test status
Simulation time 2472640994 ps
CPU time 12.53 seconds
Started Jun 27 04:42:20 PM PDT 24
Finished Jun 27 04:42:36 PM PDT 24
Peak memory 232652 kb
Host smart-2792abd3-f977-47c5-8383-9c81044abb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688258137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.688258137
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1629051323
Short name T756
Test name
Test status
Simulation time 15094146013 ps
CPU time 24.99 seconds
Started Jun 27 04:42:17 PM PDT 24
Finished Jun 27 04:42:46 PM PDT 24
Peak memory 229032 kb
Host smart-af4da64e-e0ff-41c4-bf77-5e2ad2145967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629051323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1629051323
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3467306921
Short name T406
Test name
Test status
Simulation time 24976780 ps
CPU time 1.01 seconds
Started Jun 27 04:42:17 PM PDT 24
Finished Jun 27 04:42:22 PM PDT 24
Peak memory 216644 kb
Host smart-cf2cc472-d336-465b-8625-5bbf1bb44f36
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467306921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3467306921
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.520467088
Short name T186
Test name
Test status
Simulation time 17244355201 ps
CPU time 12.98 seconds
Started Jun 27 04:42:16 PM PDT 24
Finished Jun 27 04:42:34 PM PDT 24
Peak memory 232648 kb
Host smart-9360a84e-7a8b-4bfb-bced-d1bbad4c848e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520467088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.520467088
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.4125697153
Short name T608
Test name
Test status
Simulation time 7455897805 ps
CPU time 5.21 seconds
Started Jun 27 04:42:15 PM PDT 24
Finished Jun 27 04:42:25 PM PDT 24
Peak memory 232556 kb
Host smart-5186b51a-3173-463a-a937-82a69d9c29ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125697153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.4125697153
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3997294234
Short name T584
Test name
Test status
Simulation time 348937061 ps
CPU time 5.08 seconds
Started Jun 27 04:42:28 PM PDT 24
Finished Jun 27 04:42:36 PM PDT 24
Peak memory 222208 kb
Host smart-de03a5ed-a3a8-4757-9cdc-aad4d2c153e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3997294234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3997294234
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3410148427
Short name T258
Test name
Test status
Simulation time 103010649938 ps
CPU time 179.41 seconds
Started Jun 27 04:42:25 PM PDT 24
Finished Jun 27 04:45:27 PM PDT 24
Peak memory 260536 kb
Host smart-340f0495-d76f-493e-82c3-56e3fbeb47d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410148427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3410148427
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2302466763
Short name T910
Test name
Test status
Simulation time 5515303425 ps
CPU time 8.89 seconds
Started Jun 27 04:42:34 PM PDT 24
Finished Jun 27 04:42:45 PM PDT 24
Peak memory 216148 kb
Host smart-211cf5ff-4cbe-495a-8ba2-f0f9808ec1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302466763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2302466763
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2751042627
Short name T789
Test name
Test status
Simulation time 54463628251 ps
CPU time 11.36 seconds
Started Jun 27 04:42:16 PM PDT 24
Finished Jun 27 04:42:32 PM PDT 24
Peak memory 216252 kb
Host smart-7d15e816-cf8a-45c4-a13c-d41a291f56f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751042627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2751042627
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2781014925
Short name T829
Test name
Test status
Simulation time 128586657 ps
CPU time 1.44 seconds
Started Jun 27 04:42:17 PM PDT 24
Finished Jun 27 04:42:23 PM PDT 24
Peak memory 216080 kb
Host smart-f86fa172-c76a-4716-a38d-70e00b606c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781014925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2781014925
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.259172440
Short name T670
Test name
Test status
Simulation time 31948926 ps
CPU time 0.75 seconds
Started Jun 27 04:42:21 PM PDT 24
Finished Jun 27 04:42:25 PM PDT 24
Peak memory 205796 kb
Host smart-16043f1d-8d7f-4178-955f-2d1b9303a716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259172440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.259172440
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.4066072208
Short name T569
Test name
Test status
Simulation time 15516882411 ps
CPU time 44.57 seconds
Started Jun 27 04:42:16 PM PDT 24
Finished Jun 27 04:43:04 PM PDT 24
Peak memory 232652 kb
Host smart-ece89704-1dd3-4255-91d2-07e56ab94161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066072208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.4066072208
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.496044679
Short name T327
Test name
Test status
Simulation time 33032092 ps
CPU time 0.72 seconds
Started Jun 27 04:42:21 PM PDT 24
Finished Jun 27 04:42:25 PM PDT 24
Peak memory 205692 kb
Host smart-09f06b4c-09c7-461a-8d5a-71982e4e9077
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496044679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.496044679
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3835663749
Short name T224
Test name
Test status
Simulation time 819538731 ps
CPU time 5.71 seconds
Started Jun 27 04:42:20 PM PDT 24
Finished Jun 27 04:42:29 PM PDT 24
Peak memory 232532 kb
Host smart-28aeb2cd-fd49-4de1-bd62-11467cc17ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835663749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3835663749
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1935102413
Short name T67
Test name
Test status
Simulation time 43634818 ps
CPU time 0.73 seconds
Started Jun 27 04:42:18 PM PDT 24
Finished Jun 27 04:42:22 PM PDT 24
Peak memory 205456 kb
Host smart-9b09a115-2058-4287-8d6d-c610183343d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935102413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1935102413
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1866498767
Short name T1006
Test name
Test status
Simulation time 145114215937 ps
CPU time 261.5 seconds
Started Jun 27 04:42:23 PM PDT 24
Finished Jun 27 04:46:48 PM PDT 24
Peak memory 254884 kb
Host smart-75039abe-6673-43b7-8bb9-b6e5defe3932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866498767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1866498767
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3821171130
Short name T427
Test name
Test status
Simulation time 7204240998 ps
CPU time 47.74 seconds
Started Jun 27 04:42:16 PM PDT 24
Finished Jun 27 04:43:08 PM PDT 24
Peak memory 236260 kb
Host smart-47aec31d-0f3e-4eeb-9dfd-e8380e66a0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821171130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3821171130
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.589694790
Short name T775
Test name
Test status
Simulation time 165284611060 ps
CPU time 358.84 seconds
Started Jun 27 04:42:20 PM PDT 24
Finished Jun 27 04:48:22 PM PDT 24
Peak memory 257304 kb
Host smart-081308e0-2714-410e-8aaf-d66c901b4734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589694790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.589694790
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2918759343
Short name T689
Test name
Test status
Simulation time 8389315869 ps
CPU time 34.99 seconds
Started Jun 27 04:42:25 PM PDT 24
Finished Jun 27 04:43:03 PM PDT 24
Peak memory 249460 kb
Host smart-c413682c-5003-4198-be28-85415b0787c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918759343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2918759343
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.421264020
Short name T37
Test name
Test status
Simulation time 22187601722 ps
CPU time 103.61 seconds
Started Jun 27 04:42:21 PM PDT 24
Finished Jun 27 04:44:08 PM PDT 24
Peak memory 264020 kb
Host smart-6a170263-739b-4a14-af6c-514826de5421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421264020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds
.421264020
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.180280017
Short name T613
Test name
Test status
Simulation time 917579436 ps
CPU time 10.25 seconds
Started Jun 27 04:42:15 PM PDT 24
Finished Jun 27 04:42:30 PM PDT 24
Peak memory 232488 kb
Host smart-a74f9521-96e9-4157-b4a2-7ee4a882146b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180280017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.180280017
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3017684079
Short name T187
Test name
Test status
Simulation time 32268936 ps
CPU time 2.4 seconds
Started Jun 27 04:42:19 PM PDT 24
Finished Jun 27 04:42:25 PM PDT 24
Peak memory 232520 kb
Host smart-31b44033-9c72-49f6-b987-25599e6b3aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017684079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3017684079
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2442884989
Short name T648
Test name
Test status
Simulation time 121437463 ps
CPU time 1.05 seconds
Started Jun 27 04:42:16 PM PDT 24
Finished Jun 27 04:42:22 PM PDT 24
Peak memory 216600 kb
Host smart-90482125-78f4-4316-83cb-7f1896486bdd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442884989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2442884989
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.957547112
Short name T236
Test name
Test status
Simulation time 32915080571 ps
CPU time 33.49 seconds
Started Jun 27 04:42:22 PM PDT 24
Finished Jun 27 04:42:59 PM PDT 24
Peak memory 248864 kb
Host smart-ee19409e-adc7-4c27-beb9-ed5465b95779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957547112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.957547112
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3004489076
Short name T174
Test name
Test status
Simulation time 5697967494 ps
CPU time 11.52 seconds
Started Jun 27 04:42:16 PM PDT 24
Finished Jun 27 04:42:32 PM PDT 24
Peak memory 224432 kb
Host smart-088dfe5c-84a4-420f-873b-1418932cfffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004489076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3004489076
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1257453797
Short name T400
Test name
Test status
Simulation time 893958680 ps
CPU time 3.91 seconds
Started Jun 27 04:42:25 PM PDT 24
Finished Jun 27 04:42:32 PM PDT 24
Peak memory 222912 kb
Host smart-28d4a881-c6c6-47af-94c9-12def9ab64db
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1257453797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1257453797
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1928652148
Short name T153
Test name
Test status
Simulation time 117580543287 ps
CPU time 278.92 seconds
Started Jun 27 04:42:18 PM PDT 24
Finished Jun 27 04:47:01 PM PDT 24
Peak memory 249380 kb
Host smart-c673abdd-95d0-4712-8841-822f1f6c58c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928652148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1928652148
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.939548886
Short name T24
Test name
Test status
Simulation time 5088206329 ps
CPU time 15.07 seconds
Started Jun 27 04:42:17 PM PDT 24
Finished Jun 27 04:42:36 PM PDT 24
Peak memory 216300 kb
Host smart-31932576-dd35-48d7-8407-383d4dba2d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939548886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.939548886
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.227348628
Short name T353
Test name
Test status
Simulation time 745017695 ps
CPU time 3.21 seconds
Started Jun 27 04:42:23 PM PDT 24
Finished Jun 27 04:42:29 PM PDT 24
Peak memory 216052 kb
Host smart-797ce905-6f12-48b9-b850-cab9973a0646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227348628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.227348628
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.127094711
Short name T7
Test name
Test status
Simulation time 475547484 ps
CPU time 3.39 seconds
Started Jun 27 04:42:19 PM PDT 24
Finished Jun 27 04:42:26 PM PDT 24
Peak memory 216136 kb
Host smart-1cbbfbbd-0b09-47f7-8e3b-372af1343d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127094711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.127094711
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1349383403
Short name T514
Test name
Test status
Simulation time 43455978 ps
CPU time 0.88 seconds
Started Jun 27 04:42:16 PM PDT 24
Finished Jun 27 04:42:21 PM PDT 24
Peak memory 205836 kb
Host smart-dbae26ff-bfd9-4f92-a7c4-7b211c2e7031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349383403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1349383403
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.17478492
Short name T170
Test name
Test status
Simulation time 1096095639 ps
CPU time 3.81 seconds
Started Jun 27 04:42:22 PM PDT 24
Finished Jun 27 04:42:29 PM PDT 24
Peak memory 224360 kb
Host smart-012f35d0-0792-4bf9-ba59-17987514e62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17478492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.17478492
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2599710790
Short name T69
Test name
Test status
Simulation time 17191253 ps
CPU time 0.77 seconds
Started Jun 27 04:41:27 PM PDT 24
Finished Jun 27 04:41:32 PM PDT 24
Peak memory 204692 kb
Host smart-25e1c7d2-abb8-4dc6-8476-04fe7f4b1068
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599710790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
599710790
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.647627088
Short name T215
Test name
Test status
Simulation time 318973494 ps
CPU time 3.04 seconds
Started Jun 27 04:41:26 PM PDT 24
Finished Jun 27 04:41:33 PM PDT 24
Peak memory 232448 kb
Host smart-d803e313-99f8-4ff8-8952-83457ee16a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647627088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.647627088
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2493846731
Short name T449
Test name
Test status
Simulation time 27028491 ps
CPU time 0.75 seconds
Started Jun 27 04:41:22 PM PDT 24
Finished Jun 27 04:41:26 PM PDT 24
Peak memory 206484 kb
Host smart-65f9bdf7-e35c-4b7a-b50e-947a6a76f816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493846731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2493846731
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2823050378
Short name T551
Test name
Test status
Simulation time 4987031718 ps
CPU time 32.84 seconds
Started Jun 27 04:41:25 PM PDT 24
Finished Jun 27 04:42:02 PM PDT 24
Peak memory 232608 kb
Host smart-a787217f-31f9-422b-8214-eb54c8581e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823050378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2823050378
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.614164889
Short name T445
Test name
Test status
Simulation time 16911164421 ps
CPU time 139.95 seconds
Started Jun 27 04:41:26 PM PDT 24
Finished Jun 27 04:43:51 PM PDT 24
Peak memory 264184 kb
Host smart-26789bf3-5d84-43f3-ab41-9359bfc5f704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614164889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.614164889
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.730983202
Short name T133
Test name
Test status
Simulation time 231935663221 ps
CPU time 476.31 seconds
Started Jun 27 04:41:25 PM PDT 24
Finished Jun 27 04:49:26 PM PDT 24
Peak memory 265160 kb
Host smart-080990f0-5df3-4d07-8a72-8295bd9f9482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730983202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
730983202
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.887257317
Short name T911
Test name
Test status
Simulation time 3821491511 ps
CPU time 14.12 seconds
Started Jun 27 04:41:29 PM PDT 24
Finished Jun 27 04:41:47 PM PDT 24
Peak memory 224432 kb
Host smart-adec0e54-4c68-4f50-8db4-b130707cfb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887257317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.887257317
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.2625126789
Short name T254
Test name
Test status
Simulation time 29366987854 ps
CPU time 189.94 seconds
Started Jun 27 04:41:24 PM PDT 24
Finished Jun 27 04:44:39 PM PDT 24
Peak memory 239016 kb
Host smart-1db1bbbf-cd09-48fc-a116-f4a357484143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625126789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.2625126789
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3405095656
Short name T941
Test name
Test status
Simulation time 2183825673 ps
CPU time 8.89 seconds
Started Jun 27 04:41:26 PM PDT 24
Finished Jun 27 04:41:39 PM PDT 24
Peak memory 224368 kb
Host smart-38041d30-0caf-4b85-aa48-32271e65d3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405095656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3405095656
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1862806601
Short name T555
Test name
Test status
Simulation time 7709326402 ps
CPU time 79.95 seconds
Started Jun 27 04:41:22 PM PDT 24
Finished Jun 27 04:42:46 PM PDT 24
Peak memory 232624 kb
Host smart-09bdf6c2-b7e1-4d66-82f3-a6b3f7716d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862806601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1862806601
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2170656220
Short name T320
Test name
Test status
Simulation time 19118611 ps
CPU time 1.08 seconds
Started Jun 27 04:41:24 PM PDT 24
Finished Jun 27 04:41:30 PM PDT 24
Peak memory 216692 kb
Host smart-63312dd2-24ee-45e3-ba09-401368373036
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170656220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2170656220
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1268659642
Short name T233
Test name
Test status
Simulation time 4458138334 ps
CPU time 9.09 seconds
Started Jun 27 04:41:26 PM PDT 24
Finished Jun 27 04:41:40 PM PDT 24
Peak memory 232612 kb
Host smart-c9a46349-1b0a-42fb-be0d-f45019193d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268659642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1268659642
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3485425287
Short name T969
Test name
Test status
Simulation time 306105718 ps
CPU time 4.24 seconds
Started Jun 27 04:41:30 PM PDT 24
Finished Jun 27 04:41:37 PM PDT 24
Peak memory 232504 kb
Host smart-ea28d0eb-7edb-4bbb-91f1-558eeac253c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485425287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3485425287
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.495499898
Short name T870
Test name
Test status
Simulation time 1506904663 ps
CPU time 13.93 seconds
Started Jun 27 04:41:27 PM PDT 24
Finished Jun 27 04:41:45 PM PDT 24
Peak memory 219072 kb
Host smart-b0e1c787-f115-4a4e-b07d-395bf5c9b4a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=495499898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.495499898
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.886749320
Short name T74
Test name
Test status
Simulation time 139526552 ps
CPU time 0.96 seconds
Started Jun 27 04:41:26 PM PDT 24
Finished Jun 27 04:41:32 PM PDT 24
Peak memory 235536 kb
Host smart-5971dca5-9c5d-478b-b1be-395adc8a34c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886749320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.886749320
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3916517834
Short name T588
Test name
Test status
Simulation time 2644364771 ps
CPU time 13.85 seconds
Started Jun 27 04:41:26 PM PDT 24
Finished Jun 27 04:41:45 PM PDT 24
Peak memory 216296 kb
Host smart-015b6de3-0199-473a-810b-8b59e2aa5e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916517834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3916517834
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.774735585
Short name T905
Test name
Test status
Simulation time 741675789 ps
CPU time 5.29 seconds
Started Jun 27 04:41:22 PM PDT 24
Finished Jun 27 04:41:32 PM PDT 24
Peak memory 216116 kb
Host smart-5c37ed0b-ce9b-4a44-94f8-cdd2ddf85996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774735585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.774735585
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.234835293
Short name T606
Test name
Test status
Simulation time 31632767 ps
CPU time 0.77 seconds
Started Jun 27 04:41:30 PM PDT 24
Finished Jun 27 04:41:34 PM PDT 24
Peak memory 205504 kb
Host smart-dd8fc0cc-439d-4fae-8ff0-1a078d256526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234835293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.234835293
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.423111776
Short name T313
Test name
Test status
Simulation time 81272901 ps
CPU time 0.8 seconds
Started Jun 27 04:41:30 PM PDT 24
Finished Jun 27 04:41:34 PM PDT 24
Peak memory 205520 kb
Host smart-af0fc70b-abd5-427e-a732-4791c242bd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423111776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.423111776
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3997826405
Short name T480
Test name
Test status
Simulation time 7554589888 ps
CPU time 8.45 seconds
Started Jun 27 04:41:26 PM PDT 24
Finished Jun 27 04:41:39 PM PDT 24
Peak memory 224416 kb
Host smart-a3638c4d-7d6f-4b7a-8517-23a658e493d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997826405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3997826405
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.922015303
Short name T589
Test name
Test status
Simulation time 46638508 ps
CPU time 0.73 seconds
Started Jun 27 04:42:24 PM PDT 24
Finished Jun 27 04:42:28 PM PDT 24
Peak memory 205268 kb
Host smart-fdd32dc4-153f-4f7a-ba63-7ed1d420ac5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922015303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.922015303
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.4230165029
Short name T241
Test name
Test status
Simulation time 1017023235 ps
CPU time 5.08 seconds
Started Jun 27 04:42:17 PM PDT 24
Finished Jun 27 04:42:26 PM PDT 24
Peak memory 224368 kb
Host smart-3747b1ea-8d38-40ba-934b-9ed7b237d21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230165029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.4230165029
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2090504547
Short name T572
Test name
Test status
Simulation time 19560951 ps
CPU time 0.82 seconds
Started Jun 27 04:42:22 PM PDT 24
Finished Jun 27 04:42:26 PM PDT 24
Peak memory 206428 kb
Host smart-3e09ab76-4710-4a0a-88b1-424cc0da207d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090504547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2090504547
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1424874280
Short name T853
Test name
Test status
Simulation time 762454862 ps
CPU time 8.4 seconds
Started Jun 27 04:42:29 PM PDT 24
Finished Jun 27 04:42:41 PM PDT 24
Peak memory 234840 kb
Host smart-7d5b8958-75cb-4b3b-983e-897298906a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424874280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1424874280
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1755737662
Short name T457
Test name
Test status
Simulation time 17217798058 ps
CPU time 67.28 seconds
Started Jun 27 04:42:22 PM PDT 24
Finished Jun 27 04:43:33 PM PDT 24
Peak memory 249268 kb
Host smart-73232a37-f1ea-4492-8c71-eb009163b84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755737662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1755737662
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3465842689
Short name T271
Test name
Test status
Simulation time 2845357889 ps
CPU time 41.73 seconds
Started Jun 27 04:42:44 PM PDT 24
Finished Jun 27 04:43:32 PM PDT 24
Peak memory 224440 kb
Host smart-1635c651-9b0e-46b5-a70f-21ddbe54991c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465842689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3465842689
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.3470108679
Short name T373
Test name
Test status
Simulation time 19127240024 ps
CPU time 98.86 seconds
Started Jun 27 04:42:28 PM PDT 24
Finished Jun 27 04:44:09 PM PDT 24
Peak memory 255916 kb
Host smart-145c1072-9f09-4b76-b19b-c722e513d475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470108679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.3470108679
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1999897315
Short name T645
Test name
Test status
Simulation time 81674128 ps
CPU time 2.41 seconds
Started Jun 27 04:42:19 PM PDT 24
Finished Jun 27 04:42:25 PM PDT 24
Peak memory 232304 kb
Host smart-5d5c9648-c8a3-42fe-ab67-0a31155768be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999897315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1999897315
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3589159811
Short name T434
Test name
Test status
Simulation time 917866442 ps
CPU time 4.44 seconds
Started Jun 27 04:42:24 PM PDT 24
Finished Jun 27 04:42:31 PM PDT 24
Peak memory 224268 kb
Host smart-6523dd01-df32-491c-b3e4-1f13e0ad5107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589159811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3589159811
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1282018307
Short name T228
Test name
Test status
Simulation time 55381372058 ps
CPU time 40.52 seconds
Started Jun 27 04:42:25 PM PDT 24
Finished Jun 27 04:43:08 PM PDT 24
Peak memory 249376 kb
Host smart-cf2c5f7e-9818-4691-b034-a8980f262669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282018307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1282018307
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1646307578
Short name T950
Test name
Test status
Simulation time 2194109784 ps
CPU time 10.42 seconds
Started Jun 27 04:42:24 PM PDT 24
Finished Jun 27 04:42:37 PM PDT 24
Peak memory 218988 kb
Host smart-0a47a880-abd5-49eb-94de-534189bfb293
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1646307578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1646307578
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1216143139
Short name T626
Test name
Test status
Simulation time 45653621832 ps
CPU time 139.22 seconds
Started Jun 27 04:42:26 PM PDT 24
Finished Jun 27 04:44:47 PM PDT 24
Peak memory 259784 kb
Host smart-f74597ec-b210-416d-8e46-1ab818f82fd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216143139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1216143139
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3402774364
Short name T679
Test name
Test status
Simulation time 10999799 ps
CPU time 0.72 seconds
Started Jun 27 04:42:20 PM PDT 24
Finished Jun 27 04:42:24 PM PDT 24
Peak memory 205852 kb
Host smart-a722a846-01b8-4b9d-b4e4-2ef410bedbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402774364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3402774364
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3831474278
Short name T975
Test name
Test status
Simulation time 9923110883 ps
CPU time 9.01 seconds
Started Jun 27 04:42:21 PM PDT 24
Finished Jun 27 04:42:33 PM PDT 24
Peak memory 216480 kb
Host smart-40403c34-fc12-4fa3-bbda-52ef6b4dcb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831474278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3831474278
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.183858066
Short name T874
Test name
Test status
Simulation time 374410668 ps
CPU time 1.94 seconds
Started Jun 27 04:42:25 PM PDT 24
Finished Jun 27 04:42:29 PM PDT 24
Peak memory 216068 kb
Host smart-e818cf87-2bcb-4770-92f5-d36638fbdec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183858066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.183858066
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.606898538
Short name T964
Test name
Test status
Simulation time 31384801 ps
CPU time 0.72 seconds
Started Jun 27 04:42:28 PM PDT 24
Finished Jun 27 04:42:31 PM PDT 24
Peak memory 205784 kb
Host smart-0feb58a0-99d8-40bc-988b-9af0844f4e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606898538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.606898538
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3641992128
Short name T842
Test name
Test status
Simulation time 1290251128 ps
CPU time 9.87 seconds
Started Jun 27 04:42:26 PM PDT 24
Finished Jun 27 04:42:38 PM PDT 24
Peak memory 232560 kb
Host smart-3611cc2a-afbb-4a59-8a5a-38bba5ab4b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641992128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3641992128
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.534664817
Short name T723
Test name
Test status
Simulation time 16091038 ps
CPU time 0.78 seconds
Started Jun 27 04:42:29 PM PDT 24
Finished Jun 27 04:42:33 PM PDT 24
Peak memory 205036 kb
Host smart-839f10da-a95a-479f-a816-b06eba1258b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534664817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.534664817
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1022487378
Short name T311
Test name
Test status
Simulation time 59869760 ps
CPU time 2.33 seconds
Started Jun 27 04:42:27 PM PDT 24
Finished Jun 27 04:42:31 PM PDT 24
Peak memory 232352 kb
Host smart-ba79a2f0-6ec9-4664-9732-7483cc36cb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022487378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1022487378
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1973710621
Short name T340
Test name
Test status
Simulation time 21444973 ps
CPU time 0.74 seconds
Started Jun 27 04:42:28 PM PDT 24
Finished Jun 27 04:42:31 PM PDT 24
Peak memory 205416 kb
Host smart-224d31a4-dde1-463a-af37-b1e053773cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973710621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1973710621
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1818472710
Short name T852
Test name
Test status
Simulation time 17778277676 ps
CPU time 156.27 seconds
Started Jun 27 04:42:29 PM PDT 24
Finished Jun 27 04:45:08 PM PDT 24
Peak memory 257548 kb
Host smart-c50dfe03-172b-4f44-84f1-4335cc69c3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818472710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1818472710
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.299536538
Short name T436
Test name
Test status
Simulation time 41278412546 ps
CPU time 69.43 seconds
Started Jun 27 04:42:25 PM PDT 24
Finished Jun 27 04:43:37 PM PDT 24
Peak memory 256424 kb
Host smart-f7428216-1bb3-48e9-bb1c-953b4fd91ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299536538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.299536538
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1891058734
Short name T47
Test name
Test status
Simulation time 22581497378 ps
CPU time 67.47 seconds
Started Jun 27 04:42:23 PM PDT 24
Finished Jun 27 04:43:33 PM PDT 24
Peak memory 253244 kb
Host smart-35533d95-f74b-431f-a2c9-dbca5cd1def3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891058734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1891058734
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3689858471
Short name T274
Test name
Test status
Simulation time 1509958524 ps
CPU time 23.13 seconds
Started Jun 27 04:42:29 PM PDT 24
Finished Jun 27 04:42:55 PM PDT 24
Peak memory 235660 kb
Host smart-1108981a-c56e-45ee-b1af-ad55146061ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689858471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3689858471
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.1727963721
Short name T512
Test name
Test status
Simulation time 4281728389 ps
CPU time 31.9 seconds
Started Jun 27 04:42:29 PM PDT 24
Finished Jun 27 04:43:05 PM PDT 24
Peak memory 235216 kb
Host smart-229ec317-2db4-4696-bd71-4a46c8812c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727963721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.1727963721
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.4294795137
Short name T222
Test name
Test status
Simulation time 496997068 ps
CPU time 3.1 seconds
Started Jun 27 04:42:29 PM PDT 24
Finished Jun 27 04:42:35 PM PDT 24
Peak memory 232496 kb
Host smart-6364d9cb-47b4-4bc6-92af-8e224ad0fb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294795137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.4294795137
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1104921241
Short name T218
Test name
Test status
Simulation time 4104890920 ps
CPU time 43.38 seconds
Started Jun 27 04:42:24 PM PDT 24
Finished Jun 27 04:43:10 PM PDT 24
Peak memory 232556 kb
Host smart-79bce13a-25a6-46d9-9e95-b423c236907e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104921241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1104921241
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2187979599
Short name T592
Test name
Test status
Simulation time 1818794861 ps
CPU time 11.73 seconds
Started Jun 27 04:42:24 PM PDT 24
Finished Jun 27 04:42:38 PM PDT 24
Peak memory 232540 kb
Host smart-1e92275e-d5f5-4003-8db1-2277d4c290d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187979599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2187979599
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2158412684
Short name T616
Test name
Test status
Simulation time 264920356 ps
CPU time 2.29 seconds
Started Jun 27 04:42:29 PM PDT 24
Finished Jun 27 04:42:35 PM PDT 24
Peak memory 224348 kb
Host smart-995f7bef-c3e0-4e0b-abc7-b148be517044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158412684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2158412684
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1166258856
Short name T368
Test name
Test status
Simulation time 225092775 ps
CPU time 4.17 seconds
Started Jun 27 04:42:27 PM PDT 24
Finished Jun 27 04:42:34 PM PDT 24
Peak memory 220140 kb
Host smart-d2240010-aa1e-4004-b095-5bebbae95c8d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1166258856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1166258856
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2504900700
Short name T747
Test name
Test status
Simulation time 76421841 ps
CPU time 0.91 seconds
Started Jun 27 04:42:25 PM PDT 24
Finished Jun 27 04:42:28 PM PDT 24
Peak memory 206752 kb
Host smart-69b34c20-91a9-4016-9bf0-bcf8b973cf6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504900700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2504900700
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.436186484
Short name T283
Test name
Test status
Simulation time 16126468489 ps
CPU time 19.71 seconds
Started Jun 27 04:42:29 PM PDT 24
Finished Jun 27 04:42:52 PM PDT 24
Peak memory 216184 kb
Host smart-c753b2e2-3d4a-40c0-bd90-40125e979351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436186484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.436186484
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3777646116
Short name T62
Test name
Test status
Simulation time 20731601 ps
CPU time 0.69 seconds
Started Jun 27 04:42:21 PM PDT 24
Finished Jun 27 04:42:25 PM PDT 24
Peak memory 205504 kb
Host smart-a0ca3da4-299f-4757-ae1d-fdf3558351a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777646116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3777646116
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3661346359
Short name T758
Test name
Test status
Simulation time 127854128 ps
CPU time 1.8 seconds
Started Jun 27 04:42:24 PM PDT 24
Finished Jun 27 04:42:29 PM PDT 24
Peak memory 216100 kb
Host smart-4bddd726-ae65-4eda-b751-0d058c5ca78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661346359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3661346359
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3258617565
Short name T1010
Test name
Test status
Simulation time 104760720 ps
CPU time 0.7 seconds
Started Jun 27 04:42:24 PM PDT 24
Finished Jun 27 04:42:28 PM PDT 24
Peak memory 205440 kb
Host smart-abfb8781-c544-4fff-9b26-c97f628ce8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258617565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3258617565
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2571899640
Short name T817
Test name
Test status
Simulation time 9678954584 ps
CPU time 9.84 seconds
Started Jun 27 04:42:23 PM PDT 24
Finished Jun 27 04:42:35 PM PDT 24
Peak memory 232644 kb
Host smart-cde3f94d-d04e-4739-8d5c-8914262b3bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571899640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2571899640
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3041966970
Short name T935
Test name
Test status
Simulation time 39335026 ps
CPU time 0.68 seconds
Started Jun 27 04:42:42 PM PDT 24
Finished Jun 27 04:42:46 PM PDT 24
Peak memory 205308 kb
Host smart-a15adedb-1a02-4da0-9d1d-2c8893286414
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041966970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3041966970
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1551661638
Short name T962
Test name
Test status
Simulation time 1047107833 ps
CPU time 6.93 seconds
Started Jun 27 04:42:28 PM PDT 24
Finished Jun 27 04:42:38 PM PDT 24
Peak memory 224292 kb
Host smart-4922014a-e0bd-4ac4-81fa-44046df9fe60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551661638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1551661638
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.429731543
Short name T403
Test name
Test status
Simulation time 24055415 ps
CPU time 0.74 seconds
Started Jun 27 04:42:29 PM PDT 24
Finished Jun 27 04:42:33 PM PDT 24
Peak memory 205788 kb
Host smart-54d437b5-8ecc-4c81-a419-4b87ac0e1f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429731543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.429731543
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3326164595
Short name T48
Test name
Test status
Simulation time 14485800254 ps
CPU time 148.26 seconds
Started Jun 27 04:42:27 PM PDT 24
Finished Jun 27 04:44:57 PM PDT 24
Peak memory 256472 kb
Host smart-078dcf6f-ca5a-43bd-924d-a929fe8e6f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326164595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3326164595
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.4003832209
Short name T51
Test name
Test status
Simulation time 20649930035 ps
CPU time 54.72 seconds
Started Jun 27 04:42:27 PM PDT 24
Finished Jun 27 04:43:24 PM PDT 24
Peak memory 240912 kb
Host smart-9a4929dd-91c5-4a6b-9db0-4a5c8e257f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003832209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.4003832209
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1808851549
Short name T754
Test name
Test status
Simulation time 6609066308 ps
CPU time 82.69 seconds
Started Jun 27 04:42:47 PM PDT 24
Finished Jun 27 04:44:16 PM PDT 24
Peak memory 256908 kb
Host smart-64bc4821-f86f-453e-bb6b-535e0fc3d250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808851549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1808851549
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3937269576
Short name T625
Test name
Test status
Simulation time 765015395 ps
CPU time 7.15 seconds
Started Jun 27 04:42:27 PM PDT 24
Finished Jun 27 04:42:37 PM PDT 24
Peak memory 232564 kb
Host smart-c3cfa857-c42a-4e4f-b226-4619a7d2496d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937269576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3937269576
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.543717258
Short name T676
Test name
Test status
Simulation time 6745710522 ps
CPU time 25.86 seconds
Started Jun 27 04:42:26 PM PDT 24
Finished Jun 27 04:42:54 PM PDT 24
Peak memory 249060 kb
Host smart-9e089da5-03e6-4a25-bf65-c9697b216cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543717258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds
.543717258
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3779831532
Short name T57
Test name
Test status
Simulation time 364694337 ps
CPU time 4.41 seconds
Started Jun 27 04:42:27 PM PDT 24
Finished Jun 27 04:42:34 PM PDT 24
Peak memory 232608 kb
Host smart-c89a017e-0a58-4096-a597-f401ba8b70d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779831532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3779831532
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3230613905
Short name T418
Test name
Test status
Simulation time 915413462 ps
CPU time 10.97 seconds
Started Jun 27 04:42:29 PM PDT 24
Finished Jun 27 04:42:44 PM PDT 24
Peak memory 240716 kb
Host smart-d2dd33b1-e12e-4e4d-929f-c29f5d636309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230613905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3230613905
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1324963245
Short name T365
Test name
Test status
Simulation time 14215227845 ps
CPU time 5.23 seconds
Started Jun 27 04:42:28 PM PDT 24
Finished Jun 27 04:42:36 PM PDT 24
Peak memory 224428 kb
Host smart-285f2628-9df7-4717-b566-7db169e1e770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324963245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1324963245
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.650077023
Short name T390
Test name
Test status
Simulation time 14285039768 ps
CPU time 10.99 seconds
Started Jun 27 04:42:23 PM PDT 24
Finished Jun 27 04:42:37 PM PDT 24
Peak memory 224516 kb
Host smart-dd6002a5-2fc4-479f-9247-4b65c83b2d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650077023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.650077023
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.815798770
Short name T866
Test name
Test status
Simulation time 440350641 ps
CPU time 5.24 seconds
Started Jun 27 04:42:26 PM PDT 24
Finished Jun 27 04:42:34 PM PDT 24
Peak memory 219268 kb
Host smart-06c8dd42-4b98-4a0a-9e42-727e08bbeb5d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=815798770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.815798770
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2624883382
Short name T840
Test name
Test status
Simulation time 102912811471 ps
CPU time 243.64 seconds
Started Jun 27 04:42:43 PM PDT 24
Finished Jun 27 04:46:51 PM PDT 24
Peak memory 250964 kb
Host smart-4ddf609d-b56f-4b44-a59b-dad7fe73c200
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624883382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2624883382
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1617949276
Short name T1009
Test name
Test status
Simulation time 30528613 ps
CPU time 0.78 seconds
Started Jun 27 04:42:29 PM PDT 24
Finished Jun 27 04:42:34 PM PDT 24
Peak memory 205876 kb
Host smart-4c97e246-cf83-47ae-9828-73338cb1914c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617949276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1617949276
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3367828505
Short name T678
Test name
Test status
Simulation time 538664747 ps
CPU time 2.31 seconds
Started Jun 27 04:42:29 PM PDT 24
Finished Jun 27 04:42:34 PM PDT 24
Peak memory 208064 kb
Host smart-86f3f8c9-1e22-4cc2-9300-300a2cb77616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367828505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3367828505
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3509327819
Short name T298
Test name
Test status
Simulation time 20096296 ps
CPU time 1.01 seconds
Started Jun 27 04:42:24 PM PDT 24
Finished Jun 27 04:42:28 PM PDT 24
Peak memory 207808 kb
Host smart-13e968c1-793f-4108-a9b3-812e390f1688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509327819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3509327819
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2058656056
Short name T1017
Test name
Test status
Simulation time 22278051 ps
CPU time 0.82 seconds
Started Jun 27 04:42:28 PM PDT 24
Finished Jun 27 04:42:31 PM PDT 24
Peak memory 205804 kb
Host smart-c8596c17-aef4-432d-808d-c3629ed396eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058656056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2058656056
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3172633181
Short name T649
Test name
Test status
Simulation time 11235365464 ps
CPU time 32.57 seconds
Started Jun 27 04:42:28 PM PDT 24
Finished Jun 27 04:43:03 PM PDT 24
Peak memory 232736 kb
Host smart-957cfcf3-ff05-447b-9b03-b7d9367f5b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172633181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3172633181
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1883328990
Short name T656
Test name
Test status
Simulation time 34788249 ps
CPU time 0.71 seconds
Started Jun 27 04:42:38 PM PDT 24
Finished Jun 27 04:42:40 PM PDT 24
Peak memory 204652 kb
Host smart-f46d777c-6f70-4521-a2e4-41c8ce0f238c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883328990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1883328990
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.606934189
Short name T402
Test name
Test status
Simulation time 663454532 ps
CPU time 2.77 seconds
Started Jun 27 04:42:41 PM PDT 24
Finished Jun 27 04:42:47 PM PDT 24
Peak memory 232524 kb
Host smart-4a1a571c-085e-4236-8dee-d84df94eb1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606934189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.606934189
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1742611564
Short name T904
Test name
Test status
Simulation time 73334757 ps
CPU time 0.78 seconds
Started Jun 27 04:42:41 PM PDT 24
Finished Jun 27 04:42:44 PM PDT 24
Peak memory 206456 kb
Host smart-5db13dd2-c9b9-4f9a-838f-f693aa49629d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742611564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1742611564
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2383453542
Short name T414
Test name
Test status
Simulation time 46300698241 ps
CPU time 157.62 seconds
Started Jun 27 04:42:44 PM PDT 24
Finished Jun 27 04:45:28 PM PDT 24
Peak memory 249052 kb
Host smart-53cb5477-6a57-4638-bfd8-9aceff3de5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383453542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2383453542
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.4079833641
Short name T784
Test name
Test status
Simulation time 12541385017 ps
CPU time 150.56 seconds
Started Jun 27 04:42:42 PM PDT 24
Finished Jun 27 04:45:16 PM PDT 24
Peak memory 255648 kb
Host smart-6ed3fd82-e136-4946-bd73-be64ddffbba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079833641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.4079833641
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1144145357
Short name T746
Test name
Test status
Simulation time 12909937417 ps
CPU time 107.03 seconds
Started Jun 27 04:42:43 PM PDT 24
Finished Jun 27 04:44:36 PM PDT 24
Peak memory 263200 kb
Host smart-d0538f28-06e2-4424-a559-a678266b403a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144145357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1144145357
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3866226796
Short name T546
Test name
Test status
Simulation time 6734416016 ps
CPU time 66.82 seconds
Started Jun 27 04:42:39 PM PDT 24
Finished Jun 27 04:43:47 PM PDT 24
Peak memory 257016 kb
Host smart-eb26d0d4-9420-4fa3-9647-172fb662244b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866226796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3866226796
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3899116194
Short name T349
Test name
Test status
Simulation time 70897348 ps
CPU time 2.04 seconds
Started Jun 27 04:42:42 PM PDT 24
Finished Jun 27 04:42:47 PM PDT 24
Peak memory 222912 kb
Host smart-00770d32-becc-4ce5-88fe-72c8840d5121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899116194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3899116194
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.142860879
Short name T936
Test name
Test status
Simulation time 95216836 ps
CPU time 2.59 seconds
Started Jun 27 04:42:38 PM PDT 24
Finished Jun 27 04:42:43 PM PDT 24
Peak memory 232296 kb
Host smart-f550174c-75db-43e4-87ef-6b0f87992f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142860879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.142860879
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2625729672
Short name T210
Test name
Test status
Simulation time 25322449939 ps
CPU time 13.9 seconds
Started Jun 27 04:42:41 PM PDT 24
Finished Jun 27 04:42:57 PM PDT 24
Peak memory 232636 kb
Host smart-3e2b955b-b3f7-4d3e-9dc6-19db2a456c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625729672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2625729672
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3827353753
Short name T192
Test name
Test status
Simulation time 4603502272 ps
CPU time 8.96 seconds
Started Jun 27 04:42:43 PM PDT 24
Finished Jun 27 04:42:56 PM PDT 24
Peak memory 224780 kb
Host smart-b37307ee-e5c9-4a10-b032-68b6f2baa60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827353753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3827353753
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1335058580
Short name T145
Test name
Test status
Simulation time 1966438988 ps
CPU time 21.59 seconds
Started Jun 27 04:42:40 PM PDT 24
Finished Jun 27 04:43:03 PM PDT 24
Peak memory 222052 kb
Host smart-893c6d03-93fb-4e45-b7e2-60000ee2d71b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1335058580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1335058580
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3662104316
Short name T281
Test name
Test status
Simulation time 4950039180 ps
CPU time 4.93 seconds
Started Jun 27 04:42:38 PM PDT 24
Finished Jun 27 04:42:51 PM PDT 24
Peak memory 217468 kb
Host smart-3051b0ec-9c9c-46b4-92f5-fcce82c28168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662104316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3662104316
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.939145257
Short name T847
Test name
Test status
Simulation time 1311689090 ps
CPU time 7.61 seconds
Started Jun 27 04:42:44 PM PDT 24
Finished Jun 27 04:42:57 PM PDT 24
Peak memory 216048 kb
Host smart-64b59b9d-a322-4bb8-b29c-46450cccfbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939145257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.939145257
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.89826032
Short name T735
Test name
Test status
Simulation time 29258271 ps
CPU time 0.93 seconds
Started Jun 27 04:42:43 PM PDT 24
Finished Jun 27 04:42:47 PM PDT 24
Peak memory 206852 kb
Host smart-8b1bf5ce-f03c-4923-9a3e-5a0039432888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89826032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.89826032
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.411949372
Short name T364
Test name
Test status
Simulation time 91943359 ps
CPU time 0.84 seconds
Started Jun 27 04:42:45 PM PDT 24
Finished Jun 27 04:42:53 PM PDT 24
Peak memory 205768 kb
Host smart-f7174115-dd79-4ec9-8ad5-3a96a664f1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411949372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.411949372
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1329740248
Short name T229
Test name
Test status
Simulation time 789104214 ps
CPU time 10.25 seconds
Started Jun 27 04:42:40 PM PDT 24
Finished Jun 27 04:42:52 PM PDT 24
Peak memory 252032 kb
Host smart-9ba353f6-9849-4b17-bd8c-d9ef8a94f149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329740248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1329740248
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.178180558
Short name T413
Test name
Test status
Simulation time 15325539 ps
CPU time 0.7 seconds
Started Jun 27 04:42:41 PM PDT 24
Finished Jun 27 04:42:44 PM PDT 24
Peak memory 205636 kb
Host smart-52afe1c5-cfae-44ee-ae22-2943fbf6948a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178180558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.178180558
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.154991380
Short name T549
Test name
Test status
Simulation time 1093138678 ps
CPU time 11.68 seconds
Started Jun 27 04:42:43 PM PDT 24
Finished Jun 27 04:43:00 PM PDT 24
Peak memory 232524 kb
Host smart-bc0e3919-fa26-4f15-80ea-7fe55e0009be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154991380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.154991380
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2839651107
Short name T641
Test name
Test status
Simulation time 16136455 ps
CPU time 0.76 seconds
Started Jun 27 04:42:43 PM PDT 24
Finished Jun 27 04:42:49 PM PDT 24
Peak memory 205452 kb
Host smart-6c51188d-2c41-4959-9c4c-62a0da32c667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839651107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2839651107
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1550642594
Short name T536
Test name
Test status
Simulation time 2227295394 ps
CPU time 22.91 seconds
Started Jun 27 04:42:44 PM PDT 24
Finished Jun 27 04:43:13 PM PDT 24
Peak memory 236808 kb
Host smart-3a9c233d-0375-44e7-a3cb-7214e0dc8dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550642594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1550642594
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3902524912
Short name T81
Test name
Test status
Simulation time 28039431734 ps
CPU time 64.51 seconds
Started Jun 27 04:42:43 PM PDT 24
Finished Jun 27 04:43:53 PM PDT 24
Peak memory 256244 kb
Host smart-ec424cec-379f-435f-a4d2-8e2876c70c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902524912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3902524912
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3956336421
Short name T892
Test name
Test status
Simulation time 41659443819 ps
CPU time 100.91 seconds
Started Jun 27 04:42:41 PM PDT 24
Finished Jun 27 04:44:24 PM PDT 24
Peak memory 255192 kb
Host smart-11c34fc3-e005-4fde-8ac4-6193c7537e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956336421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3956336421
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2824492976
Short name T895
Test name
Test status
Simulation time 1999514580 ps
CPU time 7.06 seconds
Started Jun 27 04:42:48 PM PDT 24
Finished Jun 27 04:43:02 PM PDT 24
Peak memory 224388 kb
Host smart-75da8354-2f86-4e93-b45f-f66530ec1e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824492976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2824492976
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.4149051802
Short name T245
Test name
Test status
Simulation time 10928883600 ps
CPU time 91.97 seconds
Started Jun 27 04:42:44 PM PDT 24
Finished Jun 27 04:44:22 PM PDT 24
Peak memory 249532 kb
Host smart-ee256193-568c-4d48-a73e-1ec30a025106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149051802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.4149051802
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3416780603
Short name T12
Test name
Test status
Simulation time 6681119954 ps
CPU time 12.68 seconds
Started Jun 27 04:42:45 PM PDT 24
Finished Jun 27 04:43:05 PM PDT 24
Peak memory 224432 kb
Host smart-7056e097-6864-4683-a4d2-e4ef6aae2a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416780603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3416780603
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1476236079
Short name T730
Test name
Test status
Simulation time 926671049 ps
CPU time 5.17 seconds
Started Jun 27 04:42:41 PM PDT 24
Finished Jun 27 04:42:48 PM PDT 24
Peak memory 224276 kb
Host smart-8eefb239-d1a0-4cc8-979c-c82fb592a402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476236079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1476236079
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1575243806
Short name T955
Test name
Test status
Simulation time 20796553559 ps
CPU time 16.29 seconds
Started Jun 27 04:42:42 PM PDT 24
Finished Jun 27 04:43:02 PM PDT 24
Peak memory 224808 kb
Host smart-d5ed04f0-ca40-49bf-a0b5-ceffac175fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575243806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1575243806
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3094246670
Short name T633
Test name
Test status
Simulation time 2122296019 ps
CPU time 6.85 seconds
Started Jun 27 04:42:40 PM PDT 24
Finished Jun 27 04:42:48 PM PDT 24
Peak memory 224300 kb
Host smart-667ee879-5440-416b-91a0-19564ed753f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094246670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3094246670
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1657535186
Short name T146
Test name
Test status
Simulation time 1288298467 ps
CPU time 10.56 seconds
Started Jun 27 04:42:39 PM PDT 24
Finished Jun 27 04:42:52 PM PDT 24
Peak memory 222252 kb
Host smart-8cb14a2a-9107-4899-976f-9e2027a4f0e9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1657535186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1657535186
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3441074103
Short name T663
Test name
Test status
Simulation time 7357791358 ps
CPU time 28.63 seconds
Started Jun 27 04:42:51 PM PDT 24
Finished Jun 27 04:43:25 PM PDT 24
Peak memory 216208 kb
Host smart-99f45508-bfd3-4f4c-94d1-78f40582c769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441074103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3441074103
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2792238341
Short name T380
Test name
Test status
Simulation time 15929191539 ps
CPU time 22.62 seconds
Started Jun 27 04:42:45 PM PDT 24
Finished Jun 27 04:43:13 PM PDT 24
Peak memory 216288 kb
Host smart-3c1b9444-0831-47de-8cab-32178be834a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792238341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2792238341
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3771070654
Short name T379
Test name
Test status
Simulation time 24860190 ps
CPU time 0.8 seconds
Started Jun 27 04:42:41 PM PDT 24
Finished Jun 27 04:42:45 PM PDT 24
Peak memory 205808 kb
Host smart-87afef8b-ad9b-4c87-85ab-2f7946a7518f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771070654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3771070654
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1842518363
Short name T925
Test name
Test status
Simulation time 361716996 ps
CPU time 0.94 seconds
Started Jun 27 04:42:46 PM PDT 24
Finished Jun 27 04:42:53 PM PDT 24
Peak memory 206496 kb
Host smart-61a03a58-f3ea-4e9b-a240-e1ef13cfdaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842518363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1842518363
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1841249585
Short name T776
Test name
Test status
Simulation time 1653704145 ps
CPU time 3.12 seconds
Started Jun 27 04:42:44 PM PDT 24
Finished Jun 27 04:42:53 PM PDT 24
Peak memory 232496 kb
Host smart-45517b81-9558-4969-9bb1-44e7eca8956a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841249585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1841249585
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.4134035572
Short name T1015
Test name
Test status
Simulation time 17484800 ps
CPU time 0.71 seconds
Started Jun 27 04:42:44 PM PDT 24
Finished Jun 27 04:42:51 PM PDT 24
Peak memory 204692 kb
Host smart-6005d1f5-5e9f-442c-99a7-dbed828fd865
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134035572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
4134035572
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2801636522
Short name T798
Test name
Test status
Simulation time 412170437 ps
CPU time 2.21 seconds
Started Jun 27 04:42:41 PM PDT 24
Finished Jun 27 04:42:46 PM PDT 24
Peak memory 223024 kb
Host smart-0176a4a8-86aa-489e-808b-f6577c638590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801636522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2801636522
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3551365814
Short name T554
Test name
Test status
Simulation time 20937721 ps
CPU time 0.81 seconds
Started Jun 27 04:42:45 PM PDT 24
Finished Jun 27 04:42:53 PM PDT 24
Peak memory 206408 kb
Host smart-07c5b02c-5b9f-46d2-ae74-4712a017d875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551365814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3551365814
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.83132862
Short name T135
Test name
Test status
Simulation time 2774121829 ps
CPU time 68.91 seconds
Started Jun 27 04:42:38 PM PDT 24
Finished Jun 27 04:43:48 PM PDT 24
Peak memory 249528 kb
Host smart-586a9824-133e-4bd2-b645-74b549acb4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83132862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.83132862
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1175086027
Short name T711
Test name
Test status
Simulation time 99678516837 ps
CPU time 212.15 seconds
Started Jun 27 04:42:45 PM PDT 24
Finished Jun 27 04:46:23 PM PDT 24
Peak memory 253880 kb
Host smart-92e3a6af-0e57-4763-8fed-72e251ac173e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175086027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1175086027
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2007527887
Short name T686
Test name
Test status
Simulation time 5271964121 ps
CPU time 17.07 seconds
Started Jun 27 04:42:42 PM PDT 24
Finished Jun 27 04:43:03 PM PDT 24
Peak memory 232632 kb
Host smart-c81813ff-2213-45ad-80e8-8d3fb6875b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007527887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2007527887
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2715139656
Short name T876
Test name
Test status
Simulation time 129718799271 ps
CPU time 223.07 seconds
Started Jun 27 04:42:48 PM PDT 24
Finished Jun 27 04:46:37 PM PDT 24
Peak memory 250060 kb
Host smart-f558cd95-b71f-42a7-8822-fa0edbcd3ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715139656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2715139656
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.481977545
Short name T570
Test name
Test status
Simulation time 7997014107 ps
CPU time 23.85 seconds
Started Jun 27 04:42:46 PM PDT 24
Finished Jun 27 04:43:16 PM PDT 24
Peak memory 232392 kb
Host smart-bb5eb6cc-db4b-476e-aebb-fc903c04efb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481977545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.481977545
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1219575735
Short name T564
Test name
Test status
Simulation time 14111204895 ps
CPU time 119.24 seconds
Started Jun 27 04:42:43 PM PDT 24
Finished Jun 27 04:44:48 PM PDT 24
Peak memory 235212 kb
Host smart-e6ecb9fc-cb50-49b0-acd9-ac38c773e8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219575735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1219575735
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2142443727
Short name T8
Test name
Test status
Simulation time 3150845135 ps
CPU time 10.05 seconds
Started Jun 27 04:42:48 PM PDT 24
Finished Jun 27 04:43:04 PM PDT 24
Peak memory 224476 kb
Host smart-72628609-f067-4c7d-b4df-491ae3d2f348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142443727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2142443727
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.807517701
Short name T541
Test name
Test status
Simulation time 1994387781 ps
CPU time 4.25 seconds
Started Jun 27 04:42:45 PM PDT 24
Finished Jun 27 04:42:56 PM PDT 24
Peak memory 224416 kb
Host smart-c95cc30b-0dfa-4d87-8924-c08221a11296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807517701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.807517701
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.566102828
Short name T878
Test name
Test status
Simulation time 1054059377 ps
CPU time 6.46 seconds
Started Jun 27 04:42:43 PM PDT 24
Finished Jun 27 04:42:54 PM PDT 24
Peak memory 220416 kb
Host smart-6bca3701-dc06-4497-b7c8-57d502b944d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=566102828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.566102828
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3186703907
Short name T291
Test name
Test status
Simulation time 7162333355 ps
CPU time 30.31 seconds
Started Jun 27 04:42:41 PM PDT 24
Finished Jun 27 04:43:14 PM PDT 24
Peak memory 216168 kb
Host smart-0f8989e3-b549-4c67-9ef8-e409c3fd333a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186703907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3186703907
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.307763025
Short name T563
Test name
Test status
Simulation time 998608647 ps
CPU time 2.17 seconds
Started Jun 27 04:42:43 PM PDT 24
Finished Jun 27 04:42:50 PM PDT 24
Peak memory 207376 kb
Host smart-e5aa1db8-170d-4c50-80d4-cd7b36a8a3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307763025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.307763025
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1121625709
Short name T341
Test name
Test status
Simulation time 52308671 ps
CPU time 1.23 seconds
Started Jun 27 04:42:43 PM PDT 24
Finished Jun 27 04:42:49 PM PDT 24
Peak memory 207560 kb
Host smart-f378181e-f6c3-41bc-8655-403939ffbf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121625709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1121625709
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.706345763
Short name T348
Test name
Test status
Simulation time 40785310 ps
CPU time 0.7 seconds
Started Jun 27 04:42:51 PM PDT 24
Finished Jun 27 04:42:57 PM PDT 24
Peak memory 205756 kb
Host smart-b403d416-55d4-44e8-ab6b-aea3686dda9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706345763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.706345763
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.4131400787
Short name T420
Test name
Test status
Simulation time 1835995760 ps
CPU time 6.91 seconds
Started Jun 27 04:42:44 PM PDT 24
Finished Jun 27 04:42:56 PM PDT 24
Peak memory 224268 kb
Host smart-43920ff7-4c69-4e33-b15e-800cb404efe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131400787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.4131400787
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.4217001923
Short name T374
Test name
Test status
Simulation time 46546204 ps
CPU time 0.72 seconds
Started Jun 27 04:42:52 PM PDT 24
Finished Jun 27 04:42:57 PM PDT 24
Peak memory 205264 kb
Host smart-7e58ff23-7add-49b6-bc6c-19e6dc50eb25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217001923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
4217001923
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.4181619968
Short name T618
Test name
Test status
Simulation time 5318396320 ps
CPU time 15.03 seconds
Started Jun 27 04:42:55 PM PDT 24
Finished Jun 27 04:43:13 PM PDT 24
Peak memory 233016 kb
Host smart-a83c79ec-a2a1-44c8-8a43-ce165b0892f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181619968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.4181619968
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3916084085
Short name T322
Test name
Test status
Simulation time 65571108 ps
CPU time 0.75 seconds
Started Jun 27 04:42:49 PM PDT 24
Finished Jun 27 04:42:55 PM PDT 24
Peak memory 206432 kb
Host smart-1b766154-ca7a-4763-b1cf-fcd684b7372d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916084085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3916084085
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3917888413
Short name T976
Test name
Test status
Simulation time 163636190290 ps
CPU time 354.19 seconds
Started Jun 27 04:42:51 PM PDT 24
Finished Jun 27 04:48:51 PM PDT 24
Peak memory 252164 kb
Host smart-bb3835b9-15eb-4d0b-ad3e-d57b5e89a934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917888413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3917888413
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.4004762843
Short name T529
Test name
Test status
Simulation time 2706800859 ps
CPU time 12.33 seconds
Started Jun 27 04:42:45 PM PDT 24
Finished Jun 27 04:43:05 PM PDT 24
Peak memory 233448 kb
Host smart-d9001082-2ac3-4713-a26f-ffdeec311fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004762843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.4004762843
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2096827718
Short name T1020
Test name
Test status
Simulation time 324876371 ps
CPU time 7.49 seconds
Started Jun 27 04:42:55 PM PDT 24
Finished Jun 27 04:43:06 PM PDT 24
Peak memory 238216 kb
Host smart-8485a8fc-a54d-4eda-a868-6d21326502d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096827718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.2096827718
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.696301874
Short name T193
Test name
Test status
Simulation time 1268101597 ps
CPU time 14.67 seconds
Started Jun 27 04:43:04 PM PDT 24
Finished Jun 27 04:43:23 PM PDT 24
Peak memory 224348 kb
Host smart-3be31d4b-e85a-487c-88c4-b713b7700a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696301874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.696301874
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2899224134
Short name T304
Test name
Test status
Simulation time 8677544040 ps
CPU time 16.6 seconds
Started Jun 27 04:42:45 PM PDT 24
Finished Jun 27 04:43:09 PM PDT 24
Peak memory 239468 kb
Host smart-b8192238-4518-40eb-83f1-4c43d8dd564b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899224134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2899224134
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.646740719
Short name T386
Test name
Test status
Simulation time 188860910 ps
CPU time 2.6 seconds
Started Jun 27 04:42:46 PM PDT 24
Finished Jun 27 04:42:55 PM PDT 24
Peak memory 224332 kb
Host smart-0f55277f-e2e6-4990-8231-457308ca35e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646740719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.646740719
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.4220742386
Short name T599
Test name
Test status
Simulation time 736517643 ps
CPU time 5.5 seconds
Started Jun 27 04:42:45 PM PDT 24
Finished Jun 27 04:42:58 PM PDT 24
Peak memory 232576 kb
Host smart-186dd916-b547-431a-932d-748bdbf54266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220742386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.4220742386
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.4271620125
Short name T430
Test name
Test status
Simulation time 313218552 ps
CPU time 3.77 seconds
Started Jun 27 04:42:50 PM PDT 24
Finished Jun 27 04:42:59 PM PDT 24
Peak memory 221612 kb
Host smart-0d51c82e-2965-4d8d-a975-95672d81ba72
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4271620125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.4271620125
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1901416731
Short name T557
Test name
Test status
Simulation time 215912261 ps
CPU time 1.06 seconds
Started Jun 27 04:42:45 PM PDT 24
Finished Jun 27 04:42:51 PM PDT 24
Peak memory 206852 kb
Host smart-9808e3dc-2958-4929-ad78-7b761ceeaf8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901416731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1901416731
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.621069005
Short name T511
Test name
Test status
Simulation time 12528767 ps
CPU time 0.74 seconds
Started Jun 27 04:42:44 PM PDT 24
Finished Jun 27 04:42:51 PM PDT 24
Peak memory 205540 kb
Host smart-7a773ecf-542a-4ab4-9251-015daf736b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621069005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.621069005
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.840484333
Short name T369
Test name
Test status
Simulation time 30869816317 ps
CPU time 9.61 seconds
Started Jun 27 04:42:44 PM PDT 24
Finished Jun 27 04:43:00 PM PDT 24
Peak memory 216168 kb
Host smart-93d38075-d4c2-4e60-85c1-0ee561b2b614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840484333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.840484333
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2204976205
Short name T350
Test name
Test status
Simulation time 676948836 ps
CPU time 1.98 seconds
Started Jun 27 04:42:44 PM PDT 24
Finished Jun 27 04:42:52 PM PDT 24
Peak memory 216044 kb
Host smart-b2dd11a5-0c36-4a0f-93b3-9bf1d5458362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204976205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2204976205
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2779695264
Short name T999
Test name
Test status
Simulation time 21559573 ps
CPU time 0.66 seconds
Started Jun 27 04:42:47 PM PDT 24
Finished Jun 27 04:42:54 PM PDT 24
Peak memory 205476 kb
Host smart-bd4e75bd-b176-4a3f-a6a0-23e5118b2d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779695264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2779695264
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1463008594
Short name T300
Test name
Test status
Simulation time 146062057 ps
CPU time 2.69 seconds
Started Jun 27 04:42:50 PM PDT 24
Finished Jun 27 04:42:58 PM PDT 24
Peak memory 224400 kb
Host smart-b798ecbf-7ac0-454c-b8a4-e2477e8db5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463008594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1463008594
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.274531469
Short name T868
Test name
Test status
Simulation time 26204141 ps
CPU time 0.71 seconds
Started Jun 27 04:42:50 PM PDT 24
Finished Jun 27 04:42:56 PM PDT 24
Peak memory 204756 kb
Host smart-0ff9070d-7eac-4c77-bf1a-fa28bda26ddc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274531469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.274531469
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1178890913
Short name T461
Test name
Test status
Simulation time 264779592 ps
CPU time 2.99 seconds
Started Jun 27 04:42:49 PM PDT 24
Finished Jun 27 04:42:58 PM PDT 24
Peak memory 232588 kb
Host smart-bc946c98-84ad-4205-b58b-340597bc25c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178890913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1178890913
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1171624437
Short name T499
Test name
Test status
Simulation time 118250730 ps
CPU time 0.79 seconds
Started Jun 27 04:42:45 PM PDT 24
Finished Jun 27 04:42:53 PM PDT 24
Peak memory 206352 kb
Host smart-6aa4d7ae-7b91-402e-8d65-11ba15c89126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171624437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1171624437
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1177269684
Short name T129
Test name
Test status
Simulation time 8436444678 ps
CPU time 50.29 seconds
Started Jun 27 04:42:50 PM PDT 24
Finished Jun 27 04:43:46 PM PDT 24
Peak memory 249904 kb
Host smart-6adf6963-3f3e-48cd-8053-b7f01a9f1482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177269684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1177269684
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1995220017
Short name T965
Test name
Test status
Simulation time 11575693218 ps
CPU time 75.79 seconds
Started Jun 27 04:42:47 PM PDT 24
Finished Jun 27 04:44:09 PM PDT 24
Peak memory 253488 kb
Host smart-e0232ba8-150e-448e-b10e-0d853587d222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995220017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1995220017
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1559428537
Short name T1007
Test name
Test status
Simulation time 19808253819 ps
CPU time 137.34 seconds
Started Jun 27 04:42:54 PM PDT 24
Finished Jun 27 04:45:15 PM PDT 24
Peak memory 266732 kb
Host smart-3f307d39-f45c-4c30-87e0-638edac1ed06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559428537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1559428537
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2651989966
Short name T768
Test name
Test status
Simulation time 4677118188 ps
CPU time 20.44 seconds
Started Jun 27 04:42:49 PM PDT 24
Finished Jun 27 04:43:15 PM PDT 24
Peak memory 239104 kb
Host smart-b3ad621d-983f-467f-b92e-ea0610a2f45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651989966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2651989966
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.2954349504
Short name T194
Test name
Test status
Simulation time 6774746915 ps
CPU time 87.79 seconds
Started Jun 27 04:42:56 PM PDT 24
Finished Jun 27 04:44:27 PM PDT 24
Peak memory 248400 kb
Host smart-59524f8b-7baa-4e49-ad00-a70d86b9c6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954349504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.2954349504
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.838163582
Short name T214
Test name
Test status
Simulation time 313213388 ps
CPU time 2.73 seconds
Started Jun 27 04:42:47 PM PDT 24
Finished Jun 27 04:42:56 PM PDT 24
Peak memory 224360 kb
Host smart-7b1c4dbd-b4de-4514-be06-3ccccff81d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838163582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.838163582
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2303944002
Short name T560
Test name
Test status
Simulation time 47990239743 ps
CPU time 83.42 seconds
Started Jun 27 04:42:45 PM PDT 24
Finished Jun 27 04:44:16 PM PDT 24
Peak memory 224476 kb
Host smart-b655a3cf-c343-4684-84c3-639c73346f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303944002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2303944002
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1808759509
Short name T460
Test name
Test status
Simulation time 2724791629 ps
CPU time 4.04 seconds
Started Jun 27 04:42:41 PM PDT 24
Finished Jun 27 04:42:47 PM PDT 24
Peak memory 232552 kb
Host smart-67eadac3-c3dc-4f6d-becb-454f3b7f2455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808759509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1808759509
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2565622257
Short name T59
Test name
Test status
Simulation time 3346546576 ps
CPU time 5.74 seconds
Started Jun 27 04:42:49 PM PDT 24
Finished Jun 27 04:43:00 PM PDT 24
Peak memory 224388 kb
Host smart-f7c157ca-e64d-4b13-9dc6-3b3eb7e0477e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565622257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2565622257
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.497067779
Short name T619
Test name
Test status
Simulation time 6663572385 ps
CPU time 12.98 seconds
Started Jun 27 04:42:50 PM PDT 24
Finished Jun 27 04:43:09 PM PDT 24
Peak memory 220692 kb
Host smart-8a6dfc12-d7be-4e37-bcfb-8db5ba2e7ad6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=497067779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.497067779
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3880099582
Short name T908
Test name
Test status
Simulation time 115426174 ps
CPU time 1.05 seconds
Started Jun 27 04:42:53 PM PDT 24
Finished Jun 27 04:42:58 PM PDT 24
Peak memory 206948 kb
Host smart-96621bac-7e93-48a9-bd13-80232f35f0ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880099582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3880099582
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.913251513
Short name T985
Test name
Test status
Simulation time 7661470207 ps
CPU time 26.33 seconds
Started Jun 27 04:42:42 PM PDT 24
Finished Jun 27 04:43:12 PM PDT 24
Peak memory 216264 kb
Host smart-a41281cf-5370-429a-a1b8-847268ebfd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913251513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.913251513
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3329120034
Short name T452
Test name
Test status
Simulation time 1260048660 ps
CPU time 7.41 seconds
Started Jun 27 04:42:52 PM PDT 24
Finished Jun 27 04:43:04 PM PDT 24
Peak memory 216016 kb
Host smart-f99b8f68-3e12-4fb9-9067-3c96c6502200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329120034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3329120034
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.757576089
Short name T296
Test name
Test status
Simulation time 917575402 ps
CPU time 1.65 seconds
Started Jun 27 04:42:54 PM PDT 24
Finished Jun 27 04:43:00 PM PDT 24
Peak memory 216040 kb
Host smart-ad273be3-fb61-4c33-8be0-3b4603980c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757576089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.757576089
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2514997166
Short name T577
Test name
Test status
Simulation time 34043448 ps
CPU time 0.69 seconds
Started Jun 27 04:42:45 PM PDT 24
Finished Jun 27 04:42:51 PM PDT 24
Peak memory 205376 kb
Host smart-157fecf0-3939-45d3-b04b-6068d2ac3465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514997166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2514997166
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3030515771
Short name T821
Test name
Test status
Simulation time 170858403 ps
CPU time 4.26 seconds
Started Jun 27 04:42:47 PM PDT 24
Finished Jun 27 04:42:58 PM PDT 24
Peak memory 232568 kb
Host smart-e5a9b4e1-f5d7-446a-aa34-14ab05b838e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030515771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3030515771
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1616233983
Short name T410
Test name
Test status
Simulation time 44858973 ps
CPU time 0.74 seconds
Started Jun 27 04:43:05 PM PDT 24
Finished Jun 27 04:43:11 PM PDT 24
Peak memory 205608 kb
Host smart-42799692-58de-4d58-8139-a815924c893a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616233983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1616233983
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1221005787
Short name T415
Test name
Test status
Simulation time 250851632 ps
CPU time 4.23 seconds
Started Jun 27 04:42:46 PM PDT 24
Finished Jun 27 04:42:57 PM PDT 24
Peak memory 224340 kb
Host smart-0f6e980f-f4a1-4fc8-a620-52b89a831a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221005787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1221005787
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3608972431
Short name T309
Test name
Test status
Simulation time 54643483 ps
CPU time 0.78 seconds
Started Jun 27 04:42:52 PM PDT 24
Finished Jun 27 04:42:58 PM PDT 24
Peak memory 205788 kb
Host smart-83a69e16-c601-4523-9350-99103529b759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608972431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3608972431
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3454926353
Short name T760
Test name
Test status
Simulation time 73920423475 ps
CPU time 123.73 seconds
Started Jun 27 04:42:45 PM PDT 24
Finished Jun 27 04:44:54 PM PDT 24
Peak memory 249080 kb
Host smart-ae3200d9-f68e-4b82-87ea-c64ef7feb37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454926353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3454926353
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3935887774
Short name T453
Test name
Test status
Simulation time 11893490554 ps
CPU time 33.75 seconds
Started Jun 27 04:42:42 PM PDT 24
Finished Jun 27 04:43:20 PM PDT 24
Peak memory 224352 kb
Host smart-ebec3a53-00f8-4f49-b9d1-2f5b4cf21e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935887774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3935887774
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3538069484
Short name T375
Test name
Test status
Simulation time 2364157796 ps
CPU time 20.48 seconds
Started Jun 27 04:42:48 PM PDT 24
Finished Jun 27 04:43:15 PM PDT 24
Peak memory 224468 kb
Host smart-d406ba48-051c-44c4-bece-6be8472e4e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538069484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3538069484
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1676217363
Short name T731
Test name
Test status
Simulation time 485359516 ps
CPU time 2.97 seconds
Started Jun 27 04:42:44 PM PDT 24
Finished Jun 27 04:42:53 PM PDT 24
Peak memory 224324 kb
Host smart-79690c88-17d8-4688-8fed-ee0c064bee5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676217363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1676217363
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.303760719
Short name T502
Test name
Test status
Simulation time 107000550 ps
CPU time 3.67 seconds
Started Jun 27 04:42:39 PM PDT 24
Finished Jun 27 04:42:45 PM PDT 24
Peak memory 234096 kb
Host smart-5ed8a101-f3f4-4169-9763-8faef7ce9f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303760719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds
.303760719
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.799285846
Short name T685
Test name
Test status
Simulation time 194346243 ps
CPU time 6.33 seconds
Started Jun 27 04:42:47 PM PDT 24
Finished Jun 27 04:43:00 PM PDT 24
Peak memory 232564 kb
Host smart-fd5cbf5b-5250-48b2-935b-146f7b5af171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799285846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.799285846
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.699048349
Short name T78
Test name
Test status
Simulation time 3076305249 ps
CPU time 16.24 seconds
Started Jun 27 04:42:48 PM PDT 24
Finished Jun 27 04:43:10 PM PDT 24
Peak memory 240496 kb
Host smart-acabd865-021e-4052-b99a-26c4c9b3b61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699048349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.699048349
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1356947167
Short name T933
Test name
Test status
Simulation time 130083602 ps
CPU time 2.61 seconds
Started Jun 27 04:42:48 PM PDT 24
Finished Jun 27 04:42:56 PM PDT 24
Peak memory 232580 kb
Host smart-babee578-96a3-46eb-bdc7-22727e4484b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356947167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1356947167
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2566989197
Short name T333
Test name
Test status
Simulation time 2897874563 ps
CPU time 9.03 seconds
Started Jun 27 04:42:51 PM PDT 24
Finished Jun 27 04:43:05 PM PDT 24
Peak memory 224428 kb
Host smart-2332b107-127c-4f21-a1aa-b7770675013f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566989197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2566989197
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3351259118
Short name T522
Test name
Test status
Simulation time 501039528 ps
CPU time 7.68 seconds
Started Jun 27 04:42:45 PM PDT 24
Finished Jun 27 04:43:00 PM PDT 24
Peak memory 220448 kb
Host smart-5cc5f89b-3f2e-4406-bf4b-92ccb02be903
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3351259118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3351259118
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2695935629
Short name T1008
Test name
Test status
Simulation time 13437427698 ps
CPU time 116.12 seconds
Started Jun 27 04:42:40 PM PDT 24
Finished Jun 27 04:44:38 PM PDT 24
Peak memory 273732 kb
Host smart-3fb775ed-d3b8-4a15-8f3a-6a6cf4c26e2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695935629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2695935629
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.804564448
Short name T886
Test name
Test status
Simulation time 25069752 ps
CPU time 0.74 seconds
Started Jun 27 04:42:45 PM PDT 24
Finished Jun 27 04:42:53 PM PDT 24
Peak memory 205620 kb
Host smart-3adeeae0-6553-42d5-a11e-792e1f9c120c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804564448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.804564448
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1796229524
Short name T314
Test name
Test status
Simulation time 6428512341 ps
CPU time 18.36 seconds
Started Jun 27 04:42:55 PM PDT 24
Finished Jun 27 04:43:16 PM PDT 24
Peak memory 216232 kb
Host smart-57b6fe97-3ea2-4b44-97de-b2eaeefc398c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796229524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1796229524
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1623894132
Short name T719
Test name
Test status
Simulation time 16870361 ps
CPU time 0.67 seconds
Started Jun 27 04:42:47 PM PDT 24
Finished Jun 27 04:42:54 PM PDT 24
Peak memory 205516 kb
Host smart-3e0162aa-c516-4a81-8877-af08d1abd8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623894132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1623894132
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.25017187
Short name T1016
Test name
Test status
Simulation time 21575252 ps
CPU time 0.77 seconds
Started Jun 27 04:42:48 PM PDT 24
Finished Jun 27 04:42:55 PM PDT 24
Peak memory 205748 kb
Host smart-d1c72707-726c-469c-8673-6c31de422bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25017187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.25017187
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2454541481
Short name T544
Test name
Test status
Simulation time 3685204743 ps
CPU time 8.93 seconds
Started Jun 27 04:42:40 PM PDT 24
Finished Jun 27 04:42:51 PM PDT 24
Peak memory 224496 kb
Host smart-6d24dbec-8f99-4c77-b3f4-e6e3c6d6240e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454541481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2454541481
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1391124086
Short name T68
Test name
Test status
Simulation time 12970328 ps
CPU time 0.67 seconds
Started Jun 27 04:42:59 PM PDT 24
Finished Jun 27 04:43:02 PM PDT 24
Peak memory 205652 kb
Host smart-b23ac4e8-0a77-4b95-94ba-4dc8b40d8845
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391124086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1391124086
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1222779816
Short name T372
Test name
Test status
Simulation time 2709378640 ps
CPU time 25.15 seconds
Started Jun 27 04:43:03 PM PDT 24
Finished Jun 27 04:43:33 PM PDT 24
Peak memory 232604 kb
Host smart-bd2c0647-2d35-4314-b44a-b11b2e923c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222779816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1222779816
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3917213576
Short name T432
Test name
Test status
Simulation time 62729103 ps
CPU time 0.77 seconds
Started Jun 27 04:43:02 PM PDT 24
Finished Jun 27 04:43:07 PM PDT 24
Peak memory 206420 kb
Host smart-555b30ce-0682-4253-8321-4b85afc8141b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917213576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3917213576
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3333388231
Short name T268
Test name
Test status
Simulation time 1285573064 ps
CPU time 24.55 seconds
Started Jun 27 04:42:59 PM PDT 24
Finished Jun 27 04:43:26 PM PDT 24
Peak memory 248952 kb
Host smart-6555a071-d041-4ceb-bda9-9d6bf4c18957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333388231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3333388231
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3964576587
Short name T288
Test name
Test status
Simulation time 2001067931 ps
CPU time 41.71 seconds
Started Jun 27 04:42:58 PM PDT 24
Finished Jun 27 04:43:42 PM PDT 24
Peak memory 249100 kb
Host smart-e89c77aa-496b-4f69-84da-3fb0dfffcf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964576587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3964576587
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3598655906
Short name T211
Test name
Test status
Simulation time 10844633603 ps
CPU time 37.67 seconds
Started Jun 27 04:42:58 PM PDT 24
Finished Jun 27 04:43:38 PM PDT 24
Peak memory 253692 kb
Host smart-beb5f1ef-17bf-49ef-be6a-de76027ac9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598655906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3598655906
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3350218934
Short name T2
Test name
Test status
Simulation time 114105105 ps
CPU time 3.42 seconds
Started Jun 27 04:42:56 PM PDT 24
Finished Jun 27 04:43:03 PM PDT 24
Peak memory 224360 kb
Host smart-c62eecb1-affb-4cac-abb1-46c7620bacec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350218934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3350218934
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.964156556
Short name T324
Test name
Test status
Simulation time 43969832 ps
CPU time 0.75 seconds
Started Jun 27 04:43:00 PM PDT 24
Finished Jun 27 04:43:04 PM PDT 24
Peak memory 215764 kb
Host smart-a837f642-91f2-4197-b6a4-c3d0236b5c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964156556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds
.964156556
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1122514137
Short name T80
Test name
Test status
Simulation time 201744275 ps
CPU time 3.02 seconds
Started Jun 27 04:43:03 PM PDT 24
Finished Jun 27 04:43:11 PM PDT 24
Peak memory 224296 kb
Host smart-0c913f82-6ebe-4406-aa38-d3895f6600d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122514137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1122514137
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.761705580
Short name T543
Test name
Test status
Simulation time 8849363475 ps
CPU time 76.78 seconds
Started Jun 27 04:43:00 PM PDT 24
Finished Jun 27 04:44:20 PM PDT 24
Peak memory 232680 kb
Host smart-7ad74795-f1c9-4a14-b879-3b9c32ef6fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761705580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.761705580
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1696946202
Short name T249
Test name
Test status
Simulation time 598028383 ps
CPU time 4.39 seconds
Started Jun 27 04:42:57 PM PDT 24
Finished Jun 27 04:43:04 PM PDT 24
Peak memory 224384 kb
Host smart-59136bfc-3ed0-41ec-8633-f64212bb0724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696946202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1696946202
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2085477438
Short name T632
Test name
Test status
Simulation time 2382971705 ps
CPU time 9.23 seconds
Started Jun 27 04:42:57 PM PDT 24
Finished Jun 27 04:43:09 PM PDT 24
Peak memory 232716 kb
Host smart-5670a4f5-a2d9-4428-a471-1a0aacabc75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085477438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2085477438
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.982810583
Short name T767
Test name
Test status
Simulation time 303232520 ps
CPU time 6.22 seconds
Started Jun 27 04:43:02 PM PDT 24
Finished Jun 27 04:43:12 PM PDT 24
Peak memory 220872 kb
Host smart-b83af722-6223-45fd-8e47-88864e36a121
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=982810583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.982810583
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.4292483987
Short name T20
Test name
Test status
Simulation time 65558004 ps
CPU time 0.88 seconds
Started Jun 27 04:43:00 PM PDT 24
Finished Jun 27 04:43:03 PM PDT 24
Peak memory 206536 kb
Host smart-47bf05c8-a4b8-4ccd-8e6f-08845d284b57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292483987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.4292483987
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3051935981
Short name T290
Test name
Test status
Simulation time 23525419527 ps
CPU time 31.49 seconds
Started Jun 27 04:43:00 PM PDT 24
Finished Jun 27 04:43:34 PM PDT 24
Peak memory 216352 kb
Host smart-f46d0b20-c81e-485c-8a7b-2697dd70fcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051935981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3051935981
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2252876608
Short name T690
Test name
Test status
Simulation time 23137322163 ps
CPU time 15.62 seconds
Started Jun 27 04:42:58 PM PDT 24
Finished Jun 27 04:43:16 PM PDT 24
Peak memory 217228 kb
Host smart-6f022a8a-b654-4efa-9a62-4550ed6702ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252876608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2252876608
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2332673815
Short name T1002
Test name
Test status
Simulation time 407012323 ps
CPU time 3.7 seconds
Started Jun 27 04:43:05 PM PDT 24
Finished Jun 27 04:43:14 PM PDT 24
Peak memory 216044 kb
Host smart-47fd380c-9b94-433d-ad62-5f35e6c5c841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332673815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2332673815
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2570733649
Short name T362
Test name
Test status
Simulation time 37660537 ps
CPU time 0.84 seconds
Started Jun 27 04:43:02 PM PDT 24
Finished Jun 27 04:43:08 PM PDT 24
Peak memory 205708 kb
Host smart-eb0516a0-c5ce-4151-a548-5791115c6301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570733649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2570733649
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2409854954
Short name T715
Test name
Test status
Simulation time 9787419373 ps
CPU time 16.44 seconds
Started Jun 27 04:42:57 PM PDT 24
Finished Jun 27 04:43:16 PM PDT 24
Peak memory 232632 kb
Host smart-f1bd253e-4ebb-40c0-bb0b-04423a76e202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409854954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2409854954
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3403395976
Short name T984
Test name
Test status
Simulation time 50302701 ps
CPU time 0.75 seconds
Started Jun 27 04:41:38 PM PDT 24
Finished Jun 27 04:41:42 PM PDT 24
Peak memory 204676 kb
Host smart-f592470e-b88a-493c-9abd-59cae62862db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403395976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
403395976
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2158250955
Short name T476
Test name
Test status
Simulation time 1540574208 ps
CPU time 6.33 seconds
Started Jun 27 04:41:38 PM PDT 24
Finished Jun 27 04:41:47 PM PDT 24
Peak memory 232508 kb
Host smart-e99b7eb8-3af8-443c-8f5a-bcc7ba8a2d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158250955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2158250955
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1556755787
Short name T751
Test name
Test status
Simulation time 15360461 ps
CPU time 0.77 seconds
Started Jun 27 04:41:22 PM PDT 24
Finished Jun 27 04:41:27 PM PDT 24
Peak memory 205384 kb
Host smart-375ecce6-c29d-4c27-9c0c-b8664ab761a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556755787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1556755787
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1672178078
Short name T578
Test name
Test status
Simulation time 19048639195 ps
CPU time 148.29 seconds
Started Jun 27 04:41:38 PM PDT 24
Finished Jun 27 04:44:10 PM PDT 24
Peak memory 253740 kb
Host smart-c00fc9c5-7187-4cdb-b5fd-7c7fdc0409b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672178078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1672178078
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.4110384660
Short name T232
Test name
Test status
Simulation time 29705841602 ps
CPU time 97.16 seconds
Started Jun 27 04:41:37 PM PDT 24
Finished Jun 27 04:43:17 PM PDT 24
Peak memory 254104 kb
Host smart-981564c5-680a-404e-ada0-9f0a6eb6aa90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110384660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.4110384660
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2488216643
Short name T797
Test name
Test status
Simulation time 7550313378 ps
CPU time 86.56 seconds
Started Jun 27 04:41:43 PM PDT 24
Finished Jun 27 04:43:15 PM PDT 24
Peak memory 238280 kb
Host smart-cad82b8d-8175-46f1-b6dc-afac081e300e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488216643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2488216643
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.4993166
Short name T354
Test name
Test status
Simulation time 1846309139 ps
CPU time 12.24 seconds
Started Jun 27 04:41:40 PM PDT 24
Finished Jun 27 04:41:55 PM PDT 24
Peak memory 224388 kb
Host smart-52f26491-a183-43ed-bded-0cf5a8f14842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4993166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.4993166
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2008116887
Short name T483
Test name
Test status
Simulation time 2803481382 ps
CPU time 6.7 seconds
Started Jun 27 04:41:40 PM PDT 24
Finished Jun 27 04:41:50 PM PDT 24
Peak memory 232712 kb
Host smart-1b0f4555-0e60-4214-9a93-e228ab72df91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008116887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2008116887
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3824982066
Short name T61
Test name
Test status
Simulation time 17068165330 ps
CPU time 27.34 seconds
Started Jun 27 04:41:38 PM PDT 24
Finished Jun 27 04:42:07 PM PDT 24
Peak memory 224460 kb
Host smart-1b4382c8-96ae-453f-82b1-b6408259c8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824982066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3824982066
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2449385540
Short name T929
Test name
Test status
Simulation time 97075445 ps
CPU time 1.09 seconds
Started Jun 27 04:41:26 PM PDT 24
Finished Jun 27 04:41:32 PM PDT 24
Peak memory 216556 kb
Host smart-84254081-a72a-4c2e-a4c5-0ebb4221ea8c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449385540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2449385540
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.516459181
Short name T930
Test name
Test status
Simulation time 20460596329 ps
CPU time 13.23 seconds
Started Jun 27 04:41:37 PM PDT 24
Finished Jun 27 04:41:52 PM PDT 24
Peak memory 224420 kb
Host smart-98835bfc-730f-400a-a884-1a6d65cd7351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516459181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
516459181
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1552173462
Short name T39
Test name
Test status
Simulation time 3388770833 ps
CPU time 7.08 seconds
Started Jun 27 04:41:43 PM PDT 24
Finished Jun 27 04:41:56 PM PDT 24
Peak memory 224408 kb
Host smart-dac4ef7c-0c3d-4006-8d42-506c243df46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552173462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1552173462
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1783502873
Short name T384
Test name
Test status
Simulation time 313459107 ps
CPU time 3.85 seconds
Started Jun 27 04:41:34 PM PDT 24
Finished Jun 27 04:41:39 PM PDT 24
Peak memory 222880 kb
Host smart-6faa6f5c-d6bb-4519-84c5-2e9b5a27e30f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1783502873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1783502873
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.516154374
Short name T73
Test name
Test status
Simulation time 134802126 ps
CPU time 0.95 seconds
Started Jun 27 04:41:44 PM PDT 24
Finished Jun 27 04:41:51 PM PDT 24
Peak memory 235676 kb
Host smart-66febc70-f3c6-405c-9ca8-c14c330720ab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516154374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.516154374
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.4185729424
Short name T503
Test name
Test status
Simulation time 79097095671 ps
CPU time 34.51 seconds
Started Jun 27 04:41:35 PM PDT 24
Finished Jun 27 04:42:10 PM PDT 24
Peak memory 216160 kb
Host smart-4c7d911f-b370-4de8-8c0b-b4a276371430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185729424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.4185729424
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.4155476173
Short name T693
Test name
Test status
Simulation time 1097713390 ps
CPU time 6.69 seconds
Started Jun 27 04:41:37 PM PDT 24
Finished Jun 27 04:41:46 PM PDT 24
Peak memory 216012 kb
Host smart-fec7bd81-c7de-48d4-ab3b-4eb6a4dad715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155476173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.4155476173
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.447066382
Short name T366
Test name
Test status
Simulation time 113203971 ps
CPU time 1.05 seconds
Started Jun 27 04:41:37 PM PDT 24
Finished Jun 27 04:41:40 PM PDT 24
Peak memory 207192 kb
Host smart-7e085acc-cc6d-449e-92e0-e1ac29ad45b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447066382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.447066382
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2363751374
Short name T951
Test name
Test status
Simulation time 395616687 ps
CPU time 0.9 seconds
Started Jun 27 04:41:35 PM PDT 24
Finished Jun 27 04:41:37 PM PDT 24
Peak memory 205768 kb
Host smart-963512f0-f739-4994-b7f6-1344079f8009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363751374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2363751374
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2004867988
Short name T398
Test name
Test status
Simulation time 2712347607 ps
CPU time 8.06 seconds
Started Jun 27 04:41:37 PM PDT 24
Finished Jun 27 04:41:48 PM PDT 24
Peak memory 232584 kb
Host smart-6d90ded9-b667-4dcf-9c16-ee5cee8f6b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004867988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2004867988
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2741514670
Short name T598
Test name
Test status
Simulation time 22842533 ps
CPU time 0.73 seconds
Started Jun 27 04:43:04 PM PDT 24
Finished Jun 27 04:43:10 PM PDT 24
Peak memory 204760 kb
Host smart-fe03b758-16a6-4c8e-8457-efa2b2d97c2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741514670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2741514670
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.651776052
Short name T701
Test name
Test status
Simulation time 47779711 ps
CPU time 2.49 seconds
Started Jun 27 04:43:00 PM PDT 24
Finished Jun 27 04:43:05 PM PDT 24
Peak memory 232308 kb
Host smart-d95cf7b9-9312-4ae2-a827-b17f4b59e736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651776052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.651776052
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.248217514
Short name T513
Test name
Test status
Simulation time 16577571 ps
CPU time 0.74 seconds
Started Jun 27 04:43:04 PM PDT 24
Finished Jun 27 04:43:10 PM PDT 24
Peak memory 206804 kb
Host smart-37c65f51-d485-4fe9-8af0-7d0b9def9d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248217514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.248217514
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.875192594
Short name T575
Test name
Test status
Simulation time 2340272287 ps
CPU time 51.71 seconds
Started Jun 27 04:43:05 PM PDT 24
Finished Jun 27 04:44:03 PM PDT 24
Peak memory 252916 kb
Host smart-d88dd1f0-217d-44ea-9bd3-2dc9d2d7373f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875192594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.875192594
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.246406761
Short name T266
Test name
Test status
Simulation time 6242816745 ps
CPU time 47.1 seconds
Started Jun 27 04:43:04 PM PDT 24
Finished Jun 27 04:43:56 PM PDT 24
Peak memory 224504 kb
Host smart-be648e25-7df0-4b39-bffc-02c1720040dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246406761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.246406761
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3601614844
Short name T909
Test name
Test status
Simulation time 77560741818 ps
CPU time 156.7 seconds
Started Jun 27 04:42:59 PM PDT 24
Finished Jun 27 04:45:38 PM PDT 24
Peak memory 249436 kb
Host smart-3d8045c8-b0f4-43ce-83fa-f58f264618ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601614844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3601614844
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3169318877
Short name T695
Test name
Test status
Simulation time 10843272060 ps
CPU time 29.68 seconds
Started Jun 27 04:43:06 PM PDT 24
Finished Jun 27 04:43:41 PM PDT 24
Peak memory 249140 kb
Host smart-722ba370-68e3-4bc1-baa0-fbe4a25372f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169318877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3169318877
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1447084386
Short name T877
Test name
Test status
Simulation time 9369813638 ps
CPU time 59.39 seconds
Started Jun 27 04:43:04 PM PDT 24
Finished Jun 27 04:44:08 PM PDT 24
Peak memory 252064 kb
Host smart-db81d2c2-dd88-40a7-b7a2-378a8be5352a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447084386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1447084386
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.477333639
Short name T179
Test name
Test status
Simulation time 4300808715 ps
CPU time 15.88 seconds
Started Jun 27 04:43:03 PM PDT 24
Finished Jun 27 04:43:25 PM PDT 24
Peak memory 229112 kb
Host smart-f8a3b9bd-e4e1-42ae-8a31-5c7d464eac35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477333639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.477333639
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.434570405
Short name T389
Test name
Test status
Simulation time 25659969835 ps
CPU time 23.8 seconds
Started Jun 27 04:42:58 PM PDT 24
Finished Jun 27 04:43:24 PM PDT 24
Peak memory 224344 kb
Host smart-ab6c40b7-a018-482b-b826-c2fa7fd07183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434570405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.434570405
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.236226814
Short name T243
Test name
Test status
Simulation time 811560899 ps
CPU time 7.18 seconds
Started Jun 27 04:43:01 PM PDT 24
Finished Jun 27 04:43:12 PM PDT 24
Peak memory 224360 kb
Host smart-c3c337b1-3846-4aca-9b1c-fa032381340b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236226814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.236226814
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2362401826
Short name T537
Test name
Test status
Simulation time 1204173700 ps
CPU time 4.02 seconds
Started Jun 27 04:43:00 PM PDT 24
Finished Jun 27 04:43:07 PM PDT 24
Peak memory 224364 kb
Host smart-d054c2b9-113d-4a91-ba48-84ee6de4c712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362401826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2362401826
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1496901611
Short name T717
Test name
Test status
Simulation time 425312116 ps
CPU time 3.61 seconds
Started Jun 27 04:43:03 PM PDT 24
Finished Jun 27 04:43:12 PM PDT 24
Peak memory 219240 kb
Host smart-a22be652-9611-4d6c-8a03-077cb8945c89
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1496901611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1496901611
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3539218895
Short name T17
Test name
Test status
Simulation time 4795109368 ps
CPU time 30.67 seconds
Started Jun 27 04:43:01 PM PDT 24
Finished Jun 27 04:43:35 PM PDT 24
Peak memory 240892 kb
Host smart-b7914019-5e58-4a86-86ba-64f4d3a30507
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539218895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3539218895
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.4277082038
Short name T684
Test name
Test status
Simulation time 5071614151 ps
CPU time 31.56 seconds
Started Jun 27 04:43:03 PM PDT 24
Finished Jun 27 04:43:40 PM PDT 24
Peak memory 216376 kb
Host smart-daaacd32-e5e4-42e9-b4fd-a9aa3969e923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277082038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.4277082038
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1698873732
Short name T928
Test name
Test status
Simulation time 5556848552 ps
CPU time 15.88 seconds
Started Jun 27 04:43:01 PM PDT 24
Finished Jun 27 04:43:21 PM PDT 24
Peak memory 216244 kb
Host smart-e3ee0855-0f6e-490a-9f28-3a3508ab2c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698873732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1698873732
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.931817206
Short name T769
Test name
Test status
Simulation time 99999748 ps
CPU time 1.47 seconds
Started Jun 27 04:43:05 PM PDT 24
Finished Jun 27 04:43:12 PM PDT 24
Peak memory 216108 kb
Host smart-13652ff9-c0b3-46e4-9cdc-7c1623566e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931817206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.931817206
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1212726948
Short name T447
Test name
Test status
Simulation time 63853946 ps
CPU time 0.89 seconds
Started Jun 27 04:42:59 PM PDT 24
Finished Jun 27 04:43:02 PM PDT 24
Peak memory 205780 kb
Host smart-1a09326c-e0d7-44b2-866d-80002d78d82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212726948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1212726948
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3103519466
Short name T946
Test name
Test status
Simulation time 213218917 ps
CPU time 2.28 seconds
Started Jun 27 04:43:05 PM PDT 24
Finished Jun 27 04:43:13 PM PDT 24
Peak memory 224248 kb
Host smart-23f70d9d-e06c-42c4-9734-13ce00d90be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103519466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3103519466
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2396789820
Short name T860
Test name
Test status
Simulation time 16000418 ps
CPU time 0.73 seconds
Started Jun 27 04:43:05 PM PDT 24
Finished Jun 27 04:43:11 PM PDT 24
Peak memory 205516 kb
Host smart-0360cb21-6fdf-4741-a51a-7c76a94e98d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396789820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2396789820
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1953860963
Short name T816
Test name
Test status
Simulation time 1045607859 ps
CPU time 9.48 seconds
Started Jun 27 04:43:02 PM PDT 24
Finished Jun 27 04:43:17 PM PDT 24
Peak memory 232484 kb
Host smart-378e0582-e804-44fc-bbe9-1ee96d3534ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953860963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1953860963
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.4207136061
Short name T931
Test name
Test status
Simulation time 38907137 ps
CPU time 0.72 seconds
Started Jun 27 04:43:00 PM PDT 24
Finished Jun 27 04:43:03 PM PDT 24
Peak memory 205780 kb
Host smart-1a87f743-3e4c-4a9d-850d-5212e26495b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207136061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.4207136061
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2559528354
Short name T471
Test name
Test status
Simulation time 8206257246 ps
CPU time 45.85 seconds
Started Jun 27 04:43:04 PM PDT 24
Finished Jun 27 04:43:55 PM PDT 24
Peak memory 249076 kb
Host smart-33c1705b-674c-4660-acbe-8e34b845ae9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559528354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2559528354
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.4272767675
Short name T806
Test name
Test status
Simulation time 28283892390 ps
CPU time 298.44 seconds
Started Jun 27 04:43:02 PM PDT 24
Finished Jun 27 04:48:06 PM PDT 24
Peak memory 253564 kb
Host smart-d0b1a103-9847-4377-8cae-d2469b692402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272767675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.4272767675
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1404233584
Short name T495
Test name
Test status
Simulation time 61178363282 ps
CPU time 130.44 seconds
Started Jun 27 04:43:01 PM PDT 24
Finished Jun 27 04:45:16 PM PDT 24
Peak memory 249120 kb
Host smart-11127b37-c7bf-431f-b0ba-452080ffde4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404233584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1404233584
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1084555029
Short name T977
Test name
Test status
Simulation time 1228128309 ps
CPU time 3.97 seconds
Started Jun 27 04:43:03 PM PDT 24
Finished Jun 27 04:43:12 PM PDT 24
Peak memory 224304 kb
Host smart-026dea73-c626-44f5-b79a-a4402abf7bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084555029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1084555029
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.1513520697
Short name T251
Test name
Test status
Simulation time 3650480875 ps
CPU time 46.66 seconds
Started Jun 27 04:43:01 PM PDT 24
Finished Jun 27 04:43:51 PM PDT 24
Peak memory 240832 kb
Host smart-ca84c7a7-ef99-4044-a69e-4579075ffa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513520697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.1513520697
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.636889313
Short name T647
Test name
Test status
Simulation time 4082904952 ps
CPU time 16.89 seconds
Started Jun 27 04:43:02 PM PDT 24
Finished Jun 27 04:43:24 PM PDT 24
Peak memory 232616 kb
Host smart-9cd264a1-8fe7-481f-b5e7-aaa2db508bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636889313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.636889313
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3417820382
Short name T388
Test name
Test status
Simulation time 1750296938 ps
CPU time 22.13 seconds
Started Jun 27 04:43:00 PM PDT 24
Finished Jun 27 04:43:25 PM PDT 24
Peak memory 240776 kb
Host smart-c467b451-9d9c-4154-a462-f37661922cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417820382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3417820382
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.298932820
Short name T259
Test name
Test status
Simulation time 6509640207 ps
CPU time 11.32 seconds
Started Jun 27 04:43:01 PM PDT 24
Finished Jun 27 04:43:15 PM PDT 24
Peak memory 232652 kb
Host smart-02a16d2e-0395-46c9-86e4-3e4c15837e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298932820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.298932820
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1904828841
Short name T419
Test name
Test status
Simulation time 3254306234 ps
CPU time 10.54 seconds
Started Jun 27 04:43:03 PM PDT 24
Finished Jun 27 04:43:19 PM PDT 24
Peak memory 240820 kb
Host smart-442b8a31-acde-46c1-84a3-298235d91389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904828841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1904828841
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3095520846
Short name T664
Test name
Test status
Simulation time 896722417 ps
CPU time 5.7 seconds
Started Jun 27 04:43:02 PM PDT 24
Finished Jun 27 04:43:13 PM PDT 24
Peak memory 222796 kb
Host smart-0fe3f139-3812-4660-8385-d1a90325ab44
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3095520846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3095520846
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1513780568
Short name T470
Test name
Test status
Simulation time 66024528498 ps
CPU time 333.1 seconds
Started Jun 27 04:43:03 PM PDT 24
Finished Jun 27 04:48:41 PM PDT 24
Peak memory 255820 kb
Host smart-2d4a6a73-f41b-4968-85e2-684ba6689e50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513780568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1513780568
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.828640948
Short name T803
Test name
Test status
Simulation time 2432570682 ps
CPU time 15.13 seconds
Started Jun 27 04:43:02 PM PDT 24
Finished Jun 27 04:43:23 PM PDT 24
Peak memory 216132 kb
Host smart-6e2b872f-abc1-435a-9393-94df220ee07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828640948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.828640948
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1804945297
Short name T332
Test name
Test status
Simulation time 8029029851 ps
CPU time 20.52 seconds
Started Jun 27 04:43:04 PM PDT 24
Finished Jun 27 04:43:30 PM PDT 24
Peak memory 216200 kb
Host smart-c8d3c430-715f-4ed8-84dc-281ba8f9774b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804945297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1804945297
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2914307701
Short name T943
Test name
Test status
Simulation time 46035842 ps
CPU time 0.99 seconds
Started Jun 27 04:43:05 PM PDT 24
Finished Jun 27 04:43:12 PM PDT 24
Peak memory 207020 kb
Host smart-d28f7118-02aa-4bfd-b400-ec86a1177ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914307701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2914307701
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.60325894
Short name T880
Test name
Test status
Simulation time 162817957 ps
CPU time 0.89 seconds
Started Jun 27 04:43:02 PM PDT 24
Finished Jun 27 04:43:08 PM PDT 24
Peak memory 205744 kb
Host smart-7c733805-ac85-4cb4-b643-d30456a65e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60325894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.60325894
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2184194830
Short name T462
Test name
Test status
Simulation time 2965464703 ps
CPU time 7.71 seconds
Started Jun 27 04:43:12 PM PDT 24
Finished Jun 27 04:43:22 PM PDT 24
Peak memory 224456 kb
Host smart-9f682eec-7b3a-43cb-a8d8-f2508a8fa7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184194830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2184194830
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.994797641
Short name T315
Test name
Test status
Simulation time 22621910 ps
CPU time 0.73 seconds
Started Jun 27 04:43:00 PM PDT 24
Finished Jun 27 04:43:03 PM PDT 24
Peak memory 205684 kb
Host smart-0bf1fdaf-6966-45a4-a400-86797df5ab56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994797641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.994797641
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2101650023
Short name T672
Test name
Test status
Simulation time 3244916865 ps
CPU time 18.01 seconds
Started Jun 27 04:43:04 PM PDT 24
Finished Jun 27 04:43:27 PM PDT 24
Peak memory 232656 kb
Host smart-f89d199f-eafa-474c-b767-42e39b9f7548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101650023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2101650023
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.746437921
Short name T665
Test name
Test status
Simulation time 23619935 ps
CPU time 0.78 seconds
Started Jun 27 04:43:09 PM PDT 24
Finished Jun 27 04:43:14 PM PDT 24
Peak memory 206476 kb
Host smart-57a776db-8e66-48cb-87ec-2297e14032e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746437921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.746437921
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.99140913
Short name T161
Test name
Test status
Simulation time 32668213559 ps
CPU time 110.24 seconds
Started Jun 27 04:43:02 PM PDT 24
Finished Jun 27 04:44:56 PM PDT 24
Peak memory 252416 kb
Host smart-ee3f9796-3472-4694-b269-02aa7bb1cf25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99140913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.99140913
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3323151358
Short name T261
Test name
Test status
Simulation time 12377234968 ps
CPU time 126.26 seconds
Started Jun 27 04:43:06 PM PDT 24
Finished Jun 27 04:45:17 PM PDT 24
Peak memory 250124 kb
Host smart-3c08be88-f430-4516-a71c-716097436993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323151358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3323151358
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3580012978
Short name T733
Test name
Test status
Simulation time 13820745220 ps
CPU time 110.04 seconds
Started Jun 27 04:43:06 PM PDT 24
Finished Jun 27 04:45:01 PM PDT 24
Peak memory 249008 kb
Host smart-7161f3d4-a5b2-4a88-a1d6-50beedb3fc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580012978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3580012978
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2038036815
Short name T601
Test name
Test status
Simulation time 1092342910 ps
CPU time 12.16 seconds
Started Jun 27 04:43:03 PM PDT 24
Finished Jun 27 04:43:20 PM PDT 24
Peak memory 240764 kb
Host smart-60a310df-883a-4414-a588-2353bbef774e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038036815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2038036815
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.134311179
Short name T378
Test name
Test status
Simulation time 13305466554 ps
CPU time 51.97 seconds
Started Jun 27 04:43:04 PM PDT 24
Finished Jun 27 04:44:01 PM PDT 24
Peak memory 250924 kb
Host smart-0b8f6825-bf2f-4b98-a22a-cc51514f40f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134311179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds
.134311179
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2563312883
Short name T914
Test name
Test status
Simulation time 1191304437 ps
CPU time 5.07 seconds
Started Jun 27 04:43:03 PM PDT 24
Finished Jun 27 04:43:13 PM PDT 24
Peak memory 232500 kb
Host smart-19c0dfeb-4b25-4772-8cfa-ca7a2ab59cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563312883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2563312883
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.744393183
Short name T25
Test name
Test status
Simulation time 11806891253 ps
CPU time 35.58 seconds
Started Jun 27 04:43:04 PM PDT 24
Finished Jun 27 04:43:45 PM PDT 24
Peak memory 224484 kb
Host smart-633ee600-8fd4-43c0-8576-febe2b7c07f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744393183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.744393183
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1497819423
Short name T65
Test name
Test status
Simulation time 2101675809 ps
CPU time 3.38 seconds
Started Jun 27 04:43:02 PM PDT 24
Finished Jun 27 04:43:10 PM PDT 24
Peak memory 224308 kb
Host smart-aba708c8-70a2-4977-a37c-cbb40284c935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497819423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1497819423
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.651986319
Short name T942
Test name
Test status
Simulation time 169006500 ps
CPU time 3.05 seconds
Started Jun 27 04:43:04 PM PDT 24
Finished Jun 27 04:43:12 PM PDT 24
Peak memory 224316 kb
Host smart-310f6fbf-1632-4406-966c-4d3e0e29d8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651986319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.651986319
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1255013834
Short name T814
Test name
Test status
Simulation time 8067620111 ps
CPU time 26.57 seconds
Started Jun 27 04:43:02 PM PDT 24
Finished Jun 27 04:43:32 PM PDT 24
Peak memory 220380 kb
Host smart-39552fa4-3c44-41d6-952b-77024f7ef383
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1255013834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1255013834
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2992935446
Short name T9
Test name
Test status
Simulation time 119639925 ps
CPU time 2.64 seconds
Started Jun 27 04:43:11 PM PDT 24
Finished Jun 27 04:43:16 PM PDT 24
Peak memory 216200 kb
Host smart-b84f2adb-2189-4625-9b24-8b28e4ebcce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992935446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2992935446
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.335554036
Short name T330
Test name
Test status
Simulation time 2065097975 ps
CPU time 9.41 seconds
Started Jun 27 04:43:01 PM PDT 24
Finished Jun 27 04:43:15 PM PDT 24
Peak memory 216008 kb
Host smart-57dc26d1-ee6d-4b24-8668-2fc8b62822c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335554036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.335554036
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2067485864
Short name T622
Test name
Test status
Simulation time 2225407055 ps
CPU time 2.42 seconds
Started Jun 27 04:43:02 PM PDT 24
Finished Jun 27 04:43:09 PM PDT 24
Peak memory 216140 kb
Host smart-22504fb3-f8b3-4e0a-af14-91bac1cf86c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067485864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2067485864
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3246704950
Short name T732
Test name
Test status
Simulation time 35013332 ps
CPU time 0.78 seconds
Started Jun 27 04:43:01 PM PDT 24
Finished Jun 27 04:43:06 PM PDT 24
Peak memory 205776 kb
Host smart-6204f99a-3687-4da0-ad07-e0454d26dfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246704950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3246704950
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1686003655
Short name T213
Test name
Test status
Simulation time 1738460640 ps
CPU time 7.47 seconds
Started Jun 27 04:43:05 PM PDT 24
Finished Jun 27 04:43:18 PM PDT 24
Peak memory 232452 kb
Host smart-dd760592-e6fd-4573-97df-bd7108134fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686003655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1686003655
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1240593156
Short name T519
Test name
Test status
Simulation time 17424515 ps
CPU time 0.71 seconds
Started Jun 27 04:43:03 PM PDT 24
Finished Jun 27 04:43:09 PM PDT 24
Peak memory 204756 kb
Host smart-1c6cb221-07d2-4d81-bcf5-81e73b42b2a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240593156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1240593156
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.4179105773
Short name T854
Test name
Test status
Simulation time 2034525656 ps
CPU time 5.5 seconds
Started Jun 27 04:43:03 PM PDT 24
Finished Jun 27 04:43:13 PM PDT 24
Peak memory 232484 kb
Host smart-afa9a266-259b-43dc-9064-48e1988de043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179105773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.4179105773
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3778973605
Short name T439
Test name
Test status
Simulation time 54645415 ps
CPU time 0.79 seconds
Started Jun 27 04:43:00 PM PDT 24
Finished Jun 27 04:43:03 PM PDT 24
Peak memory 206820 kb
Host smart-83575854-b266-4a0a-8bfc-08d93d335faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778973605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3778973605
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2420276224
Short name T724
Test name
Test status
Simulation time 12183098557 ps
CPU time 78.4 seconds
Started Jun 27 04:43:06 PM PDT 24
Finished Jun 27 04:44:29 PM PDT 24
Peak memory 252272 kb
Host smart-df87e636-7339-4cbe-8944-605561a2dd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420276224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2420276224
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2407892353
Short name T326
Test name
Test status
Simulation time 133393670 ps
CPU time 4.1 seconds
Started Jun 27 04:42:59 PM PDT 24
Finished Jun 27 04:43:06 PM PDT 24
Peak memory 233552 kb
Host smart-99eb85fb-0141-4926-95d2-8cf30b42233d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407892353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2407892353
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.1250212590
Short name T856
Test name
Test status
Simulation time 2881321295 ps
CPU time 25.9 seconds
Started Jun 27 04:43:05 PM PDT 24
Finished Jun 27 04:43:36 PM PDT 24
Peak memory 254012 kb
Host smart-a9a53561-c5be-49ab-b523-e1905ae53319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250212590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.1250212590
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2947809774
Short name T205
Test name
Test status
Simulation time 2697823691 ps
CPU time 8.5 seconds
Started Jun 27 04:43:04 PM PDT 24
Finished Jun 27 04:43:18 PM PDT 24
Peak memory 224420 kb
Host smart-840c25bc-ffd3-4cb9-a1fe-8785c8c45ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947809774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2947809774
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2632052054
Short name T891
Test name
Test status
Simulation time 14325274526 ps
CPU time 32.64 seconds
Started Jun 27 04:43:06 PM PDT 24
Finished Jun 27 04:43:43 PM PDT 24
Peak memory 224424 kb
Host smart-82653da3-743c-4e20-8dba-d863016b2eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632052054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2632052054
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2692181640
Short name T757
Test name
Test status
Simulation time 6774649013 ps
CPU time 8.08 seconds
Started Jun 27 04:43:05 PM PDT 24
Finished Jun 27 04:43:19 PM PDT 24
Peak memory 224360 kb
Host smart-af5d4cc4-024b-47df-8047-af087da86fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692181640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2692181640
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3667646463
Short name T586
Test name
Test status
Simulation time 6253895550 ps
CPU time 17.16 seconds
Started Jun 27 04:43:06 PM PDT 24
Finished Jun 27 04:43:28 PM PDT 24
Peak memory 240640 kb
Host smart-06e777c4-d795-4567-932b-588fb03b0b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667646463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3667646463
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1685657264
Short name T967
Test name
Test status
Simulation time 2772921119 ps
CPU time 7.91 seconds
Started Jun 27 04:43:05 PM PDT 24
Finished Jun 27 04:43:18 PM PDT 24
Peak memory 221904 kb
Host smart-3cc409ac-35ae-4134-9eaa-74eade3327e9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1685657264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1685657264
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2065578715
Short name T591
Test name
Test status
Simulation time 50015220324 ps
CPU time 469.05 seconds
Started Jun 27 04:43:09 PM PDT 24
Finished Jun 27 04:51:02 PM PDT 24
Peak memory 265520 kb
Host smart-a01ffedd-fc9b-4d92-808b-cf0f0d3c288e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065578715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2065578715
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3668290620
Short name T1013
Test name
Test status
Simulation time 687032071 ps
CPU time 2.48 seconds
Started Jun 27 04:43:01 PM PDT 24
Finished Jun 27 04:43:06 PM PDT 24
Peak memory 216336 kb
Host smart-a5c0da35-5296-4e16-9d35-8e67ca1c7c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668290620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3668290620
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1490729326
Short name T850
Test name
Test status
Simulation time 6140400534 ps
CPU time 18.18 seconds
Started Jun 27 04:43:05 PM PDT 24
Finished Jun 27 04:43:28 PM PDT 24
Peak memory 216172 kb
Host smart-c71b0f86-4a1c-4c02-a816-1081682c5e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490729326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1490729326
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2899952238
Short name T329
Test name
Test status
Simulation time 799437886 ps
CPU time 2.76 seconds
Started Jun 27 04:43:01 PM PDT 24
Finished Jun 27 04:43:07 PM PDT 24
Peak memory 216052 kb
Host smart-0e989cbe-36a4-4076-bccc-c66a3f2a8c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899952238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2899952238
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2229542303
Short name T331
Test name
Test status
Simulation time 148718602 ps
CPU time 0.78 seconds
Started Jun 27 04:43:00 PM PDT 24
Finished Jun 27 04:43:03 PM PDT 24
Peak memory 205724 kb
Host smart-91612591-4d97-494c-b4f8-fdcbba35da89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229542303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2229542303
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1989582115
Short name T405
Test name
Test status
Simulation time 823688321 ps
CPU time 5.33 seconds
Started Jun 27 04:43:06 PM PDT 24
Finished Jun 27 04:43:16 PM PDT 24
Peak memory 232524 kb
Host smart-7e52d19e-bdf5-4a9f-b4b4-79f52f75eadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989582115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1989582115
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2369939961
Short name T858
Test name
Test status
Simulation time 13880401 ps
CPU time 0.71 seconds
Started Jun 27 04:43:01 PM PDT 24
Finished Jun 27 04:43:05 PM PDT 24
Peak memory 204700 kb
Host smart-a6c5cddf-9f31-4f96-b168-095d8bde3090
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369939961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2369939961
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1397125208
Short name T573
Test name
Test status
Simulation time 151978746 ps
CPU time 2.41 seconds
Started Jun 27 04:43:08 PM PDT 24
Finished Jun 27 04:43:15 PM PDT 24
Peak memory 224304 kb
Host smart-4c322442-b6e5-4a27-b12f-3072d94e5053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397125208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1397125208
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3754294152
Short name T867
Test name
Test status
Simulation time 18467723 ps
CPU time 0.81 seconds
Started Jun 27 04:43:06 PM PDT 24
Finished Jun 27 04:43:12 PM PDT 24
Peak memory 205808 kb
Host smart-561aa9bf-d410-431a-8479-a88b82ed82ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754294152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3754294152
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.495346854
Short name T811
Test name
Test status
Simulation time 14457309524 ps
CPU time 110.06 seconds
Started Jun 27 04:43:05 PM PDT 24
Finished Jun 27 04:45:00 PM PDT 24
Peak memory 257320 kb
Host smart-0bb17827-9b07-4e29-9d5d-41ab35f3f3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495346854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.495346854
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2548655762
Short name T1005
Test name
Test status
Simulation time 5317388076 ps
CPU time 129.32 seconds
Started Jun 27 04:43:00 PM PDT 24
Finished Jun 27 04:45:13 PM PDT 24
Peak memory 269368 kb
Host smart-1e465a15-0861-4fdf-b73f-06b3ce5eed0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548655762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2548655762
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3961376633
Short name T863
Test name
Test status
Simulation time 26888120890 ps
CPU time 94.15 seconds
Started Jun 27 04:43:02 PM PDT 24
Finished Jun 27 04:44:42 PM PDT 24
Peak memory 251404 kb
Host smart-c67fa651-9d6b-4f22-bdc8-b5f114c0fcbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961376633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3961376633
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2376330080
Short name T799
Test name
Test status
Simulation time 311887884 ps
CPU time 2.73 seconds
Started Jun 27 04:43:08 PM PDT 24
Finished Jun 27 04:43:15 PM PDT 24
Peak memory 232508 kb
Host smart-c946eaa4-f9d7-4a07-be02-d8095a0073e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376330080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2376330080
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2873099626
Short name T412
Test name
Test status
Simulation time 1516852354 ps
CPU time 5.96 seconds
Started Jun 27 04:43:02 PM PDT 24
Finished Jun 27 04:43:13 PM PDT 24
Peak memory 224380 kb
Host smart-77dba1bc-7dcc-4ebb-bed7-66f546230252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873099626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2873099626
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2002618974
Short name T674
Test name
Test status
Simulation time 2503048317 ps
CPU time 10.7 seconds
Started Jun 27 04:43:06 PM PDT 24
Finished Jun 27 04:43:22 PM PDT 24
Peak memory 232648 kb
Host smart-69946e5c-33e4-47e9-b4c2-f4f0c2b12fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002618974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2002618974
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.350915062
Short name T401
Test name
Test status
Simulation time 8787198912 ps
CPU time 9.92 seconds
Started Jun 27 04:43:06 PM PDT 24
Finished Jun 27 04:43:21 PM PDT 24
Peak memory 236800 kb
Host smart-86594f6f-280c-4a49-80aa-54475aea593f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350915062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.350915062
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2719418099
Short name T523
Test name
Test status
Simulation time 1130503109 ps
CPU time 13.11 seconds
Started Jun 27 04:43:06 PM PDT 24
Finished Jun 27 04:43:24 PM PDT 24
Peak memory 222120 kb
Host smart-d2f6d514-3969-4dad-867e-ac713345a95c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2719418099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2719418099
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1441703323
Short name T246
Test name
Test status
Simulation time 596211766147 ps
CPU time 579.58 seconds
Started Jun 27 04:43:05 PM PDT 24
Finished Jun 27 04:52:50 PM PDT 24
Peak memory 267084 kb
Host smart-ae03be64-f2a2-4569-9af4-5c0f0ca4c5ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441703323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1441703323
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.37449353
Short name T485
Test name
Test status
Simulation time 6846960248 ps
CPU time 14.29 seconds
Started Jun 27 04:43:05 PM PDT 24
Finished Jun 27 04:43:25 PM PDT 24
Peak memory 216352 kb
Host smart-b80f8ea1-57b4-49ee-9d95-fe943d8940e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37449353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.37449353
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1972588058
Short name T92
Test name
Test status
Simulation time 1575696069 ps
CPU time 4.08 seconds
Started Jun 27 04:43:08 PM PDT 24
Finished Jun 27 04:43:16 PM PDT 24
Peak memory 216012 kb
Host smart-00b02cc3-b6bf-4f00-9391-96f73dd5593d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972588058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1972588058
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2973255514
Short name T79
Test name
Test status
Simulation time 238578197 ps
CPU time 1.35 seconds
Started Jun 27 04:43:09 PM PDT 24
Finished Jun 27 04:43:14 PM PDT 24
Peak memory 207580 kb
Host smart-abd6a7d3-030d-40aa-a8b0-c7c42d209bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973255514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2973255514
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.4273037945
Short name T849
Test name
Test status
Simulation time 23939961 ps
CPU time 0.71 seconds
Started Jun 27 04:43:08 PM PDT 24
Finished Jun 27 04:43:13 PM PDT 24
Peak memory 205756 kb
Host smart-62ff4953-ed50-456c-b4f6-0cde3a0f0375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273037945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.4273037945
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.4095842345
Short name T494
Test name
Test status
Simulation time 3433792618 ps
CPU time 7.39 seconds
Started Jun 27 04:43:03 PM PDT 24
Finished Jun 27 04:43:15 PM PDT 24
Peak memory 232628 kb
Host smart-83594745-0fdc-4374-a5f3-327da3d47823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095842345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.4095842345
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2080920883
Short name T70
Test name
Test status
Simulation time 12519623 ps
CPU time 0.73 seconds
Started Jun 27 04:43:32 PM PDT 24
Finished Jun 27 04:43:35 PM PDT 24
Peak memory 204648 kb
Host smart-27cfac93-1cac-4b01-8470-e39b4470f480
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080920883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2080920883
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2543962885
Short name T865
Test name
Test status
Simulation time 1509901648 ps
CPU time 7.8 seconds
Started Jun 27 04:43:35 PM PDT 24
Finished Jun 27 04:43:50 PM PDT 24
Peak memory 224264 kb
Host smart-3854ee41-5062-41f7-be13-f48b01d62001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543962885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2543962885
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2654117676
Short name T609
Test name
Test status
Simulation time 16479918 ps
CPU time 0.7 seconds
Started Jun 27 04:43:01 PM PDT 24
Finished Jun 27 04:43:05 PM PDT 24
Peak memory 205728 kb
Host smart-18d60d85-960b-42d8-9421-3185c066daad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654117676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2654117676
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1933208665
Short name T896
Test name
Test status
Simulation time 2170128162 ps
CPU time 24 seconds
Started Jun 27 04:43:30 PM PDT 24
Finished Jun 27 04:43:56 PM PDT 24
Peak memory 240348 kb
Host smart-e4a6e0b2-339c-4219-8472-9c7c55c92b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933208665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1933208665
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.13943398
Short name T705
Test name
Test status
Simulation time 25851739624 ps
CPU time 99.93 seconds
Started Jun 27 04:43:33 PM PDT 24
Finished Jun 27 04:45:18 PM PDT 24
Peak memory 253608 kb
Host smart-54465746-4cb7-46d9-a94e-87c5fad20ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13943398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.13943398
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2470351199
Short name T284
Test name
Test status
Simulation time 490645103 ps
CPU time 6.51 seconds
Started Jun 27 04:43:37 PM PDT 24
Finished Jun 27 04:43:51 PM PDT 24
Peak memory 222624 kb
Host smart-c965ab73-edd8-49e5-ba6d-a35af62d5351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470351199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2470351199
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3436348242
Short name T277
Test name
Test status
Simulation time 130204216 ps
CPU time 6.98 seconds
Started Jun 27 04:43:30 PM PDT 24
Finished Jun 27 04:43:39 PM PDT 24
Peak memory 232556 kb
Host smart-590a8320-17e9-4e10-9638-29eb8902614e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436348242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3436348242
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.1728814394
Short name T542
Test name
Test status
Simulation time 74219337059 ps
CPU time 267.84 seconds
Started Jun 27 04:43:35 PM PDT 24
Finished Jun 27 04:48:10 PM PDT 24
Peak memory 265432 kb
Host smart-e9433f63-d4ee-462c-bf8e-a827becad5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728814394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.1728814394
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1753183693
Short name T749
Test name
Test status
Simulation time 726432788 ps
CPU time 10.65 seconds
Started Jun 27 04:43:32 PM PDT 24
Finished Jun 27 04:43:47 PM PDT 24
Peak memory 232556 kb
Host smart-e2d7505f-9d9b-40cc-a5c9-2594603154ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753183693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1753183693
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2442464058
Short name T93
Test name
Test status
Simulation time 5814564724 ps
CPU time 49.96 seconds
Started Jun 27 04:43:32 PM PDT 24
Finished Jun 27 04:44:27 PM PDT 24
Peak memory 234268 kb
Host smart-c04d7f65-2064-4f41-a191-ea52e6f43c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442464058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2442464058
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2297412668
Short name T561
Test name
Test status
Simulation time 10042137556 ps
CPU time 10.94 seconds
Started Jun 27 04:43:30 PM PDT 24
Finished Jun 27 04:43:43 PM PDT 24
Peak memory 232596 kb
Host smart-97ef8140-c686-4be1-8ba2-c18fd08aed05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297412668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2297412668
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1467650290
Short name T148
Test name
Test status
Simulation time 631453295 ps
CPU time 2.39 seconds
Started Jun 27 04:43:02 PM PDT 24
Finished Jun 27 04:43:08 PM PDT 24
Peak memory 223612 kb
Host smart-73c789ad-5f65-4580-96c9-75b56f920475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467650290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1467650290
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3008949030
Short name T952
Test name
Test status
Simulation time 2922336293 ps
CPU time 9.25 seconds
Started Jun 27 04:43:37 PM PDT 24
Finished Jun 27 04:43:53 PM PDT 24
Peak memory 219136 kb
Host smart-764138a1-9c4e-4187-b54e-93c1d703c150
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3008949030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3008949030
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.293103589
Short name T720
Test name
Test status
Simulation time 4354481715 ps
CPU time 70.59 seconds
Started Jun 27 04:43:29 PM PDT 24
Finished Jun 27 04:44:41 PM PDT 24
Peak memory 250788 kb
Host smart-cf842631-7df2-4e36-b48a-8be6fce507bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293103589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.293103589
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2442962726
Short name T547
Test name
Test status
Simulation time 760130013 ps
CPU time 7.51 seconds
Started Jun 27 04:43:06 PM PDT 24
Finished Jun 27 04:43:19 PM PDT 24
Peak memory 216472 kb
Host smart-ca91fbda-5e28-4a6a-bba9-67f221d749ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442962726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2442962726
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2890427203
Short name T367
Test name
Test status
Simulation time 1928737606 ps
CPU time 4.55 seconds
Started Jun 27 04:43:04 PM PDT 24
Finished Jun 27 04:43:14 PM PDT 24
Peak memory 216128 kb
Host smart-ec3d46f2-7c2a-4490-ab45-0fb4317fcdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890427203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2890427203
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3484880301
Short name T581
Test name
Test status
Simulation time 50468406 ps
CPU time 0.87 seconds
Started Jun 27 04:43:04 PM PDT 24
Finished Jun 27 04:43:10 PM PDT 24
Peak memory 207000 kb
Host smart-7217b717-e430-4334-a03f-5980de494b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484880301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3484880301
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2083251923
Short name T744
Test name
Test status
Simulation time 124106756 ps
CPU time 0.98 seconds
Started Jun 27 04:43:04 PM PDT 24
Finished Jun 27 04:43:10 PM PDT 24
Peak memory 205756 kb
Host smart-a6cf530a-accb-4e45-b307-2ae27eadeed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083251923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2083251923
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1878096726
Short name T356
Test name
Test status
Simulation time 655303475 ps
CPU time 2.34 seconds
Started Jun 27 04:43:33 PM PDT 24
Finished Jun 27 04:43:40 PM PDT 24
Peak memory 223988 kb
Host smart-fbdf766e-7923-4b07-aedc-494297120e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878096726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1878096726
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1270101651
Short name T566
Test name
Test status
Simulation time 19321060 ps
CPU time 0.75 seconds
Started Jun 27 04:43:30 PM PDT 24
Finished Jun 27 04:43:33 PM PDT 24
Peak memory 205604 kb
Host smart-98e76973-46e2-4183-9eb4-62729795b134
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270101651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1270101651
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2445981957
Short name T172
Test name
Test status
Simulation time 220964832 ps
CPU time 2.68 seconds
Started Jun 27 04:43:36 PM PDT 24
Finished Jun 27 04:43:45 PM PDT 24
Peak memory 224308 kb
Host smart-49de2e8a-5383-4436-a276-8186d7f29117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445981957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2445981957
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.14387068
Short name T627
Test name
Test status
Simulation time 16780544 ps
CPU time 0.8 seconds
Started Jun 27 04:43:33 PM PDT 24
Finished Jun 27 04:43:38 PM PDT 24
Peak memory 206476 kb
Host smart-829c6e79-d2cb-43ba-9b52-331595041cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14387068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.14387068
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.376453243
Short name T902
Test name
Test status
Simulation time 3018107862 ps
CPU time 18.27 seconds
Started Jun 27 04:43:32 PM PDT 24
Finished Jun 27 04:43:54 PM PDT 24
Peak memory 240876 kb
Host smart-9b20dfca-e660-43d3-a208-710a83428ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376453243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.376453243
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3173711323
Short name T198
Test name
Test status
Simulation time 44688888395 ps
CPU time 200.02 seconds
Started Jun 27 04:43:33 PM PDT 24
Finished Jun 27 04:46:58 PM PDT 24
Peak memory 256724 kb
Host smart-88630689-fb5e-4aab-9767-24eb56fb23f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173711323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3173711323
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3222025438
Short name T883
Test name
Test status
Simulation time 39369866461 ps
CPU time 195.72 seconds
Started Jun 27 04:43:33 PM PDT 24
Finished Jun 27 04:46:54 PM PDT 24
Peak memory 251448 kb
Host smart-a03b1584-77f0-428f-ad60-a5fc68fa0a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222025438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3222025438
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.721455230
Short name T486
Test name
Test status
Simulation time 244744777 ps
CPU time 6.57 seconds
Started Jun 27 04:43:33 PM PDT 24
Finished Jun 27 04:43:44 PM PDT 24
Peak memory 224340 kb
Host smart-e106416b-07ec-4239-be4c-bf855912df13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721455230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.721455230
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.4005183368
Short name T777
Test name
Test status
Simulation time 27461536657 ps
CPU time 18.6 seconds
Started Jun 27 04:43:36 PM PDT 24
Finished Jun 27 04:44:02 PM PDT 24
Peak memory 224400 kb
Host smart-ed4f0dee-dc70-4062-a12f-155388120fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005183368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.4005183368
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1361058420
Short name T487
Test name
Test status
Simulation time 1218357526 ps
CPU time 13.73 seconds
Started Jun 27 04:43:34 PM PDT 24
Finished Jun 27 04:43:55 PM PDT 24
Peak memory 248640 kb
Host smart-b7bcab01-5ffa-4e3d-8305-7465fcaeb3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361058420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1361058420
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1653959556
Short name T1014
Test name
Test status
Simulation time 4531163146 ps
CPU time 7.9 seconds
Started Jun 27 04:43:35 PM PDT 24
Finished Jun 27 04:43:50 PM PDT 24
Peak memory 224444 kb
Host smart-6c7fd323-9e47-4b77-a9e8-52cf84997ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653959556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1653959556
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.910530904
Short name T638
Test name
Test status
Simulation time 11414570871 ps
CPU time 18.39 seconds
Started Jun 27 04:43:35 PM PDT 24
Finished Jun 27 04:44:00 PM PDT 24
Peak memory 232656 kb
Host smart-f16e5304-e739-4463-b92e-cd7170271506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910530904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.910530904
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2654706793
Short name T147
Test name
Test status
Simulation time 465551239 ps
CPU time 3.43 seconds
Started Jun 27 04:43:32 PM PDT 24
Finished Jun 27 04:43:38 PM PDT 24
Peak memory 218692 kb
Host smart-2caa2506-11ec-4fb6-9545-c13b96109dce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2654706793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2654706793
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2344724832
Short name T267
Test name
Test status
Simulation time 9466219631 ps
CPU time 48.32 seconds
Started Jun 27 04:43:36 PM PDT 24
Finished Jun 27 04:44:32 PM PDT 24
Peak memory 250684 kb
Host smart-fd42085f-091a-4e19-a39d-ec6f18bc42a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344724832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2344724832
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2498936426
Short name T475
Test name
Test status
Simulation time 126902572357 ps
CPU time 41.23 seconds
Started Jun 27 04:43:29 PM PDT 24
Finished Jun 27 04:44:12 PM PDT 24
Peak memory 216192 kb
Host smart-6db7df51-73e0-48a1-988a-6d8dda1bf1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498936426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2498936426
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3084950831
Short name T540
Test name
Test status
Simulation time 17289959507 ps
CPU time 12.33 seconds
Started Jun 27 04:43:32 PM PDT 24
Finished Jun 27 04:43:48 PM PDT 24
Peak memory 216144 kb
Host smart-3b13b0f5-2fde-4230-b4ed-abe45c2cd679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084950831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3084950831
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.987972576
Short name T352
Test name
Test status
Simulation time 27283609 ps
CPU time 1 seconds
Started Jun 27 04:43:37 PM PDT 24
Finished Jun 27 04:43:46 PM PDT 24
Peak memory 206980 kb
Host smart-5f656732-2658-4723-80ff-e926e29fc70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987972576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.987972576
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.966784804
Short name T343
Test name
Test status
Simulation time 55273439 ps
CPU time 0.88 seconds
Started Jun 27 04:43:32 PM PDT 24
Finished Jun 27 04:43:36 PM PDT 24
Peak memory 205756 kb
Host smart-5b154415-bbaa-4a74-804d-dd02001242ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966784804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.966784804
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1105801910
Short name T217
Test name
Test status
Simulation time 971445576 ps
CPU time 6.82 seconds
Started Jun 27 04:43:33 PM PDT 24
Finished Jun 27 04:43:45 PM PDT 24
Peak memory 232480 kb
Host smart-468b34d0-a8a4-4e26-ab4b-d54386ee36ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105801910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1105801910
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2311348428
Short name T956
Test name
Test status
Simulation time 14841197 ps
CPU time 0.79 seconds
Started Jun 27 04:43:33 PM PDT 24
Finished Jun 27 04:43:38 PM PDT 24
Peak memory 205700 kb
Host smart-1722688c-094a-4aa1-a963-27941e99308a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311348428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2311348428
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3597584510
Short name T716
Test name
Test status
Simulation time 2533891410 ps
CPU time 13.45 seconds
Started Jun 27 04:43:34 PM PDT 24
Finished Jun 27 04:43:53 PM PDT 24
Peak memory 224476 kb
Host smart-aa0c86ed-fa6a-48e7-ad04-6eb553345eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597584510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3597584510
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1954674852
Short name T989
Test name
Test status
Simulation time 18363645 ps
CPU time 0.79 seconds
Started Jun 27 04:43:32 PM PDT 24
Finished Jun 27 04:43:35 PM PDT 24
Peak memory 206480 kb
Host smart-c539efc5-e9ab-48ed-ba20-0aa28d7d5e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954674852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1954674852
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3347510381
Short name T207
Test name
Test status
Simulation time 23955802047 ps
CPU time 23.38 seconds
Started Jun 27 04:43:36 PM PDT 24
Finished Jun 27 04:44:07 PM PDT 24
Peak memory 236988 kb
Host smart-02ab0040-1536-4371-82f6-5402e3f7283e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347510381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3347510381
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2080898992
Short name T235
Test name
Test status
Simulation time 11192213363 ps
CPU time 159.12 seconds
Started Jun 27 04:43:34 PM PDT 24
Finished Jun 27 04:46:18 PM PDT 24
Peak memory 249168 kb
Host smart-ec067ea4-32aa-4461-8469-e88bcb797363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080898992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2080898992
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3973588016
Short name T42
Test name
Test status
Simulation time 68057257612 ps
CPU time 91.12 seconds
Started Jun 27 04:43:32 PM PDT 24
Finished Jun 27 04:45:07 PM PDT 24
Peak memory 249128 kb
Host smart-709f3896-3ecd-44a4-a694-fc25f4ef7ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973588016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3973588016
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3009434571
Short name T363
Test name
Test status
Simulation time 372340996 ps
CPU time 6 seconds
Started Jun 27 04:43:35 PM PDT 24
Finished Jun 27 04:43:47 PM PDT 24
Peak memory 232584 kb
Host smart-e3123771-ccce-4fd8-859e-0522436729c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009434571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3009434571
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.2616706696
Short name T431
Test name
Test status
Simulation time 6850836945 ps
CPU time 57.15 seconds
Started Jun 27 04:43:35 PM PDT 24
Finished Jun 27 04:44:38 PM PDT 24
Peak memory 249024 kb
Host smart-ee8702b6-8a8b-4985-be3f-f572f8c452c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616706696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.2616706696
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2908735116
Short name T468
Test name
Test status
Simulation time 168429745 ps
CPU time 4.71 seconds
Started Jun 27 04:43:34 PM PDT 24
Finished Jun 27 04:43:45 PM PDT 24
Peak memory 232588 kb
Host smart-a7a92001-d4b0-4413-9def-517fb8749952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908735116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2908735116
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3518167795
Short name T682
Test name
Test status
Simulation time 533785255 ps
CPU time 8.59 seconds
Started Jun 27 04:43:35 PM PDT 24
Finished Jun 27 04:43:51 PM PDT 24
Peak memory 240340 kb
Host smart-552cc4a2-860c-4f84-89c5-519fede635a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518167795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3518167795
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2784355832
Short name T671
Test name
Test status
Simulation time 6168503693 ps
CPU time 18.17 seconds
Started Jun 27 04:43:32 PM PDT 24
Finished Jun 27 04:43:53 PM PDT 24
Peak memory 248512 kb
Host smart-7902fe27-f2a5-48e5-9806-d44ff96bb935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784355832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2784355832
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.564602084
Short name T175
Test name
Test status
Simulation time 993478069 ps
CPU time 6.95 seconds
Started Jun 27 04:43:34 PM PDT 24
Finished Jun 27 04:43:48 PM PDT 24
Peak memory 224416 kb
Host smart-2158edad-434f-48fb-a17a-81568d79642e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564602084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.564602084
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2623147549
Short name T442
Test name
Test status
Simulation time 141688935 ps
CPU time 3.59 seconds
Started Jun 27 04:43:29 PM PDT 24
Finished Jun 27 04:43:34 PM PDT 24
Peak memory 219956 kb
Host smart-336745bf-722d-41ab-81a0-8a9497129c1b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2623147549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2623147549
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.874631169
Short name T90
Test name
Test status
Simulation time 955534406 ps
CPU time 9.88 seconds
Started Jun 27 04:43:35 PM PDT 24
Finished Jun 27 04:43:52 PM PDT 24
Peak memory 216116 kb
Host smart-ca2fec0f-9809-4e19-9d21-ba858f72dfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874631169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.874631169
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.538560506
Short name T835
Test name
Test status
Simulation time 4238871415 ps
CPU time 4.53 seconds
Started Jun 27 04:43:36 PM PDT 24
Finished Jun 27 04:43:48 PM PDT 24
Peak memory 216180 kb
Host smart-bdc6bc85-3660-4c2b-96cc-60da09d23363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538560506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.538560506
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1201196913
Short name T945
Test name
Test status
Simulation time 55066690 ps
CPU time 2.14 seconds
Started Jun 27 04:43:33 PM PDT 24
Finished Jun 27 04:43:40 PM PDT 24
Peak memory 207800 kb
Host smart-4ff56ab2-9402-4e14-b996-32787c0569b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201196913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1201196913
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3575822777
Short name T520
Test name
Test status
Simulation time 31378812 ps
CPU time 0.75 seconds
Started Jun 27 04:43:32 PM PDT 24
Finished Jun 27 04:43:38 PM PDT 24
Peak memory 205736 kb
Host smart-a5e7a441-ca3e-4869-b6cc-e85acd379ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575822777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3575822777
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2812203199
Short name T774
Test name
Test status
Simulation time 2213966916 ps
CPU time 6.69 seconds
Started Jun 27 04:43:32 PM PDT 24
Finished Jun 27 04:43:42 PM PDT 24
Peak memory 224360 kb
Host smart-ae1326e8-f7db-4673-84b6-ed19573b54d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812203199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2812203199
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.500778950
Short name T469
Test name
Test status
Simulation time 20256540 ps
CPU time 0.75 seconds
Started Jun 27 04:43:37 PM PDT 24
Finished Jun 27 04:43:45 PM PDT 24
Peak memory 205352 kb
Host smart-85f61bf7-5987-4e9f-a972-99e8a1f18f1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500778950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.500778950
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3530445235
Short name T979
Test name
Test status
Simulation time 359642920 ps
CPU time 4.43 seconds
Started Jun 27 04:43:34 PM PDT 24
Finished Jun 27 04:43:44 PM PDT 24
Peak memory 232576 kb
Host smart-c1f86546-de6f-4c35-b685-ccc4d77997a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530445235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3530445235
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1562735245
Short name T489
Test name
Test status
Simulation time 27221584 ps
CPU time 0.78 seconds
Started Jun 27 04:43:32 PM PDT 24
Finished Jun 27 04:43:38 PM PDT 24
Peak memory 206376 kb
Host smart-182a0fec-0d28-477e-88a8-a64d2434ae8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562735245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1562735245
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3073611385
Short name T940
Test name
Test status
Simulation time 36752671946 ps
CPU time 105.15 seconds
Started Jun 27 04:43:37 PM PDT 24
Finished Jun 27 04:45:30 PM PDT 24
Peak memory 267740 kb
Host smart-014f8c76-b983-4874-b1a4-b10fe05a8bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073611385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3073611385
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3187108093
Short name T846
Test name
Test status
Simulation time 40277071084 ps
CPU time 99.69 seconds
Started Jun 27 04:43:37 PM PDT 24
Finished Jun 27 04:45:24 PM PDT 24
Peak memory 253740 kb
Host smart-ec68af64-e3fa-44d4-9b62-c0af1a49ecde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187108093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3187108093
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3526527647
Short name T571
Test name
Test status
Simulation time 440934468 ps
CPU time 5.98 seconds
Started Jun 27 04:43:35 PM PDT 24
Finished Jun 27 04:43:47 PM PDT 24
Peak memory 224368 kb
Host smart-db13fdb6-5764-4b1f-bc6c-83a4e6ebf10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526527647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3526527647
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1399221086
Short name T64
Test name
Test status
Simulation time 13600139165 ps
CPU time 22.63 seconds
Started Jun 27 04:43:39 PM PDT 24
Finished Jun 27 04:44:10 PM PDT 24
Peak memory 240884 kb
Host smart-9faefa39-4f14-4f02-9412-420c3a21bfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399221086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1399221086
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3825358331
Short name T435
Test name
Test status
Simulation time 5941672338 ps
CPU time 16.42 seconds
Started Jun 27 04:43:37 PM PDT 24
Finished Jun 27 04:44:01 PM PDT 24
Peak memory 232656 kb
Host smart-12058c24-f40d-429e-80d3-73c23d9f636d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825358331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3825358331
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2426835619
Short name T448
Test name
Test status
Simulation time 86628050 ps
CPU time 2.12 seconds
Started Jun 27 04:43:37 PM PDT 24
Finished Jun 27 04:43:46 PM PDT 24
Peak memory 222992 kb
Host smart-e5313cb0-0121-4ca6-9287-37f190f4901e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426835619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2426835619
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.468973754
Short name T234
Test name
Test status
Simulation time 883039982 ps
CPU time 4.43 seconds
Started Jun 27 04:43:40 PM PDT 24
Finished Jun 27 04:43:52 PM PDT 24
Peak memory 232588 kb
Host smart-b7736b8e-b7a7-41d5-84ed-610094fce2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468973754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.468973754
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3642416443
Short name T869
Test name
Test status
Simulation time 2662508179 ps
CPU time 10.41 seconds
Started Jun 27 04:43:38 PM PDT 24
Finished Jun 27 04:43:56 PM PDT 24
Peak memory 239200 kb
Host smart-e16393ae-9a99-4f78-a0b5-e48acab78a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642416443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3642416443
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.4283042570
Short name T63
Test name
Test status
Simulation time 1262663866 ps
CPU time 3.77 seconds
Started Jun 27 04:43:36 PM PDT 24
Finished Jun 27 04:43:46 PM PDT 24
Peak memory 222464 kb
Host smart-dff00919-ef40-4565-bc16-ec3f07c55a29
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4283042570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.4283042570
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3622421200
Short name T761
Test name
Test status
Simulation time 35683665 ps
CPU time 0.99 seconds
Started Jun 27 04:43:37 PM PDT 24
Finished Jun 27 04:43:46 PM PDT 24
Peak memory 206904 kb
Host smart-1e44ef81-0b18-4b92-aa90-e38230cb65a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622421200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3622421200
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1557767629
Short name T477
Test name
Test status
Simulation time 2059567024 ps
CPU time 20.36 seconds
Started Jun 27 04:43:33 PM PDT 24
Finished Jun 27 04:43:59 PM PDT 24
Peak memory 216204 kb
Host smart-5a19d28d-110e-474b-854e-a9162f91e376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557767629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1557767629
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2216071622
Short name T91
Test name
Test status
Simulation time 26411548174 ps
CPU time 16.21 seconds
Started Jun 27 04:43:31 PM PDT 24
Finished Jun 27 04:43:49 PM PDT 24
Peak memory 216184 kb
Host smart-5775ee1a-2510-4182-9110-d104e2228aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216071622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2216071622
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3070508368
Short name T299
Test name
Test status
Simulation time 1146700493 ps
CPU time 2.73 seconds
Started Jun 27 04:43:32 PM PDT 24
Finished Jun 27 04:43:38 PM PDT 24
Peak memory 216120 kb
Host smart-d79fe738-0f58-4b6c-96d6-1c00d02b106b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070508368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3070508368
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_upload.1400921899
Short name T321
Test name
Test status
Simulation time 1998450827 ps
CPU time 7.95 seconds
Started Jun 27 04:43:34 PM PDT 24
Finished Jun 27 04:43:49 PM PDT 24
Peak memory 224364 kb
Host smart-0fa1a248-130c-4a65-bd11-34db0ec6c39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400921899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1400921899
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.4075612451
Short name T360
Test name
Test status
Simulation time 14984797 ps
CPU time 0.8 seconds
Started Jun 27 04:43:36 PM PDT 24
Finished Jun 27 04:43:43 PM PDT 24
Peak memory 204788 kb
Host smart-b55b0e9a-c193-4353-8b02-a2f8f75d1753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075612451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
4075612451
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1841780114
Short name T996
Test name
Test status
Simulation time 32491653 ps
CPU time 2.24 seconds
Started Jun 27 04:43:38 PM PDT 24
Finished Jun 27 04:43:48 PM PDT 24
Peak memory 232264 kb
Host smart-7507428a-9d0f-48a9-8a58-0f60f548fb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841780114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1841780114
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.968301887
Short name T568
Test name
Test status
Simulation time 34390293 ps
CPU time 0.81 seconds
Started Jun 27 04:43:38 PM PDT 24
Finished Jun 27 04:43:46 PM PDT 24
Peak memory 205684 kb
Host smart-2789c284-a6a0-4bfa-89c9-9681cf6d8af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968301887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.968301887
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3199510246
Short name T206
Test name
Test status
Simulation time 53560452897 ps
CPU time 376.9 seconds
Started Jun 27 04:43:36 PM PDT 24
Finished Jun 27 04:50:00 PM PDT 24
Peak memory 255088 kb
Host smart-81e2613f-c092-4ba0-b9de-0fa7039a4db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199510246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3199510246
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2299927956
Short name T585
Test name
Test status
Simulation time 19139675190 ps
CPU time 90.24 seconds
Started Jun 27 04:43:38 PM PDT 24
Finished Jun 27 04:45:16 PM PDT 24
Peak memory 240824 kb
Host smart-5dd05e7d-43b4-4b00-9501-2851e4643448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299927956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2299927956
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.139209172
Short name T864
Test name
Test status
Simulation time 8824599071 ps
CPU time 20.63 seconds
Started Jun 27 04:43:37 PM PDT 24
Finished Jun 27 04:44:05 PM PDT 24
Peak memory 224404 kb
Host smart-2b196ad2-46fe-460b-b6c2-cc92cf6f9897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139209172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.139209172
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2699861938
Short name T580
Test name
Test status
Simulation time 1358015434 ps
CPU time 20.15 seconds
Started Jun 27 04:43:36 PM PDT 24
Finished Jun 27 04:44:04 PM PDT 24
Peak memory 232600 kb
Host smart-cb9a584c-2f1d-4e7c-b469-8c5cf2d324d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699861938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2699861938
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2560961420
Short name T517
Test name
Test status
Simulation time 1768539435 ps
CPU time 16.95 seconds
Started Jun 27 04:43:39 PM PDT 24
Finished Jun 27 04:44:04 PM PDT 24
Peak memory 224364 kb
Host smart-af57ee5a-b83a-4839-9698-a69bed25ec97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560961420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2560961420
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.4177613815
Short name T668
Test name
Test status
Simulation time 1736993277 ps
CPU time 4.24 seconds
Started Jun 27 04:43:36 PM PDT 24
Finished Jun 27 04:43:48 PM PDT 24
Peak memory 218668 kb
Host smart-ac000d17-bba7-42e2-bdfb-a4c9ca66ae25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177613815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.4177613815
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3974750629
Short name T451
Test name
Test status
Simulation time 472762039 ps
CPU time 2.78 seconds
Started Jun 27 04:43:37 PM PDT 24
Finished Jun 27 04:43:47 PM PDT 24
Peak memory 232528 kb
Host smart-0463e12b-6853-4c37-9959-f99809397ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974750629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3974750629
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.746808462
Short name T759
Test name
Test status
Simulation time 41480065774 ps
CPU time 15.46 seconds
Started Jun 27 04:43:37 PM PDT 24
Finished Jun 27 04:44:00 PM PDT 24
Peak memory 232720 kb
Host smart-dfdd08ce-ffc3-4b4e-95a5-31bcf455dedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746808462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.746808462
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2633259813
Short name T358
Test name
Test status
Simulation time 2328252729 ps
CPU time 8 seconds
Started Jun 27 04:43:37 PM PDT 24
Finished Jun 27 04:43:52 PM PDT 24
Peak memory 223128 kb
Host smart-1a19f420-cd5e-4f0f-9920-64dbfb33a23d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2633259813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2633259813
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3143735008
Short name T289
Test name
Test status
Simulation time 52841049115 ps
CPU time 22.96 seconds
Started Jun 27 04:43:37 PM PDT 24
Finished Jun 27 04:44:08 PM PDT 24
Peak memory 216152 kb
Host smart-9d3da14b-1d20-4c69-9517-9e829c84e302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143735008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3143735008
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1396768077
Short name T828
Test name
Test status
Simulation time 1026837492 ps
CPU time 6.74 seconds
Started Jun 27 04:43:37 PM PDT 24
Finished Jun 27 04:43:52 PM PDT 24
Peak memory 215952 kb
Host smart-f8cf1989-3c3c-40a1-b3e0-a4b434761fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396768077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1396768077
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2175619163
Short name T893
Test name
Test status
Simulation time 838414430 ps
CPU time 3.66 seconds
Started Jun 27 04:43:37 PM PDT 24
Finished Jun 27 04:43:48 PM PDT 24
Peak memory 216204 kb
Host smart-f4dfa046-9677-4f24-bace-8c9405377d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175619163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2175619163
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2730532561
Short name T923
Test name
Test status
Simulation time 327872803 ps
CPU time 0.92 seconds
Started Jun 27 04:43:37 PM PDT 24
Finished Jun 27 04:43:46 PM PDT 24
Peak memory 206832 kb
Host smart-94dc4d41-4d30-40e9-90d0-ff00a71e37f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730532561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2730532561
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2271706697
Short name T706
Test name
Test status
Simulation time 1009958922 ps
CPU time 4.44 seconds
Started Jun 27 04:43:33 PM PDT 24
Finished Jun 27 04:43:43 PM PDT 24
Peak memory 232472 kb
Host smart-379e8933-02e8-4e4c-9f91-466079b3ac97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271706697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2271706697
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2578606554
Short name T376
Test name
Test status
Simulation time 37583822 ps
CPU time 0.69 seconds
Started Jun 27 04:41:41 PM PDT 24
Finished Jun 27 04:41:45 PM PDT 24
Peak memory 205276 kb
Host smart-5ca40c13-e809-4635-b207-10adb1994062
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578606554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
578606554
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2062347592
Short name T871
Test name
Test status
Simulation time 59487007 ps
CPU time 2.64 seconds
Started Jun 27 04:41:38 PM PDT 24
Finished Jun 27 04:41:44 PM PDT 24
Peak memory 232536 kb
Host smart-00f4e978-5d3e-4d8c-b58a-657550059716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062347592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2062347592
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.199382212
Short name T630
Test name
Test status
Simulation time 55688032 ps
CPU time 0.8 seconds
Started Jun 27 04:41:37 PM PDT 24
Finished Jun 27 04:41:40 PM PDT 24
Peak memory 205424 kb
Host smart-8f70ccea-14ac-4a59-a311-1b58a8234db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199382212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.199382212
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.62330045
Short name T181
Test name
Test status
Simulation time 31728893283 ps
CPU time 135.82 seconds
Started Jun 27 04:41:38 PM PDT 24
Finished Jun 27 04:43:56 PM PDT 24
Peak memory 249020 kb
Host smart-786581aa-0c3d-4953-bebf-08c7a085b1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62330045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.62330045
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1923315133
Short name T614
Test name
Test status
Simulation time 97768464557 ps
CPU time 272.86 seconds
Started Jun 27 04:41:40 PM PDT 24
Finished Jun 27 04:46:16 PM PDT 24
Peak memory 257188 kb
Host smart-362fa2c8-4243-432f-9bab-084e0ac7576a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923315133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1923315133
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3778317127
Short name T660
Test name
Test status
Simulation time 116879285263 ps
CPU time 250.48 seconds
Started Jun 27 04:41:39 PM PDT 24
Finished Jun 27 04:45:52 PM PDT 24
Peak memory 249104 kb
Host smart-69d17617-6d10-4932-810d-916a67bba668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778317127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3778317127
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1097205943
Short name T687
Test name
Test status
Simulation time 160610183 ps
CPU time 4.29 seconds
Started Jun 27 04:41:39 PM PDT 24
Finished Jun 27 04:41:46 PM PDT 24
Peak memory 224336 kb
Host smart-ce7bd30c-1137-432c-b297-7dec02d4b215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097205943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1097205943
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.1382572946
Short name T807
Test name
Test status
Simulation time 24770131875 ps
CPU time 91.57 seconds
Started Jun 27 04:41:42 PM PDT 24
Finished Jun 27 04:43:18 PM PDT 24
Peak memory 260088 kb
Host smart-b371c2ce-c4d8-449e-8df5-5022410a6978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382572946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.1382572946
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.4258223125
Short name T838
Test name
Test status
Simulation time 5658925877 ps
CPU time 12.85 seconds
Started Jun 27 04:41:37 PM PDT 24
Finished Jun 27 04:41:52 PM PDT 24
Peak memory 232608 kb
Host smart-25357639-439d-4206-9ad4-f7a4cbc888a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258223125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.4258223125
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.4258892601
Short name T995
Test name
Test status
Simulation time 214560165 ps
CPU time 3.3 seconds
Started Jun 27 04:41:35 PM PDT 24
Finished Jun 27 04:41:40 PM PDT 24
Peak memory 232584 kb
Host smart-d980d01e-e606-4ba4-b2f3-31ebb70279b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258892601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.4258892601
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.79466723
Short name T345
Test name
Test status
Simulation time 117797755 ps
CPU time 1.07 seconds
Started Jun 27 04:41:43 PM PDT 24
Finished Jun 27 04:41:51 PM PDT 24
Peak memory 216692 kb
Host smart-12fbeb12-80db-40f8-839d-43a74d10e876
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79466723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.spi_device_mem_parity.79466723
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3443957991
Short name T763
Test name
Test status
Simulation time 57420448 ps
CPU time 2.47 seconds
Started Jun 27 04:41:40 PM PDT 24
Finished Jun 27 04:41:46 PM PDT 24
Peak memory 232444 kb
Host smart-d8166922-cd3b-48a0-866b-74db0892a6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443957991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3443957991
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3096839618
Short name T526
Test name
Test status
Simulation time 1581419020 ps
CPU time 6.81 seconds
Started Jun 27 04:41:40 PM PDT 24
Finished Jun 27 04:41:51 PM PDT 24
Peak memory 239752 kb
Host smart-b572e5be-8b3c-4755-ad1e-a67273ef97ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096839618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3096839618
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.996108882
Short name T473
Test name
Test status
Simulation time 5818700374 ps
CPU time 6.76 seconds
Started Jun 27 04:41:38 PM PDT 24
Finished Jun 27 04:41:48 PM PDT 24
Peak memory 223112 kb
Host smart-3e9580fb-3d9b-446b-b21c-ec308ba19584
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=996108882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.996108882
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3609557251
Short name T422
Test name
Test status
Simulation time 6283301927 ps
CPU time 41.17 seconds
Started Jun 27 04:41:40 PM PDT 24
Finished Jun 27 04:42:24 PM PDT 24
Peak memory 232728 kb
Host smart-4e227fcc-cfca-4218-92a1-bf2a4ecb7429
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609557251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3609557251
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2193073049
Short name T583
Test name
Test status
Simulation time 5850833553 ps
CPU time 16.58 seconds
Started Jun 27 04:41:38 PM PDT 24
Finished Jun 27 04:41:57 PM PDT 24
Peak memory 216220 kb
Host smart-943fcfda-2895-433e-9a53-b9c8451f145d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193073049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2193073049
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.213981936
Short name T357
Test name
Test status
Simulation time 763817552 ps
CPU time 2.91 seconds
Started Jun 27 04:41:37 PM PDT 24
Finished Jun 27 04:41:42 PM PDT 24
Peak memory 207672 kb
Host smart-6bc5ca73-3c69-496c-99d5-f18f1a127888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213981936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.213981936
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.680948098
Short name T634
Test name
Test status
Simulation time 324970483 ps
CPU time 10.23 seconds
Started Jun 27 04:41:36 PM PDT 24
Finished Jun 27 04:41:49 PM PDT 24
Peak memory 216160 kb
Host smart-1946c232-60fe-4048-a9eb-7ddca8d5a05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680948098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.680948098
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1320810454
Short name T338
Test name
Test status
Simulation time 212648061 ps
CPU time 0.8 seconds
Started Jun 27 04:41:38 PM PDT 24
Finished Jun 27 04:41:42 PM PDT 24
Peak memory 205732 kb
Host smart-71cdee01-79c3-4785-9ea5-474b040ad43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320810454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1320810454
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2816539223
Short name T691
Test name
Test status
Simulation time 8463821508 ps
CPU time 12.7 seconds
Started Jun 27 04:41:39 PM PDT 24
Finished Jun 27 04:41:54 PM PDT 24
Peak memory 232628 kb
Host smart-3e17b228-6df2-4cae-9850-756a7cb4d2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816539223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2816539223
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2042011952
Short name T635
Test name
Test status
Simulation time 22389963 ps
CPU time 0.73 seconds
Started Jun 27 04:43:37 PM PDT 24
Finished Jun 27 04:43:45 PM PDT 24
Peak memory 204708 kb
Host smart-796757ef-ee60-40b4-86d6-a0aa78fc94a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042011952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2042011952
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1798603978
Short name T709
Test name
Test status
Simulation time 3796668063 ps
CPU time 16.03 seconds
Started Jun 27 04:43:36 PM PDT 24
Finished Jun 27 04:43:59 PM PDT 24
Peak memory 232604 kb
Host smart-5855a397-f9cd-44ab-8296-33dce0a8a3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798603978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1798603978
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3941101547
Short name T621
Test name
Test status
Simulation time 17713169 ps
CPU time 0.77 seconds
Started Jun 27 04:43:34 PM PDT 24
Finished Jun 27 04:43:41 PM PDT 24
Peak memory 205388 kb
Host smart-31dae971-ed57-4829-a896-4927bb00f833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941101547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3941101547
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1791073625
Short name T493
Test name
Test status
Simulation time 9446581843 ps
CPU time 21.77 seconds
Started Jun 27 04:43:38 PM PDT 24
Finished Jun 27 04:44:07 PM PDT 24
Peak memory 248828 kb
Host smart-87c66cee-7d5a-4e68-a6a0-f407cc4380b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791073625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1791073625
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.196385538
Short name T260
Test name
Test status
Simulation time 12541443280 ps
CPU time 117.14 seconds
Started Jun 27 04:43:32 PM PDT 24
Finished Jun 27 04:45:33 PM PDT 24
Peak memory 251820 kb
Host smart-e54de9de-9679-41ff-9d5a-89a655b97bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196385538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.196385538
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2055306445
Short name T444
Test name
Test status
Simulation time 48651954040 ps
CPU time 127.35 seconds
Started Jun 27 04:43:38 PM PDT 24
Finished Jun 27 04:45:53 PM PDT 24
Peak memory 256776 kb
Host smart-de8d12b0-1a1a-4515-bf26-b93e46c9359f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055306445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2055306445
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3460235114
Short name T450
Test name
Test status
Simulation time 1890599890 ps
CPU time 30 seconds
Started Jun 27 04:43:33 PM PDT 24
Finished Jun 27 04:44:08 PM PDT 24
Peak memory 247860 kb
Host smart-1e4da28c-ff10-4177-904a-05928b281207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460235114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3460235114
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1090318401
Short name T605
Test name
Test status
Simulation time 9297847882 ps
CPU time 18.4 seconds
Started Jun 27 04:43:35 PM PDT 24
Finished Jun 27 04:44:01 PM PDT 24
Peak memory 232576 kb
Host smart-4a3b4845-080c-4a66-bfdc-fafd7c17dccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090318401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1090318401
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.472782779
Short name T426
Test name
Test status
Simulation time 650919636 ps
CPU time 14.67 seconds
Started Jun 27 04:43:35 PM PDT 24
Finished Jun 27 04:43:57 PM PDT 24
Peak memory 248888 kb
Host smart-23ff5e1e-b730-467c-9543-96f985e0e40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472782779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.472782779
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1071139423
Short name T574
Test name
Test status
Simulation time 2521402885 ps
CPU time 10.03 seconds
Started Jun 27 04:43:38 PM PDT 24
Finished Jun 27 04:43:55 PM PDT 24
Peak memory 249360 kb
Host smart-8dafb4f4-f316-4c8d-8ebe-e04fb0bfc676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071139423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1071139423
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2165661792
Short name T371
Test name
Test status
Simulation time 9342869728 ps
CPU time 19.14 seconds
Started Jun 27 04:43:34 PM PDT 24
Finished Jun 27 04:43:59 PM PDT 24
Peak memory 224476 kb
Host smart-63ddc871-d14c-45ad-885c-e23e8808492e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165661792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2165661792
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3539689552
Short name T27
Test name
Test status
Simulation time 635614078 ps
CPU time 4.57 seconds
Started Jun 27 04:43:33 PM PDT 24
Finished Jun 27 04:43:42 PM PDT 24
Peak memory 222172 kb
Host smart-c9f65aae-d2d1-42ab-b163-7b9eb5871df5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3539689552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3539689552
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.775063465
Short name T683
Test name
Test status
Simulation time 5594815644 ps
CPU time 109.07 seconds
Started Jun 27 04:43:37 PM PDT 24
Finished Jun 27 04:45:33 PM PDT 24
Peak memory 273628 kb
Host smart-944fc319-a756-4ae7-a096-64550a45fc6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775063465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.775063465
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1707934187
Short name T612
Test name
Test status
Simulation time 2904194412 ps
CPU time 15.35 seconds
Started Jun 27 04:43:40 PM PDT 24
Finished Jun 27 04:44:03 PM PDT 24
Peak memory 219868 kb
Host smart-6e3c0c61-909d-48f7-a315-0442ec73278f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707934187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1707934187
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2284846237
Short name T787
Test name
Test status
Simulation time 1837961117 ps
CPU time 8.01 seconds
Started Jun 27 04:43:40 PM PDT 24
Finished Jun 27 04:43:56 PM PDT 24
Peak memory 215988 kb
Host smart-2ffb5996-4780-4ee3-a833-6b129f1a3dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284846237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2284846237
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3888349164
Short name T722
Test name
Test status
Simulation time 40885411 ps
CPU time 0.78 seconds
Started Jun 27 04:43:40 PM PDT 24
Finished Jun 27 04:43:49 PM PDT 24
Peak memory 205812 kb
Host smart-4f3ae50d-6f4c-4e62-9619-b8ef59606748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888349164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3888349164
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1479646320
Short name T534
Test name
Test status
Simulation time 79922459 ps
CPU time 1.13 seconds
Started Jun 27 04:43:35 PM PDT 24
Finished Jun 27 04:43:43 PM PDT 24
Peak memory 205792 kb
Host smart-a9b458d3-c534-45d1-bf91-38b495cf9c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479646320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1479646320
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.631123976
Short name T351
Test name
Test status
Simulation time 696329889 ps
CPU time 5.99 seconds
Started Jun 27 04:43:32 PM PDT 24
Finished Jun 27 04:43:43 PM PDT 24
Peak memory 224324 kb
Host smart-6e3ad42c-daa4-4cfa-b8a3-03d54ea571a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631123976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.631123976
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1925607989
Short name T553
Test name
Test status
Simulation time 31287068 ps
CPU time 0.69 seconds
Started Jun 27 04:43:38 PM PDT 24
Finished Jun 27 04:43:46 PM PDT 24
Peak memory 205692 kb
Host smart-95f35200-4353-49ee-b2c6-1876d2b9cf40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925607989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1925607989
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.189785400
Short name T839
Test name
Test status
Simulation time 42187736 ps
CPU time 2.16 seconds
Started Jun 27 04:43:37 PM PDT 24
Finished Jun 27 04:43:47 PM PDT 24
Peak memory 224356 kb
Host smart-1170c49d-803f-4830-9a7e-9e67af7e5f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189785400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.189785400
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2520932127
Short name T134
Test name
Test status
Simulation time 100363922 ps
CPU time 0.76 seconds
Started Jun 27 04:43:31 PM PDT 24
Finished Jun 27 04:43:34 PM PDT 24
Peak memory 206444 kb
Host smart-c39dfcfd-c56b-468f-8d1b-88ebe264b734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520932127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2520932127
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2627697405
Short name T185
Test name
Test status
Simulation time 1443050669 ps
CPU time 26.2 seconds
Started Jun 27 04:43:39 PM PDT 24
Finished Jun 27 04:44:13 PM PDT 24
Peak memory 249020 kb
Host smart-61c8bed6-c5b3-467f-b30a-feb009c30c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627697405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2627697405
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3888227627
Short name T862
Test name
Test status
Simulation time 8384963994 ps
CPU time 26.77 seconds
Started Jun 27 04:43:39 PM PDT 24
Finished Jun 27 04:44:14 PM PDT 24
Peak memory 224492 kb
Host smart-1b00d181-b1cd-42d5-9bfb-500d5fe4763a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888227627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3888227627
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.364218923
Short name T993
Test name
Test status
Simulation time 4663929758 ps
CPU time 115.72 seconds
Started Jun 27 04:43:35 PM PDT 24
Finished Jun 27 04:45:38 PM PDT 24
Peak memory 262688 kb
Host smart-90c9f56e-fcb6-411d-af17-c23576d8b401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364218923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.364218923
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.179020417
Short name T875
Test name
Test status
Simulation time 1540447659 ps
CPU time 7.47 seconds
Started Jun 27 04:43:37 PM PDT 24
Finished Jun 27 04:43:52 PM PDT 24
Peak memory 232572 kb
Host smart-ff168c79-a1d7-4b51-aa81-9d210181022a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179020417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.179020417
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.921651832
Short name T455
Test name
Test status
Simulation time 244801767 ps
CPU time 6.03 seconds
Started Jun 27 04:43:36 PM PDT 24
Finished Jun 27 04:43:50 PM PDT 24
Peak memory 227224 kb
Host smart-05e19648-982a-46ad-9614-18d49cf716d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921651832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds
.921651832
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.4143743877
Short name T1018
Test name
Test status
Simulation time 1096367595 ps
CPU time 3.48 seconds
Started Jun 27 04:43:39 PM PDT 24
Finished Jun 27 04:43:51 PM PDT 24
Peak memory 232588 kb
Host smart-b0ee20f7-0f83-48de-874e-09aa2f56da30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143743877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.4143743877
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3282621416
Short name T805
Test name
Test status
Simulation time 28027571935 ps
CPU time 94.21 seconds
Started Jun 27 04:43:37 PM PDT 24
Finished Jun 27 04:45:19 PM PDT 24
Peak memory 232636 kb
Host smart-9d274b63-12c8-4fc1-8868-6eaff59a2125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282621416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3282621416
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2911807229
Short name T986
Test name
Test status
Simulation time 706863317 ps
CPU time 10.17 seconds
Started Jun 27 04:43:37 PM PDT 24
Finished Jun 27 04:43:55 PM PDT 24
Peak memory 232572 kb
Host smart-2c68c8db-85bf-4d3e-a378-513a504d1762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911807229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2911807229
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3466376742
Short name T791
Test name
Test status
Simulation time 3036035438 ps
CPU time 4.07 seconds
Started Jun 27 04:43:38 PM PDT 24
Finished Jun 27 04:43:49 PM PDT 24
Peak memory 224776 kb
Host smart-f446d71d-c7a1-4fe9-901f-f89038a71227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466376742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3466376742
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1692963868
Short name T428
Test name
Test status
Simulation time 3113216282 ps
CPU time 10.12 seconds
Started Jun 27 04:43:39 PM PDT 24
Finished Jun 27 04:43:57 PM PDT 24
Peak memory 219272 kb
Host smart-71b683e6-80ab-4c84-9436-cfe373566cdc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1692963868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1692963868
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1373289962
Short name T136
Test name
Test status
Simulation time 58103713446 ps
CPU time 120.6 seconds
Started Jun 27 04:43:38 PM PDT 24
Finished Jun 27 04:45:46 PM PDT 24
Peak memory 250736 kb
Host smart-8c3c0187-d7d4-444b-ad71-37c79c323255
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373289962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1373289962
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.4042142778
Short name T285
Test name
Test status
Simulation time 2219340601 ps
CPU time 18.86 seconds
Started Jun 27 04:43:35 PM PDT 24
Finished Jun 27 04:44:00 PM PDT 24
Peak memory 216212 kb
Host smart-63b7e097-f0dc-40ad-a1b6-0809f939cc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042142778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.4042142778
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.4244549873
Short name T620
Test name
Test status
Simulation time 9714693036 ps
CPU time 8.51 seconds
Started Jun 27 04:43:39 PM PDT 24
Finished Jun 27 04:43:56 PM PDT 24
Peak memory 216300 kb
Host smart-e6de551e-a54d-46b6-9a8e-b75800d8c1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244549873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.4244549873
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1853576917
Short name T636
Test name
Test status
Simulation time 478373321 ps
CPU time 1.43 seconds
Started Jun 27 04:43:40 PM PDT 24
Finished Jun 27 04:43:49 PM PDT 24
Peak memory 216104 kb
Host smart-7d379531-917c-4ba1-aed3-6afc6bc4a2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853576917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1853576917
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.149163640
Short name T318
Test name
Test status
Simulation time 383886804 ps
CPU time 1.01 seconds
Started Jun 27 04:43:37 PM PDT 24
Finished Jun 27 04:43:46 PM PDT 24
Peak memory 205776 kb
Host smart-b3656b1d-5707-4154-9c62-a40b1ca404c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149163640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.149163640
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2560218266
Short name T657
Test name
Test status
Simulation time 21250353191 ps
CPU time 9.64 seconds
Started Jun 27 04:43:36 PM PDT 24
Finished Jun 27 04:43:54 PM PDT 24
Peak memory 224484 kb
Host smart-115a0436-0db3-40a5-bd48-a8538d9b25ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560218266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2560218266
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.491173303
Short name T579
Test name
Test status
Simulation time 28862408 ps
CPU time 0.7 seconds
Started Jun 27 04:43:53 PM PDT 24
Finished Jun 27 04:44:01 PM PDT 24
Peak memory 205332 kb
Host smart-46dcda36-cdf5-478e-a256-f5b27d40db29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491173303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.491173303
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1439447681
Short name T565
Test name
Test status
Simulation time 327712725 ps
CPU time 4.84 seconds
Started Jun 27 04:43:50 PM PDT 24
Finished Jun 27 04:44:00 PM PDT 24
Peak memory 224344 kb
Host smart-2d4c143b-c13e-4df2-b935-ddf5e8eee0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439447681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1439447681
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2082597547
Short name T968
Test name
Test status
Simulation time 13896193 ps
CPU time 0.79 seconds
Started Jun 27 04:43:35 PM PDT 24
Finished Jun 27 04:43:43 PM PDT 24
Peak memory 206500 kb
Host smart-7cc9dec2-b922-46c6-9677-f1fa192c3f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082597547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2082597547
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2408048235
Short name T567
Test name
Test status
Simulation time 3035968091 ps
CPU time 52.71 seconds
Started Jun 27 04:43:48 PM PDT 24
Finished Jun 27 04:44:45 PM PDT 24
Peak memory 249804 kb
Host smart-47844c62-7cf9-4a08-a45a-0e5249ffe48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408048235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2408048235
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3387959242
Short name T644
Test name
Test status
Simulation time 81480065287 ps
CPU time 193.63 seconds
Started Jun 27 04:43:52 PM PDT 24
Finished Jun 27 04:47:13 PM PDT 24
Peak memory 256256 kb
Host smart-acf59574-75ce-4b5c-8e40-f6c18748f627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387959242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3387959242
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.2050208103
Short name T1004
Test name
Test status
Simulation time 21178333887 ps
CPU time 44.71 seconds
Started Jun 27 04:43:47 PM PDT 24
Finished Jun 27 04:44:36 PM PDT 24
Peak memory 234660 kb
Host smart-bf7eabe4-c059-45e4-837d-f1812ca2446f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050208103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.2050208103
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.4129579398
Short name T482
Test name
Test status
Simulation time 1062139176 ps
CPU time 6.71 seconds
Started Jun 27 04:43:50 PM PDT 24
Finished Jun 27 04:44:01 PM PDT 24
Peak memory 224364 kb
Host smart-dade6efd-bc59-47a5-9b43-d2936467c904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129579398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.4129579398
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3526010976
Short name T446
Test name
Test status
Simulation time 15146729947 ps
CPU time 33.3 seconds
Started Jun 27 04:43:49 PM PDT 24
Finished Jun 27 04:44:26 PM PDT 24
Peak memory 248904 kb
Host smart-f858e2f9-f490-4aa0-bce1-e9ffa405bef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526010976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3526010976
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.371381690
Short name T197
Test name
Test status
Simulation time 14788719520 ps
CPU time 14.36 seconds
Started Jun 27 04:43:48 PM PDT 24
Finished Jun 27 04:44:06 PM PDT 24
Peak memory 240332 kb
Host smart-d3b5851c-1ca6-4b3b-adfb-0b2b64381419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371381690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.371381690
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2682095514
Short name T500
Test name
Test status
Simulation time 6690604978 ps
CPU time 6.1 seconds
Started Jun 27 04:43:49 PM PDT 24
Finished Jun 27 04:43:59 PM PDT 24
Peak memory 232680 kb
Host smart-dc3fd740-a471-4cb1-8810-b1884420ff77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682095514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2682095514
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1675156936
Short name T922
Test name
Test status
Simulation time 17684782481 ps
CPU time 12.98 seconds
Started Jun 27 04:43:52 PM PDT 24
Finished Jun 27 04:44:13 PM PDT 24
Peak memory 222448 kb
Host smart-05f20f85-3ecf-4c38-8283-30660c553e37
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1675156936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1675156936
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.960714321
Short name T154
Test name
Test status
Simulation time 7444251051 ps
CPU time 164.2 seconds
Started Jun 27 04:43:51 PM PDT 24
Finished Jun 27 04:46:42 PM PDT 24
Peak memory 273692 kb
Host smart-8bef24a4-106a-4a4b-9cdc-07d40ebf2e9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960714321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.960714321
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3203274496
Short name T287
Test name
Test status
Simulation time 2705858946 ps
CPU time 13.62 seconds
Started Jun 27 04:43:53 PM PDT 24
Finished Jun 27 04:44:14 PM PDT 24
Peak memory 216132 kb
Host smart-62505ab0-02af-41c1-b8b1-d2ce4cb417d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203274496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3203274496
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1809854313
Short name T639
Test name
Test status
Simulation time 37666704613 ps
CPU time 18.29 seconds
Started Jun 27 04:43:36 PM PDT 24
Finished Jun 27 04:44:01 PM PDT 24
Peak memory 216128 kb
Host smart-fb7f7442-aa0d-414d-906b-9ed30ffb4f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809854313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1809854313
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2797166130
Short name T548
Test name
Test status
Simulation time 101316587 ps
CPU time 1.29 seconds
Started Jun 27 04:43:51 PM PDT 24
Finished Jun 27 04:43:59 PM PDT 24
Peak memory 215960 kb
Host smart-fb185592-bcd1-44bc-865a-f1160a205417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797166130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2797166130
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.300480563
Short name T60
Test name
Test status
Simulation time 259693741 ps
CPU time 0.94 seconds
Started Jun 27 04:43:51 PM PDT 24
Finished Jun 27 04:43:58 PM PDT 24
Peak memory 205772 kb
Host smart-ad5f88a9-c99e-4458-8641-de941fcf534d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300480563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.300480563
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.4015389117
Short name T491
Test name
Test status
Simulation time 1061559124 ps
CPU time 4.31 seconds
Started Jun 27 04:43:52 PM PDT 24
Finished Jun 27 04:44:04 PM PDT 24
Peak memory 224420 kb
Host smart-7d81308a-a5ff-4efd-a530-5e8f61cc3ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015389117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.4015389117
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3945007603
Short name T786
Test name
Test status
Simulation time 13738981 ps
CPU time 0.7 seconds
Started Jun 27 04:43:50 PM PDT 24
Finished Jun 27 04:43:56 PM PDT 24
Peak memory 205244 kb
Host smart-5a6bfca0-5b6c-4bb4-a573-ac8085bea42a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945007603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3945007603
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2376490642
Short name T347
Test name
Test status
Simulation time 287328549 ps
CPU time 2.31 seconds
Started Jun 27 04:43:54 PM PDT 24
Finished Jun 27 04:44:05 PM PDT 24
Peak memory 224320 kb
Host smart-db2c55ac-f196-49ec-a09a-cea4bee2ae32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376490642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2376490642
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2684796213
Short name T762
Test name
Test status
Simulation time 14784550 ps
CPU time 0.82 seconds
Started Jun 27 04:43:51 PM PDT 24
Finished Jun 27 04:43:58 PM PDT 24
Peak memory 206800 kb
Host smart-bc323a3b-1964-4e3e-93ef-6aeac0da70e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684796213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2684796213
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.817175209
Short name T458
Test name
Test status
Simulation time 39877157 ps
CPU time 0.76 seconds
Started Jun 27 04:43:52 PM PDT 24
Finished Jun 27 04:44:00 PM PDT 24
Peak memory 207488 kb
Host smart-175c88d8-1a51-46a4-bf35-6e91932c33ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817175209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.817175209
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.110646195
Short name T810
Test name
Test status
Simulation time 1208961943 ps
CPU time 14.64 seconds
Started Jun 27 04:43:52 PM PDT 24
Finished Jun 27 04:44:14 PM PDT 24
Peak memory 217220 kb
Host smart-ede52841-f7d4-4488-b65a-2a08a742a0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110646195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.110646195
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2859353815
Short name T728
Test name
Test status
Simulation time 3688648964 ps
CPU time 72.36 seconds
Started Jun 27 04:43:50 PM PDT 24
Finished Jun 27 04:45:08 PM PDT 24
Peak memory 256292 kb
Host smart-aa91c217-70d0-4b82-802b-8f95e4347cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859353815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2859353815
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1044360609
Short name T280
Test name
Test status
Simulation time 1234580220 ps
CPU time 3.64 seconds
Started Jun 27 04:43:54 PM PDT 24
Finished Jun 27 04:44:05 PM PDT 24
Peak memory 224604 kb
Host smart-9248c0f0-5c9c-4017-bdb4-21cd2f2ee932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044360609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1044360609
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.1259165778
Short name T822
Test name
Test status
Simulation time 5053565346 ps
CPU time 10.48 seconds
Started Jun 27 04:43:53 PM PDT 24
Finished Jun 27 04:44:12 PM PDT 24
Peak memory 234056 kb
Host smart-7fcab9a7-9688-4303-bf83-94617571a24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259165778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.1259165778
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1031111690
Short name T199
Test name
Test status
Simulation time 1983705289 ps
CPU time 8.14 seconds
Started Jun 27 04:43:51 PM PDT 24
Finished Jun 27 04:44:05 PM PDT 24
Peak memory 232552 kb
Host smart-5925dbe6-3981-45ca-a4de-467a480c2569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031111690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1031111690
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3049392772
Short name T504
Test name
Test status
Simulation time 8975690237 ps
CPU time 31.68 seconds
Started Jun 27 04:43:52 PM PDT 24
Finished Jun 27 04:44:31 PM PDT 24
Peak memory 224436 kb
Host smart-2f196a09-99eb-4950-84b0-6a42682e7360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049392772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3049392772
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.276744659
Short name T11
Test name
Test status
Simulation time 260757564 ps
CPU time 5.48 seconds
Started Jun 27 04:43:51 PM PDT 24
Finished Jun 27 04:44:03 PM PDT 24
Peak memory 232868 kb
Host smart-5d4fa401-2073-4228-a2c0-a9e7b945ac1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276744659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.276744659
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2457211114
Short name T456
Test name
Test status
Simulation time 390389156 ps
CPU time 4.01 seconds
Started Jun 27 04:43:52 PM PDT 24
Finished Jun 27 04:44:02 PM PDT 24
Peak memory 224264 kb
Host smart-71d70875-cb56-4832-ab8a-7e9857aff922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457211114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2457211114
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2176780085
Short name T41
Test name
Test status
Simulation time 713573638 ps
CPU time 6.72 seconds
Started Jun 27 04:43:50 PM PDT 24
Finished Jun 27 04:44:00 PM PDT 24
Peak memory 222436 kb
Host smart-fe6f64dd-18b9-4527-bef7-4dbe5a480bd7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2176780085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2176780085
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.283066126
Short name T21
Test name
Test status
Simulation time 308558033 ps
CPU time 1.07 seconds
Started Jun 27 04:43:56 PM PDT 24
Finished Jun 27 04:44:05 PM PDT 24
Peak memory 206848 kb
Host smart-b133afa5-946f-4d93-8313-31bef7d35850
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283066126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.283066126
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1939710621
Short name T889
Test name
Test status
Simulation time 12223670 ps
CPU time 0.72 seconds
Started Jun 27 04:43:52 PM PDT 24
Finished Jun 27 04:43:59 PM PDT 24
Peak memory 205536 kb
Host smart-17a8b1d7-1e44-44ff-8399-2ec0d5dc974f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939710621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1939710621
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3233469348
Short name T881
Test name
Test status
Simulation time 56886773963 ps
CPU time 17.29 seconds
Started Jun 27 04:43:50 PM PDT 24
Finished Jun 27 04:44:11 PM PDT 24
Peak memory 217308 kb
Host smart-a3722d13-a71a-4bc6-9a5d-8cd01cb0ed65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233469348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3233469348
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2609628710
Short name T361
Test name
Test status
Simulation time 20741136 ps
CPU time 0.92 seconds
Started Jun 27 04:43:47 PM PDT 24
Finished Jun 27 04:43:52 PM PDT 24
Peak memory 207776 kb
Host smart-ff2a04a9-7642-4466-888e-f2197b72b3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609628710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2609628710
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1446494378
Short name T924
Test name
Test status
Simulation time 194163503 ps
CPU time 0.83 seconds
Started Jun 27 04:43:52 PM PDT 24
Finished Jun 27 04:43:59 PM PDT 24
Peak memory 205756 kb
Host smart-c914a1ef-7a35-4a00-8f44-705a8e8e5d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446494378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1446494378
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3296168992
Short name T454
Test name
Test status
Simulation time 4542019411 ps
CPU time 13.33 seconds
Started Jun 27 04:43:52 PM PDT 24
Finished Jun 27 04:44:12 PM PDT 24
Peak memory 248496 kb
Host smart-64006ab8-b5a7-43a2-9ed3-1eab36a13868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296168992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3296168992
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1030914530
Short name T960
Test name
Test status
Simulation time 14123516 ps
CPU time 0.7 seconds
Started Jun 27 04:43:49 PM PDT 24
Finished Jun 27 04:43:53 PM PDT 24
Peak memory 205332 kb
Host smart-4d6a2f9e-9c66-4e3e-918c-d5f860dc152b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030914530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1030914530
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2393889801
Short name T539
Test name
Test status
Simulation time 250248634 ps
CPU time 4.57 seconds
Started Jun 27 04:43:51 PM PDT 24
Finished Jun 27 04:44:02 PM PDT 24
Peak memory 224676 kb
Host smart-ad010c6e-4ecd-4619-b620-bb94e2bd7d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393889801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2393889801
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3122081854
Short name T785
Test name
Test status
Simulation time 69711157 ps
CPU time 0.8 seconds
Started Jun 27 04:43:49 PM PDT 24
Finished Jun 27 04:43:53 PM PDT 24
Peak memory 206476 kb
Host smart-8b016799-868f-4871-bcd0-678bc6a764d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122081854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3122081854
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.65056502
Short name T753
Test name
Test status
Simulation time 5349009190 ps
CPU time 32.86 seconds
Started Jun 27 04:43:54 PM PDT 24
Finished Jun 27 04:44:35 PM PDT 24
Peak memory 252616 kb
Host smart-0c5b6273-d078-4a9b-bdad-4b22dc98a00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65056502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.65056502
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1907516195
Short name T437
Test name
Test status
Simulation time 3950464826 ps
CPU time 34.91 seconds
Started Jun 27 04:43:52 PM PDT 24
Finished Jun 27 04:44:35 PM PDT 24
Peak memory 238492 kb
Host smart-088d780e-7f66-4339-a4ec-26817af1bb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907516195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1907516195
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.442770404
Short name T467
Test name
Test status
Simulation time 26418541809 ps
CPU time 46.29 seconds
Started Jun 27 04:43:50 PM PDT 24
Finished Jun 27 04:44:41 PM PDT 24
Peak memory 240900 kb
Host smart-390d340b-5a5a-4786-8119-5bc8946ccd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442770404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.442770404
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1760893642
Short name T998
Test name
Test status
Simulation time 1363723437 ps
CPU time 10.31 seconds
Started Jun 27 04:43:49 PM PDT 24
Finished Jun 27 04:44:04 PM PDT 24
Peak memory 224316 kb
Host smart-c5188e29-af82-4af5-a7c5-608eb6859f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760893642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1760893642
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.1826907736
Short name T225
Test name
Test status
Simulation time 28151953643 ps
CPU time 85.94 seconds
Started Jun 27 04:43:52 PM PDT 24
Finished Jun 27 04:45:25 PM PDT 24
Peak memory 264744 kb
Host smart-cc32d931-e2c1-4415-bbd5-e140f998c0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826907736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.1826907736
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1865067025
Short name T658
Test name
Test status
Simulation time 397767797 ps
CPU time 6.95 seconds
Started Jun 27 04:43:47 PM PDT 24
Finished Jun 27 04:43:58 PM PDT 24
Peak memory 224312 kb
Host smart-bd911483-d57f-4f65-87ef-902d6d00fdf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865067025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1865067025
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2023685339
Short name T954
Test name
Test status
Simulation time 37052589790 ps
CPU time 97.1 seconds
Started Jun 27 04:43:52 PM PDT 24
Finished Jun 27 04:45:37 PM PDT 24
Peak memory 232740 kb
Host smart-14f7a6f9-13d6-4540-807c-6becd464cac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023685339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2023685339
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1131452886
Short name T26
Test name
Test status
Simulation time 1513916493 ps
CPU time 12.07 seconds
Started Jun 27 04:43:54 PM PDT 24
Finished Jun 27 04:44:15 PM PDT 24
Peak memory 248576 kb
Host smart-a6dc9181-3451-4ffa-9bba-d04adf972ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131452886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1131452886
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1425309603
Short name T675
Test name
Test status
Simulation time 1216405148 ps
CPU time 5.32 seconds
Started Jun 27 04:43:53 PM PDT 24
Finished Jun 27 04:44:06 PM PDT 24
Peak memory 232616 kb
Host smart-e43cce3c-14bc-42a3-b081-48e1da1b7a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425309603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1425309603
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3920898887
Short name T927
Test name
Test status
Simulation time 1029873469 ps
CPU time 5.2 seconds
Started Jun 27 04:43:52 PM PDT 24
Finished Jun 27 04:44:04 PM PDT 24
Peak memory 222480 kb
Host smart-90082d6d-e62a-4784-a55e-ea38b5b202ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3920898887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3920898887
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3812620046
Short name T825
Test name
Test status
Simulation time 153711510250 ps
CPU time 257.21 seconds
Started Jun 27 04:43:51 PM PDT 24
Finished Jun 27 04:48:15 PM PDT 24
Peak memory 251432 kb
Host smart-84d3ec00-5931-481e-89b3-8d4d460c4b3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812620046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3812620046
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3366761235
Short name T912
Test name
Test status
Simulation time 4059381088 ps
CPU time 21.13 seconds
Started Jun 27 04:43:52 PM PDT 24
Finished Jun 27 04:44:21 PM PDT 24
Peak memory 216212 kb
Host smart-8d7dc280-8f75-4339-aaf9-b8751c804ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366761235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3366761235
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3449264522
Short name T794
Test name
Test status
Simulation time 41812167488 ps
CPU time 9.19 seconds
Started Jun 27 04:43:51 PM PDT 24
Finished Jun 27 04:44:06 PM PDT 24
Peak memory 216208 kb
Host smart-0218c7a8-6231-4366-abc2-e47dad6e4e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449264522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3449264522
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1140507031
Short name T726
Test name
Test status
Simulation time 26735535 ps
CPU time 1.64 seconds
Started Jun 27 04:43:50 PM PDT 24
Finished Jun 27 04:43:57 PM PDT 24
Peak memory 216004 kb
Host smart-2dd3e5e4-3880-450e-aec0-fb51c3908779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140507031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1140507031
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.179545334
Short name T1021
Test name
Test status
Simulation time 116687583 ps
CPU time 1.02 seconds
Started Jun 27 04:43:52 PM PDT 24
Finished Jun 27 04:44:01 PM PDT 24
Peak memory 205808 kb
Host smart-55a550ec-e732-4a61-8010-f3a936dc6beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179545334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.179545334
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2433458925
Short name T603
Test name
Test status
Simulation time 10031791714 ps
CPU time 12.34 seconds
Started Jun 27 04:43:50 PM PDT 24
Finished Jun 27 04:44:06 PM PDT 24
Peak memory 224456 kb
Host smart-fa3f37fd-e89e-4040-b5ae-707fc029a165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433458925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2433458925
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3374850037
Short name T440
Test name
Test status
Simulation time 13900531 ps
CPU time 0.75 seconds
Started Jun 27 04:43:56 PM PDT 24
Finished Jun 27 04:44:05 PM PDT 24
Peak memory 204668 kb
Host smart-c84a61d1-274c-45a8-8439-6fd6faeab2d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374850037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3374850037
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1206458265
Short name T901
Test name
Test status
Simulation time 8990028293 ps
CPU time 11.24 seconds
Started Jun 27 04:43:55 PM PDT 24
Finished Jun 27 04:44:15 PM PDT 24
Peak memory 232656 kb
Host smart-d16347cb-47c8-471e-bea8-2c0a5523f376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206458265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1206458265
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1798927778
Short name T310
Test name
Test status
Simulation time 14201918 ps
CPU time 0.78 seconds
Started Jun 27 04:43:52 PM PDT 24
Finished Jun 27 04:44:00 PM PDT 24
Peak memory 206808 kb
Host smart-6030b63a-0bf9-48c0-b8ed-a59451652aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798927778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1798927778
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.4255446279
Short name T707
Test name
Test status
Simulation time 2312486538 ps
CPU time 50.48 seconds
Started Jun 27 04:43:54 PM PDT 24
Finished Jun 27 04:44:53 PM PDT 24
Peak memory 265436 kb
Host smart-bdafcaad-2bdf-4334-ac25-e945653f5fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255446279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.4255446279
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2920080785
Short name T216
Test name
Test status
Simulation time 56972157159 ps
CPU time 530.17 seconds
Started Jun 27 04:43:52 PM PDT 24
Finished Jun 27 04:52:50 PM PDT 24
Peak memory 257284 kb
Host smart-0f4c4e3e-91a7-4858-98bb-bc8a662ce6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920080785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2920080785
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3560003312
Short name T680
Test name
Test status
Simulation time 58664247678 ps
CPU time 239.24 seconds
Started Jun 27 04:43:55 PM PDT 24
Finished Jun 27 04:48:02 PM PDT 24
Peak memory 240636 kb
Host smart-deb02e70-c2dc-4249-98d4-7dde291385e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560003312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3560003312
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3981973055
Short name T346
Test name
Test status
Simulation time 283408380 ps
CPU time 5.75 seconds
Started Jun 27 04:43:55 PM PDT 24
Finished Jun 27 04:44:09 PM PDT 24
Peak memory 224392 kb
Host smart-06ab15a3-12da-460c-b14b-bdc7ae5cad54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981973055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3981973055
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.3321923917
Short name T845
Test name
Test status
Simulation time 7776308953 ps
CPU time 74.55 seconds
Started Jun 27 04:43:57 PM PDT 24
Finished Jun 27 04:45:19 PM PDT 24
Peak memory 248744 kb
Host smart-46ecd11c-3a35-4250-a7f0-e3ad22e5cad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321923917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.3321923917
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2329062924
Short name T202
Test name
Test status
Simulation time 2860173832 ps
CPU time 16.58 seconds
Started Jun 27 04:43:51 PM PDT 24
Finished Jun 27 04:44:14 PM PDT 24
Peak memory 224436 kb
Host smart-6077142d-b7b5-43ae-978d-d27928b89f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329062924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2329062924
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3855302786
Short name T673
Test name
Test status
Simulation time 14977710170 ps
CPU time 42.14 seconds
Started Jun 27 04:43:58 PM PDT 24
Finished Jun 27 04:44:48 PM PDT 24
Peak memory 232676 kb
Host smart-d9bc99b8-9359-4cda-bc5d-b1d185045787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855302786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3855302786
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1591104551
Short name T479
Test name
Test status
Simulation time 3728562835 ps
CPU time 11.71 seconds
Started Jun 27 04:43:53 PM PDT 24
Finished Jun 27 04:44:12 PM PDT 24
Peak memory 239220 kb
Host smart-efe36215-e23f-4e43-a459-da37d0b627df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591104551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1591104551
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.446452855
Short name T966
Test name
Test status
Simulation time 188157130 ps
CPU time 2.11 seconds
Started Jun 27 04:43:48 PM PDT 24
Finished Jun 27 04:43:54 PM PDT 24
Peak memory 224004 kb
Host smart-a315d2b2-e820-4ea1-97b6-4bd31528cd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446452855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.446452855
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3060204264
Short name T796
Test name
Test status
Simulation time 5027252061 ps
CPU time 11.12 seconds
Started Jun 27 04:43:54 PM PDT 24
Finished Jun 27 04:44:14 PM PDT 24
Peak memory 223248 kb
Host smart-5045dca9-3e99-4707-ab9a-6cba3e68cc4b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3060204264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3060204264
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.282467467
Short name T56
Test name
Test status
Simulation time 91734195166 ps
CPU time 309 seconds
Started Jun 27 04:43:57 PM PDT 24
Finished Jun 27 04:49:14 PM PDT 24
Peak memory 298212 kb
Host smart-0cc4ceea-1946-4bfc-8586-eafc75e28365
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282467467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.282467467
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2674673797
Short name T745
Test name
Test status
Simulation time 4854785955 ps
CPU time 30.2 seconds
Started Jun 27 04:43:52 PM PDT 24
Finished Jun 27 04:44:29 PM PDT 24
Peak memory 216456 kb
Host smart-3fc91322-030d-4cd4-a341-998c98afef29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674673797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2674673797
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.905595289
Short name T748
Test name
Test status
Simulation time 16090498561 ps
CPU time 14.13 seconds
Started Jun 27 04:43:52 PM PDT 24
Finished Jun 27 04:44:13 PM PDT 24
Peak memory 216184 kb
Host smart-20bef548-96c3-4fa3-addc-1e106440898f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905595289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.905595289
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1842203216
Short name T887
Test name
Test status
Simulation time 531210230 ps
CPU time 1.57 seconds
Started Jun 27 04:43:52 PM PDT 24
Finished Jun 27 04:44:01 PM PDT 24
Peak memory 216076 kb
Host smart-590f7afb-fa26-456b-89b2-8432368fe484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842203216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1842203216
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2746095029
Short name T708
Test name
Test status
Simulation time 32949756 ps
CPU time 0.82 seconds
Started Jun 27 04:43:51 PM PDT 24
Finished Jun 27 04:43:58 PM PDT 24
Peak memory 206100 kb
Host smart-982c3f7c-3b18-4638-9b98-1e0c74145152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746095029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2746095029
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3173876644
Short name T392
Test name
Test status
Simulation time 21212584647 ps
CPU time 11.96 seconds
Started Jun 27 04:43:57 PM PDT 24
Finished Jun 27 04:44:17 PM PDT 24
Peak memory 232228 kb
Host smart-abf36273-7d83-49b0-ad59-c96cd36af683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173876644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3173876644
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3052025568
Short name T827
Test name
Test status
Simulation time 17104457 ps
CPU time 0.75 seconds
Started Jun 27 04:44:00 PM PDT 24
Finished Jun 27 04:44:09 PM PDT 24
Peak memory 205312 kb
Host smart-d814afe9-5fcd-462d-ad9d-a80ee71a06dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052025568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3052025568
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.4264568745
Short name T77
Test name
Test status
Simulation time 31928299 ps
CPU time 2.38 seconds
Started Jun 27 04:44:00 PM PDT 24
Finished Jun 27 04:44:10 PM PDT 24
Peak memory 232304 kb
Host smart-6a344184-3798-4cab-a0f9-e3048fea0667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264568745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.4264568745
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3739136937
Short name T782
Test name
Test status
Simulation time 90326682 ps
CPU time 0.8 seconds
Started Jun 27 04:43:58 PM PDT 24
Finished Jun 27 04:44:07 PM PDT 24
Peak memory 206388 kb
Host smart-6499bfe7-fb6a-4723-a8e7-31063f89d69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739136937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3739136937
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1573869815
Short name T184
Test name
Test status
Simulation time 376896029213 ps
CPU time 381.77 seconds
Started Jun 27 04:44:00 PM PDT 24
Finished Jun 27 04:50:29 PM PDT 24
Peak memory 263200 kb
Host smart-431c7297-272c-4d82-bc22-f75e9a3ebbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573869815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1573869815
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.321887109
Short name T54
Test name
Test status
Simulation time 101467723797 ps
CPU time 514.37 seconds
Started Jun 27 04:43:53 PM PDT 24
Finished Jun 27 04:52:35 PM PDT 24
Peak memory 256824 kb
Host smart-5e3cf5d9-425e-4d7a-a5a8-45659fd2c0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321887109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.321887109
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3318500753
Short name T204
Test name
Test status
Simulation time 41991291278 ps
CPU time 231.73 seconds
Started Jun 27 04:43:59 PM PDT 24
Finished Jun 27 04:47:58 PM PDT 24
Peak memory 271696 kb
Host smart-f2aa042a-e47e-40a8-b5fd-d7b525b18b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318500753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3318500753
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1346615054
Short name T276
Test name
Test status
Simulation time 284450157 ps
CPU time 7.97 seconds
Started Jun 27 04:44:00 PM PDT 24
Finished Jun 27 04:44:15 PM PDT 24
Peak memory 232600 kb
Host smart-93b2a8b8-1bdd-42aa-989f-2e9d11dfd96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346615054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1346615054
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.3659319462
Short name T600
Test name
Test status
Simulation time 18489414664 ps
CPU time 140.46 seconds
Started Jun 27 04:44:00 PM PDT 24
Finished Jun 27 04:46:28 PM PDT 24
Peak memory 252400 kb
Host smart-40f99407-d371-43b1-9284-f164163abc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659319462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.3659319462
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.137422927
Short name T697
Test name
Test status
Simulation time 700557616 ps
CPU time 7.39 seconds
Started Jun 27 04:43:57 PM PDT 24
Finished Jun 27 04:44:12 PM PDT 24
Peak memory 224272 kb
Host smart-6bac4579-887d-4b8b-8232-20411957c3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137422927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.137422927
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2458639565
Short name T76
Test name
Test status
Simulation time 6652372761 ps
CPU time 46.53 seconds
Started Jun 27 04:43:57 PM PDT 24
Finished Jun 27 04:44:51 PM PDT 24
Peak memory 250028 kb
Host smart-5163bcd5-5e86-4aaa-af8f-895522201e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458639565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2458639565
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2645782277
Short name T244
Test name
Test status
Simulation time 3031225154 ps
CPU time 12.79 seconds
Started Jun 27 04:43:57 PM PDT 24
Finished Jun 27 04:44:17 PM PDT 24
Peak memory 240688 kb
Host smart-c79e3e56-cb34-4ee7-9c96-5b6c068525b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645782277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2645782277
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.719979483
Short name T990
Test name
Test status
Simulation time 150277814 ps
CPU time 2.08 seconds
Started Jun 27 04:43:59 PM PDT 24
Finished Jun 27 04:44:09 PM PDT 24
Peak memory 224132 kb
Host smart-75ba44b3-310b-4b1e-a16b-96a43c428a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719979483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.719979483
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1116704764
Short name T508
Test name
Test status
Simulation time 2274534823 ps
CPU time 6.53 seconds
Started Jun 27 04:44:01 PM PDT 24
Finished Jun 27 04:44:15 PM PDT 24
Peak memory 220088 kb
Host smart-d5f950a2-0540-4254-a431-dceda2097be1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1116704764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1116704764
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1665112134
Short name T857
Test name
Test status
Simulation time 174157792012 ps
CPU time 130.64 seconds
Started Jun 27 04:44:00 PM PDT 24
Finished Jun 27 04:46:19 PM PDT 24
Peak memory 257124 kb
Host smart-a179c24b-2120-4196-9daa-1a65d5814358
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665112134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1665112134
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1411263492
Short name T773
Test name
Test status
Simulation time 949094078 ps
CPU time 8.35 seconds
Started Jun 27 04:43:52 PM PDT 24
Finished Jun 27 04:44:08 PM PDT 24
Peak memory 216176 kb
Host smart-beb6a50e-4fe8-4750-b35f-bc9633ae6b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411263492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1411263492
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.987448785
Short name T659
Test name
Test status
Simulation time 836703122 ps
CPU time 2.11 seconds
Started Jun 27 04:43:58 PM PDT 24
Finished Jun 27 04:44:08 PM PDT 24
Peak memory 216016 kb
Host smart-df7f0257-6106-48ab-9f61-c8115a0b3e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987448785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.987448785
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1453184144
Short name T38
Test name
Test status
Simulation time 247164117 ps
CPU time 1.18 seconds
Started Jun 27 04:43:58 PM PDT 24
Finished Jun 27 04:44:07 PM PDT 24
Peak memory 215928 kb
Host smart-269e41e9-670a-4791-8689-76cf3d61bb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453184144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1453184144
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2216665891
Short name T629
Test name
Test status
Simulation time 30415772 ps
CPU time 0.8 seconds
Started Jun 27 04:43:59 PM PDT 24
Finished Jun 27 04:44:07 PM PDT 24
Peak memory 205780 kb
Host smart-24edd425-721f-45ec-80ae-6fd4ca94ec20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216665891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2216665891
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2395581377
Short name T997
Test name
Test status
Simulation time 8098241428 ps
CPU time 30.37 seconds
Started Jun 27 04:44:01 PM PDT 24
Finished Jun 27 04:44:39 PM PDT 24
Peak memory 240832 kb
Host smart-7a4cc197-a7a7-491c-b915-7ea3119542bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395581377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2395581377
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.215411640
Short name T958
Test name
Test status
Simulation time 11860982 ps
CPU time 0.72 seconds
Started Jun 27 04:44:01 PM PDT 24
Finished Jun 27 04:44:09 PM PDT 24
Peak memory 205244 kb
Host smart-654edd66-547f-4a30-b031-32b9230f1e3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215411640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.215411640
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.570904248
Short name T742
Test name
Test status
Simulation time 342076693 ps
CPU time 3.59 seconds
Started Jun 27 04:43:54 PM PDT 24
Finished Jun 27 04:44:05 PM PDT 24
Peak memory 232580 kb
Host smart-af7bc186-810f-442f-95be-408ca8ba831f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570904248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.570904248
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.833066408
Short name T820
Test name
Test status
Simulation time 32217291 ps
CPU time 0.78 seconds
Started Jun 27 04:44:01 PM PDT 24
Finished Jun 27 04:44:09 PM PDT 24
Peak memory 206448 kb
Host smart-091f56f2-d855-41b3-bd6f-19575a9dca98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833066408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.833066408
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1815897078
Short name T231
Test name
Test status
Simulation time 7673629335 ps
CPU time 72.66 seconds
Started Jun 27 04:43:54 PM PDT 24
Finished Jun 27 04:45:15 PM PDT 24
Peak memory 249000 kb
Host smart-b9c2ec48-212b-4e68-90f4-7eaf8c37fb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815897078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1815897078
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.4063134160
Short name T286
Test name
Test status
Simulation time 161741624380 ps
CPU time 156.47 seconds
Started Jun 27 04:43:54 PM PDT 24
Finished Jun 27 04:46:38 PM PDT 24
Peak memory 240652 kb
Host smart-83189b78-e4ae-4b0c-910d-f6392cd9893c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063134160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.4063134160
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.319951725
Short name T884
Test name
Test status
Simulation time 10375859702 ps
CPU time 76.79 seconds
Started Jun 27 04:43:59 PM PDT 24
Finished Jun 27 04:45:24 PM PDT 24
Peak memory 239816 kb
Host smart-5cbff8e2-939b-41b3-9afd-94206d81011e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319951725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.319951725
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2640144711
Short name T704
Test name
Test status
Simulation time 545394595 ps
CPU time 8.36 seconds
Started Jun 27 04:44:01 PM PDT 24
Finished Jun 27 04:44:17 PM PDT 24
Peak memory 224280 kb
Host smart-65233952-ad23-4c00-9412-236bf3140da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640144711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2640144711
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.1478251017
Short name T992
Test name
Test status
Simulation time 4955834608 ps
CPU time 33.38 seconds
Started Jun 27 04:43:54 PM PDT 24
Finished Jun 27 04:44:35 PM PDT 24
Peak memory 237256 kb
Host smart-421a0c3c-f974-4f05-a9cc-6c566f3b5806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478251017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.1478251017
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.481125110
Short name T879
Test name
Test status
Simulation time 631442291 ps
CPU time 10.52 seconds
Started Jun 27 04:43:59 PM PDT 24
Finished Jun 27 04:44:17 PM PDT 24
Peak memory 224284 kb
Host smart-2f222367-9318-4c65-a4f7-5e1adfc76fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481125110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.481125110
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1495699563
Short name T642
Test name
Test status
Simulation time 516160020 ps
CPU time 6.58 seconds
Started Jun 27 04:43:51 PM PDT 24
Finished Jun 27 04:44:04 PM PDT 24
Peak memory 232492 kb
Host smart-9388c027-78a1-4e86-8627-39a18188fcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495699563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1495699563
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1674350779
Short name T465
Test name
Test status
Simulation time 900623803 ps
CPU time 3.37 seconds
Started Jun 27 04:44:01 PM PDT 24
Finished Jun 27 04:44:12 PM PDT 24
Peak memory 224328 kb
Host smart-3ec9c519-6270-40da-a81f-387f52aeb872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674350779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1674350779
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.173326918
Short name T155
Test name
Test status
Simulation time 2995415697 ps
CPU time 11.18 seconds
Started Jun 27 04:43:59 PM PDT 24
Finished Jun 27 04:44:18 PM PDT 24
Peak memory 240056 kb
Host smart-c42d77f4-4686-43df-8de5-65ab084d69d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173326918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.173326918
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2367318744
Short name T518
Test name
Test status
Simulation time 3717697909 ps
CPU time 8.75 seconds
Started Jun 27 04:43:50 PM PDT 24
Finished Jun 27 04:44:04 PM PDT 24
Peak memory 218820 kb
Host smart-b4ace9e0-3e21-4986-8318-2830556fba09
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2367318744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2367318744
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3108064882
Short name T783
Test name
Test status
Simulation time 10384319753 ps
CPU time 58.08 seconds
Started Jun 27 04:43:50 PM PDT 24
Finished Jun 27 04:44:51 PM PDT 24
Peak memory 249412 kb
Host smart-0acbd62d-069d-4bd0-b01c-8799398587c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108064882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3108064882
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3828228910
Short name T393
Test name
Test status
Simulation time 1314573568 ps
CPU time 5.16 seconds
Started Jun 27 04:43:54 PM PDT 24
Finished Jun 27 04:44:08 PM PDT 24
Peak memory 216008 kb
Host smart-14047f08-0e83-442f-8bb4-38fc35e8ecfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828228910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3828228910
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2384970670
Short name T552
Test name
Test status
Simulation time 630917191 ps
CPU time 4.98 seconds
Started Jun 27 04:43:59 PM PDT 24
Finished Jun 27 04:44:12 PM PDT 24
Peak memory 215496 kb
Host smart-fdaf7137-ccb1-4d51-af3a-e22aa463d448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384970670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2384970670
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2088798392
Short name T766
Test name
Test status
Simulation time 152194011 ps
CPU time 1.5 seconds
Started Jun 27 04:43:59 PM PDT 24
Finished Jun 27 04:44:08 PM PDT 24
Peak memory 215704 kb
Host smart-9fa57a7a-613e-4304-80c8-4edabfe96b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088798392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2088798392
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2599701149
Short name T370
Test name
Test status
Simulation time 56357936 ps
CPU time 0.75 seconds
Started Jun 27 04:43:59 PM PDT 24
Finished Jun 27 04:44:07 PM PDT 24
Peak memory 205584 kb
Host smart-949f5fcb-96ef-4fbb-bb62-061f2fff7cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599701149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2599701149
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.4262160983
Short name T851
Test name
Test status
Simulation time 33341392 ps
CPU time 2.59 seconds
Started Jun 27 04:43:51 PM PDT 24
Finished Jun 27 04:44:00 PM PDT 24
Peak memory 232564 kb
Host smart-ffa9043a-b672-4081-bce5-690b653f991d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262160983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.4262160983
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.4113012410
Short name T872
Test name
Test status
Simulation time 40037721 ps
CPU time 0.74 seconds
Started Jun 27 04:44:01 PM PDT 24
Finished Jun 27 04:44:09 PM PDT 24
Peak memory 205296 kb
Host smart-424393e5-0c3e-4295-a3c2-441a007a64ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113012410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
4113012410
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3075774253
Short name T226
Test name
Test status
Simulation time 394501830 ps
CPU time 4.3 seconds
Started Jun 27 04:43:51 PM PDT 24
Finished Jun 27 04:44:01 PM PDT 24
Peak memory 224416 kb
Host smart-38631e42-9336-41ea-8558-483293751c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075774253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3075774253
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2501453848
Short name T836
Test name
Test status
Simulation time 51706595 ps
CPU time 0.76 seconds
Started Jun 27 04:43:55 PM PDT 24
Finished Jun 27 04:44:04 PM PDT 24
Peak memory 206804 kb
Host smart-3f6619e4-21f2-428e-9079-5240188c3021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501453848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2501453848
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3010656472
Short name T882
Test name
Test status
Simulation time 90718858926 ps
CPU time 168.61 seconds
Started Jun 27 04:43:51 PM PDT 24
Finished Jun 27 04:46:45 PM PDT 24
Peak memory 255076 kb
Host smart-c9a84170-c659-48b1-830d-7c4cdfa18716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010656472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3010656472
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1586960286
Short name T32
Test name
Test status
Simulation time 41341604724 ps
CPU time 190.13 seconds
Started Jun 27 04:43:58 PM PDT 24
Finished Jun 27 04:47:16 PM PDT 24
Peak memory 263932 kb
Host smart-72d07c82-8192-4a12-8017-ed69c8ca9bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586960286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1586960286
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2437444328
Short name T263
Test name
Test status
Simulation time 7298244955 ps
CPU time 24.27 seconds
Started Jun 27 04:43:59 PM PDT 24
Finished Jun 27 04:44:31 PM PDT 24
Peak memory 249864 kb
Host smart-f7dc63b9-8e25-469a-9d5f-99f18c0e9524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437444328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2437444328
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1768534331
Short name T1023
Test name
Test status
Simulation time 577610757 ps
CPU time 3.87 seconds
Started Jun 27 04:43:55 PM PDT 24
Finished Jun 27 04:44:08 PM PDT 24
Peak memory 232572 kb
Host smart-a767294e-3917-4f2c-9469-ee6d634e65bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768534331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1768534331
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.2324130518
Short name T255
Test name
Test status
Simulation time 2996473128 ps
CPU time 53.83 seconds
Started Jun 27 04:43:51 PM PDT 24
Finished Jun 27 04:44:52 PM PDT 24
Peak memory 257276 kb
Host smart-ad135110-9d1d-4d8d-9bb2-8276267b1a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324130518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.2324130518
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.399179815
Short name T308
Test name
Test status
Simulation time 31917631 ps
CPU time 2.08 seconds
Started Jun 27 04:43:58 PM PDT 24
Finished Jun 27 04:44:08 PM PDT 24
Peak memory 223456 kb
Host smart-11a8b3f3-f91a-4a97-841c-3fd6c74af4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399179815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.399179815
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1310205604
Short name T832
Test name
Test status
Simulation time 4395848442 ps
CPU time 18.23 seconds
Started Jun 27 04:43:56 PM PDT 24
Finished Jun 27 04:44:23 PM PDT 24
Peak memory 232636 kb
Host smart-a8c21769-3301-4c76-857b-d87b1b8e9d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310205604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1310205604
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.696303678
Short name T156
Test name
Test status
Simulation time 214934967 ps
CPU time 2.14 seconds
Started Jun 27 04:43:55 PM PDT 24
Finished Jun 27 04:44:05 PM PDT 24
Peak memory 224360 kb
Host smart-13ab30b7-260f-4222-8bb4-60f38699290c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696303678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.696303678
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2142803312
Short name T973
Test name
Test status
Simulation time 7210567603 ps
CPU time 12.84 seconds
Started Jun 27 04:43:51 PM PDT 24
Finished Jun 27 04:44:11 PM PDT 24
Peak memory 234240 kb
Host smart-c323034c-512b-4336-8610-2d194139a0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142803312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2142803312
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1932053482
Short name T677
Test name
Test status
Simulation time 532445471 ps
CPU time 4.25 seconds
Started Jun 27 04:43:59 PM PDT 24
Finished Jun 27 04:44:11 PM PDT 24
Peak memory 221824 kb
Host smart-ad037ac7-3df8-4019-917a-c1c0c1f54ca9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1932053482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1932053482
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2543954973
Short name T562
Test name
Test status
Simulation time 3172011027 ps
CPU time 48.96 seconds
Started Jun 27 04:43:59 PM PDT 24
Finished Jun 27 04:44:56 PM PDT 24
Peak memory 240812 kb
Host smart-89121a18-d6f1-42d7-97cb-4dac4d59d201
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543954973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2543954973
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2242500431
Short name T694
Test name
Test status
Simulation time 5027513798 ps
CPU time 18.89 seconds
Started Jun 27 04:43:52 PM PDT 24
Finished Jun 27 04:44:19 PM PDT 24
Peak memory 219780 kb
Host smart-86d63f0d-61e3-4cc5-a896-b7f57db3dec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242500431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2242500431
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.588428178
Short name T306
Test name
Test status
Simulation time 31236577012 ps
CPU time 19.55 seconds
Started Jun 27 04:43:55 PM PDT 24
Finished Jun 27 04:44:23 PM PDT 24
Peak memory 217444 kb
Host smart-37e58547-7c39-4aa6-8bdc-b5d907b01ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588428178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.588428178
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3899773733
Short name T596
Test name
Test status
Simulation time 25719511 ps
CPU time 1.05 seconds
Started Jun 27 04:43:55 PM PDT 24
Finished Jun 27 04:44:05 PM PDT 24
Peak memory 206936 kb
Host smart-5fd72685-f571-402b-b567-e37220795fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899773733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3899773733
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2659560871
Short name T736
Test name
Test status
Simulation time 23975722 ps
CPU time 0.8 seconds
Started Jun 27 04:43:54 PM PDT 24
Finished Jun 27 04:44:03 PM PDT 24
Peak memory 205676 kb
Host smart-dacfbbad-8dc1-4f74-8657-54694af5d2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659560871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2659560871
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2206803358
Short name T702
Test name
Test status
Simulation time 2335130961 ps
CPU time 9.32 seconds
Started Jun 27 04:43:55 PM PDT 24
Finished Jun 27 04:44:12 PM PDT 24
Peak memory 232680 kb
Host smart-5e69a0fd-f71f-4eaa-bb99-3a3b36b2876f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206803358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2206803358
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1660649578
Short name T770
Test name
Test status
Simulation time 55750789 ps
CPU time 0.7 seconds
Started Jun 27 04:44:09 PM PDT 24
Finished Jun 27 04:44:16 PM PDT 24
Peak memory 204664 kb
Host smart-f14cebcf-12c9-4eac-86d8-79c416cdae6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660649578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1660649578
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3733309068
Short name T545
Test name
Test status
Simulation time 626521657 ps
CPU time 2.67 seconds
Started Jun 27 04:43:54 PM PDT 24
Finished Jun 27 04:44:04 PM PDT 24
Peak memory 224396 kb
Host smart-919e732e-ea08-4c19-b67e-3b60926468c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733309068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3733309068
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.555542035
Short name T307
Test name
Test status
Simulation time 14749279 ps
CPU time 0.85 seconds
Started Jun 27 04:44:00 PM PDT 24
Finished Jun 27 04:44:08 PM PDT 24
Peak memory 206784 kb
Host smart-cd515ca0-caa4-4d07-9349-c3fdf6469283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555542035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.555542035
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1924126268
Short name T525
Test name
Test status
Simulation time 13914863888 ps
CPU time 102.37 seconds
Started Jun 27 04:44:07 PM PDT 24
Finished Jun 27 04:45:56 PM PDT 24
Peak memory 252024 kb
Host smart-965946be-3906-4f30-a204-e7dec17b5199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924126268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1924126268
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.392582150
Short name T292
Test name
Test status
Simulation time 1934540510 ps
CPU time 33.45 seconds
Started Jun 27 04:44:05 PM PDT 24
Finished Jun 27 04:44:46 PM PDT 24
Peak memory 249088 kb
Host smart-eb82ec22-2ab0-448d-b338-ec3a1b0fd5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392582150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.392582150
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.626393916
Short name T972
Test name
Test status
Simulation time 32878305645 ps
CPU time 195.31 seconds
Started Jun 27 04:44:04 PM PDT 24
Finished Jun 27 04:47:26 PM PDT 24
Peak memory 263940 kb
Host smart-5f9835e8-359a-44f5-add0-ad9a814b84ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626393916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.626393916
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.170984280
Short name T907
Test name
Test status
Simulation time 7410958712 ps
CPU time 7.97 seconds
Started Jun 27 04:43:54 PM PDT 24
Finished Jun 27 04:44:10 PM PDT 24
Peak memory 236280 kb
Host smart-2a966957-b6ef-429a-b6e2-2972f1982089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170984280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.170984280
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.720384277
Short name T176
Test name
Test status
Simulation time 221616963658 ps
CPU time 396.31 seconds
Started Jun 27 04:44:07 PM PDT 24
Finished Jun 27 04:50:50 PM PDT 24
Peak memory 265456 kb
Host smart-4833f7d4-1999-4cd8-a939-c55a1893943f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720384277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds
.720384277
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3646748702
Short name T359
Test name
Test status
Simulation time 90675466 ps
CPU time 2.42 seconds
Started Jun 27 04:44:00 PM PDT 24
Finished Jun 27 04:44:10 PM PDT 24
Peak memory 232304 kb
Host smart-3d457cc5-c15d-44e9-a2be-3146a047c8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646748702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3646748702
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2694771316
Short name T474
Test name
Test status
Simulation time 576051568 ps
CPU time 2.42 seconds
Started Jun 27 04:43:59 PM PDT 24
Finished Jun 27 04:44:09 PM PDT 24
Peak memory 224340 kb
Host smart-56a0cc2a-3613-427f-8a0d-ffef21887361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694771316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2694771316
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1087937797
Short name T646
Test name
Test status
Simulation time 617113445 ps
CPU time 6.07 seconds
Started Jun 27 04:44:01 PM PDT 24
Finished Jun 27 04:44:15 PM PDT 24
Peak memory 239988 kb
Host smart-53a7f551-6ce5-4a93-aed5-9d44b8a16b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087937797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1087937797
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3078994876
Short name T888
Test name
Test status
Simulation time 86042559 ps
CPU time 2.25 seconds
Started Jun 27 04:43:59 PM PDT 24
Finished Jun 27 04:44:09 PM PDT 24
Peak memory 224356 kb
Host smart-c929aafd-c0b2-4641-924b-e9c38675a24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078994876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3078994876
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3622580404
Short name T1011
Test name
Test status
Simulation time 1037496284 ps
CPU time 8.89 seconds
Started Jun 27 04:44:05 PM PDT 24
Finished Jun 27 04:44:21 PM PDT 24
Peak memory 220024 kb
Host smart-47e0e372-984c-43cb-a61b-52e614b30194
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3622580404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3622580404
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3350070722
Short name T1022
Test name
Test status
Simulation time 58919660393 ps
CPU time 373.48 seconds
Started Jun 27 04:44:09 PM PDT 24
Finished Jun 27 04:50:29 PM PDT 24
Peak memory 257312 kb
Host smart-dcb39a9c-7112-4a10-8427-85ddc7c5c08d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350070722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3350070722
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.442707091
Short name T394
Test name
Test status
Simulation time 661174309 ps
CPU time 4.79 seconds
Started Jun 27 04:43:59 PM PDT 24
Finished Jun 27 04:44:11 PM PDT 24
Peak memory 216140 kb
Host smart-1af6fb9c-703b-4f1d-aed9-dac9582653a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442707091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.442707091
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.294373327
Short name T507
Test name
Test status
Simulation time 10461444734 ps
CPU time 14.15 seconds
Started Jun 27 04:44:01 PM PDT 24
Finished Jun 27 04:44:23 PM PDT 24
Peak memory 216208 kb
Host smart-dcb0abb4-86aa-469b-8e11-dc1dbc4c5484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294373327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.294373327
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3844233143
Short name T385
Test name
Test status
Simulation time 590723549 ps
CPU time 2.11 seconds
Started Jun 27 04:43:59 PM PDT 24
Finished Jun 27 04:44:09 PM PDT 24
Peak memory 216108 kb
Host smart-aeee602e-da55-454f-b465-f2560f30e0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844233143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3844233143
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1471767001
Short name T316
Test name
Test status
Simulation time 17598780 ps
CPU time 0.72 seconds
Started Jun 27 04:43:53 PM PDT 24
Finished Jun 27 04:44:02 PM PDT 24
Peak memory 205744 kb
Host smart-42479120-0a12-4f34-88e6-3f8e811604ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471767001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1471767001
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2042831654
Short name T991
Test name
Test status
Simulation time 3885589488 ps
CPU time 13.91 seconds
Started Jun 27 04:43:56 PM PDT 24
Finished Jun 27 04:44:18 PM PDT 24
Peak memory 232748 kb
Host smart-573cc380-ad41-4fce-a7e4-aedfa5da71ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042831654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2042831654
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.4202837917
Short name T653
Test name
Test status
Simulation time 11768623 ps
CPU time 0.73 seconds
Started Jun 27 04:41:42 PM PDT 24
Finished Jun 27 04:41:49 PM PDT 24
Peak memory 205636 kb
Host smart-ef5558cd-e34a-4a11-a9f8-d0b3cfc7f53b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202837917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.4
202837917
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2573467514
Short name T844
Test name
Test status
Simulation time 638181803 ps
CPU time 5.67 seconds
Started Jun 27 04:41:38 PM PDT 24
Finished Jun 27 04:41:46 PM PDT 24
Peak memory 224308 kb
Host smart-bcb1c348-f904-463b-9b72-4fd6456045a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573467514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2573467514
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2460915605
Short name T576
Test name
Test status
Simulation time 99939917 ps
CPU time 0.82 seconds
Started Jun 27 04:41:40 PM PDT 24
Finished Jun 27 04:41:44 PM PDT 24
Peak memory 205732 kb
Host smart-e5e6b772-d987-4b2f-9cac-5d3000ccb2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460915605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2460915605
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1404135687
Short name T894
Test name
Test status
Simulation time 4339796535 ps
CPU time 13.32 seconds
Started Jun 27 04:41:43 PM PDT 24
Finished Jun 27 04:42:02 PM PDT 24
Peak memory 232708 kb
Host smart-809d0f7e-e66c-4585-a6c8-55472916734c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404135687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1404135687
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3074445015
Short name T533
Test name
Test status
Simulation time 2338867934 ps
CPU time 23.03 seconds
Started Jun 27 04:41:44 PM PDT 24
Finished Jun 27 04:42:14 PM PDT 24
Peak memory 223452 kb
Host smart-321b055c-7e14-4995-871e-e5013f89f6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074445015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3074445015
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1279690581
Short name T160
Test name
Test status
Simulation time 6927169944 ps
CPU time 90.71 seconds
Started Jun 27 04:41:42 PM PDT 24
Finished Jun 27 04:43:17 PM PDT 24
Peak memory 249120 kb
Host smart-f04631fb-39ec-48f4-be64-ee4b3891371c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279690581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1279690581
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1334546149
Short name T319
Test name
Test status
Simulation time 5178973827 ps
CPU time 64.58 seconds
Started Jun 27 04:41:43 PM PDT 24
Finished Jun 27 04:42:54 PM PDT 24
Peak memory 253064 kb
Host smart-6d82f74a-90b6-4551-97c6-fd2363e5a550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334546149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1334546149
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2926990278
Short name T1019
Test name
Test status
Simulation time 9640179049 ps
CPU time 31.35 seconds
Started Jun 27 04:41:40 PM PDT 24
Finished Jun 27 04:42:15 PM PDT 24
Peak memory 240868 kb
Host smart-dbea9ff8-7869-4888-a159-097571558c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926990278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2926990278
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2082330410
Short name T404
Test name
Test status
Simulation time 1217200118 ps
CPU time 15.32 seconds
Started Jun 27 04:41:39 PM PDT 24
Finished Jun 27 04:41:57 PM PDT 24
Peak memory 224420 kb
Host smart-618042fd-4bb6-4d1a-9001-ac5cdc2c2487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082330410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2082330410
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1468351622
Short name T191
Test name
Test status
Simulation time 3495370969 ps
CPU time 38.61 seconds
Started Jun 27 04:41:40 PM PDT 24
Finished Jun 27 04:42:22 PM PDT 24
Peak memory 240288 kb
Host smart-9bfee7a2-1663-4f00-bc9d-5b0f4e33a1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468351622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1468351622
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.4201540790
Short name T416
Test name
Test status
Simulation time 16644990 ps
CPU time 1.15 seconds
Started Jun 27 04:41:35 PM PDT 24
Finished Jun 27 04:41:38 PM PDT 24
Peak memory 216636 kb
Host smart-1fb1f8e6-7403-4b9c-b734-245fcafe37e6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201540790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.4201540790
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3674428306
Short name T237
Test name
Test status
Simulation time 1487353989 ps
CPU time 5.19 seconds
Started Jun 27 04:41:36 PM PDT 24
Finished Jun 27 04:41:43 PM PDT 24
Peak memory 232512 kb
Host smart-4a15a1e6-09c8-4a9a-9c6b-9db3d2e803fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674428306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3674428306
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.630143872
Short name T201
Test name
Test status
Simulation time 11296569796 ps
CPU time 31.52 seconds
Started Jun 27 04:41:42 PM PDT 24
Finished Jun 27 04:42:19 PM PDT 24
Peak memory 232616 kb
Host smart-45bc32ce-d624-4a75-b39b-fa5abfe1b6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630143872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.630143872
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2269749523
Short name T355
Test name
Test status
Simulation time 425114056 ps
CPU time 4.19 seconds
Started Jun 27 04:41:38 PM PDT 24
Finished Jun 27 04:41:45 PM PDT 24
Peak memory 222868 kb
Host smart-e0e61b4b-d781-40d5-9fa8-76e23da05ffe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2269749523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2269749523
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1708984950
Short name T611
Test name
Test status
Simulation time 26855758028 ps
CPU time 257.12 seconds
Started Jun 27 04:41:36 PM PDT 24
Finished Jun 27 04:45:54 PM PDT 24
Peak memory 251240 kb
Host smart-887d4d65-dadd-45a8-97d8-4e5f78f6eefc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708984950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1708984950
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1197271947
Short name T897
Test name
Test status
Simulation time 2502422720 ps
CPU time 25.05 seconds
Started Jun 27 04:41:44 PM PDT 24
Finished Jun 27 04:42:16 PM PDT 24
Peak memory 216276 kb
Host smart-ef2ef198-c41b-4385-9132-0ab681e7f0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197271947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1197271947
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2592945448
Short name T939
Test name
Test status
Simulation time 3807446135 ps
CPU time 5.52 seconds
Started Jun 27 04:41:40 PM PDT 24
Finished Jun 27 04:41:49 PM PDT 24
Peak memory 216156 kb
Host smart-be07a525-5d41-43de-b1ce-2b84e11ccbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592945448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2592945448
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2988580483
Short name T302
Test name
Test status
Simulation time 163870552 ps
CPU time 2.26 seconds
Started Jun 27 04:41:43 PM PDT 24
Finished Jun 27 04:41:51 PM PDT 24
Peak memory 216080 kb
Host smart-d2b6e425-0561-40fe-9a39-564aaba8ae9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988580483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2988580483
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1090119589
Short name T961
Test name
Test status
Simulation time 92511489 ps
CPU time 0.76 seconds
Started Jun 27 04:41:42 PM PDT 24
Finished Jun 27 04:41:46 PM PDT 24
Peak memory 205724 kb
Host smart-87c27b87-e7cf-4954-9b1a-75db0fdf0852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090119589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1090119589
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1831006093
Short name T718
Test name
Test status
Simulation time 435918459 ps
CPU time 6.81 seconds
Started Jun 27 04:41:42 PM PDT 24
Finished Jun 27 04:41:53 PM PDT 24
Peak memory 231976 kb
Host smart-02996062-b49d-4898-812e-9f74b94e1f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831006093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1831006093
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3956753436
Short name T772
Test name
Test status
Simulation time 74977308 ps
CPU time 0.7 seconds
Started Jun 27 04:41:47 PM PDT 24
Finished Jun 27 04:41:54 PM PDT 24
Peak memory 205348 kb
Host smart-5a586ada-2482-43f4-aa8e-a6399f45d90f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956753436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
956753436
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.59629838
Short name T4
Test name
Test status
Simulation time 134229587 ps
CPU time 2.39 seconds
Started Jun 27 04:41:42 PM PDT 24
Finished Jun 27 04:41:48 PM PDT 24
Peak memory 223792 kb
Host smart-2696e4d8-b6aa-44fa-be2e-968e8446bc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59629838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.59629838
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2540471413
Short name T399
Test name
Test status
Simulation time 28745288 ps
CPU time 0.76 seconds
Started Jun 27 04:41:40 PM PDT 24
Finished Jun 27 04:41:43 PM PDT 24
Peak memory 206756 kb
Host smart-80c05c1d-a681-456e-8bd3-4c2d19b707f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540471413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2540471413
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1012145923
Short name T159
Test name
Test status
Simulation time 14714748987 ps
CPU time 28.65 seconds
Started Jun 27 04:41:46 PM PDT 24
Finished Jun 27 04:42:22 PM PDT 24
Peak memory 252400 kb
Host smart-c8bb67d9-ab17-46e5-b3b1-c2c60826140e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012145923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1012145923
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3165310382
Short name T131
Test name
Test status
Simulation time 5861261983 ps
CPU time 87.04 seconds
Started Jun 27 04:41:46 PM PDT 24
Finished Jun 27 04:43:20 PM PDT 24
Peak memory 257348 kb
Host smart-7cb5c922-815d-410a-8cad-851fdbc7c446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165310382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3165310382
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2665464949
Short name T31
Test name
Test status
Simulation time 202211963317 ps
CPU time 158.56 seconds
Started Jun 27 04:42:34 PM PDT 24
Finished Jun 27 04:45:16 PM PDT 24
Peak memory 249180 kb
Host smart-282f783f-5fac-4aca-a98e-327c19780a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665464949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2665464949
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1920780985
Short name T433
Test name
Test status
Simulation time 360352307 ps
CPU time 3.99 seconds
Started Jun 27 04:41:43 PM PDT 24
Finished Jun 27 04:41:53 PM PDT 24
Peak memory 224264 kb
Host smart-1f21e3f5-119a-4d69-bc5e-f9c76b113f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920780985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1920780985
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.418483536
Short name T558
Test name
Test status
Simulation time 259332796628 ps
CPU time 117.53 seconds
Started Jun 27 04:41:42 PM PDT 24
Finished Jun 27 04:43:45 PM PDT 24
Peak memory 249072 kb
Host smart-358ba737-426a-4dae-b47d-d3628272bde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418483536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.
418483536
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.858022349
Short name T692
Test name
Test status
Simulation time 1718520362 ps
CPU time 14.43 seconds
Started Jun 27 04:41:42 PM PDT 24
Finished Jun 27 04:42:01 PM PDT 24
Peak memory 224288 kb
Host smart-bf740447-cd97-4a70-bbac-74013aedc9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858022349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.858022349
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3841821549
Short name T227
Test name
Test status
Simulation time 601061149 ps
CPU time 9.77 seconds
Started Jun 27 04:41:42 PM PDT 24
Finished Jun 27 04:41:56 PM PDT 24
Peak memory 231984 kb
Host smart-a14dd66b-5dfd-4866-8e0e-5284f879d9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841821549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3841821549
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.1397543054
Short name T421
Test name
Test status
Simulation time 123832126 ps
CPU time 1.06 seconds
Started Jun 27 04:41:38 PM PDT 24
Finished Jun 27 04:41:41 PM PDT 24
Peak memory 216984 kb
Host smart-37efa758-0ab2-407f-9c3a-7a5795e9505c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397543054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.1397543054
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.4018326102
Short name T441
Test name
Test status
Simulation time 31766706947 ps
CPU time 23.72 seconds
Started Jun 27 04:41:42 PM PDT 24
Finished Jun 27 04:42:09 PM PDT 24
Peak memory 248352 kb
Host smart-5267aa0b-bd04-43c1-88d4-25796183d0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018326102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.4018326102
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.776179659
Short name T764
Test name
Test status
Simulation time 838074604 ps
CPU time 4.58 seconds
Started Jun 27 04:41:41 PM PDT 24
Finished Jun 27 04:41:49 PM PDT 24
Peak memory 232524 kb
Host smart-9c5692a6-f3c1-4e19-9ddb-ce554e5244b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776179659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.776179659
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1866044261
Short name T824
Test name
Test status
Simulation time 1204248586 ps
CPU time 7.28 seconds
Started Jun 27 04:41:42 PM PDT 24
Finished Jun 27 04:41:55 PM PDT 24
Peak memory 221844 kb
Host smart-76b0c99b-84e3-4ea2-b999-7252c77c1cf5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1866044261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1866044261
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.976542462
Short name T15
Test name
Test status
Simulation time 99226102 ps
CPU time 0.96 seconds
Started Jun 27 04:41:48 PM PDT 24
Finished Jun 27 04:41:54 PM PDT 24
Peak memory 207444 kb
Host smart-50ffe5cd-e697-40f6-b62e-792fb46980e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976542462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.976542462
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2211299661
Short name T50
Test name
Test status
Simulation time 2008216086 ps
CPU time 9.95 seconds
Started Jun 27 04:41:39 PM PDT 24
Finished Jun 27 04:41:52 PM PDT 24
Peak memory 216120 kb
Host smart-52d5b53e-8f96-4164-8ab4-d2d6645f9ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211299661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2211299661
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2796156563
Short name T464
Test name
Test status
Simulation time 403582204 ps
CPU time 1.9 seconds
Started Jun 27 04:41:37 PM PDT 24
Finished Jun 27 04:41:41 PM PDT 24
Peak memory 207768 kb
Host smart-28365754-027b-4af0-b8e3-c305fc7f0ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796156563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2796156563
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2821569412
Short name T793
Test name
Test status
Simulation time 135041978 ps
CPU time 2.13 seconds
Started Jun 27 04:41:46 PM PDT 24
Finished Jun 27 04:41:55 PM PDT 24
Peak memory 216064 kb
Host smart-a0426d69-5fbb-48a2-a388-c715c1e3626a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821569412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2821569412
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3994116257
Short name T913
Test name
Test status
Simulation time 123042257 ps
CPU time 0.82 seconds
Started Jun 27 04:41:43 PM PDT 24
Finished Jun 27 04:41:49 PM PDT 24
Peak memory 205760 kb
Host smart-f8801992-a7b9-4abf-b424-42f090337fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994116257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3994116257
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1547283044
Short name T203
Test name
Test status
Simulation time 760580214 ps
CPU time 4.67 seconds
Started Jun 27 04:41:46 PM PDT 24
Finished Jun 27 04:41:57 PM PDT 24
Peak memory 234036 kb
Host smart-68ae0e53-8826-4832-9137-98d93be38841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547283044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1547283044
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1521090328
Short name T382
Test name
Test status
Simulation time 12305023 ps
CPU time 0.73 seconds
Started Jun 27 04:41:45 PM PDT 24
Finished Jun 27 04:41:53 PM PDT 24
Peak memory 205592 kb
Host smart-c83dae07-8350-49d7-bd0c-a73d6048119e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521090328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
521090328
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3960673928
Short name T212
Test name
Test status
Simulation time 84732763 ps
CPU time 3.27 seconds
Started Jun 27 04:41:45 PM PDT 24
Finished Jun 27 04:41:55 PM PDT 24
Peak memory 232492 kb
Host smart-a7395776-6960-42cd-bd76-369d37fcd6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960673928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3960673928
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3313431436
Short name T937
Test name
Test status
Simulation time 36129298 ps
CPU time 0.78 seconds
Started Jun 27 04:41:46 PM PDT 24
Finished Jun 27 04:41:53 PM PDT 24
Peak memory 206480 kb
Host smart-2a70e1c9-6b1d-4715-b0af-dc7c00768956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313431436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3313431436
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1721388737
Short name T819
Test name
Test status
Simulation time 38979004830 ps
CPU time 76.31 seconds
Started Jun 27 04:41:39 PM PDT 24
Finished Jun 27 04:42:59 PM PDT 24
Peak memory 253680 kb
Host smart-4718fbd1-4984-47e8-b355-a1ec0158be6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721388737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1721388737
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3405896728
Short name T532
Test name
Test status
Simulation time 5410048146 ps
CPU time 24.69 seconds
Started Jun 27 04:41:40 PM PDT 24
Finished Jun 27 04:42:08 PM PDT 24
Peak memory 232712 kb
Host smart-5ec85775-cb0c-491f-9cfa-c30bd076dd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405896728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3405896728
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1491490499
Short name T182
Test name
Test status
Simulation time 8265225896 ps
CPU time 100.15 seconds
Started Jun 27 04:41:45 PM PDT 24
Finished Jun 27 04:43:32 PM PDT 24
Peak memory 266480 kb
Host smart-fc068b2c-81f4-4919-88f8-9401df3b0fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491490499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1491490499
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.4230197266
Short name T738
Test name
Test status
Simulation time 141077482 ps
CPU time 6.22 seconds
Started Jun 27 04:41:38 PM PDT 24
Finished Jun 27 04:41:47 PM PDT 24
Peak memory 243096 kb
Host smart-256a5cd1-d0c9-46e5-aa10-3b8f663f3bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230197266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.4230197266
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.2721560938
Short name T335
Test name
Test status
Simulation time 568348370 ps
CPU time 12.41 seconds
Started Jun 27 04:41:41 PM PDT 24
Finished Jun 27 04:41:57 PM PDT 24
Peak memory 239464 kb
Host smart-00cf9332-b207-4102-8317-56b2bfcab7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721560938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.2721560938
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1044409162
Short name T472
Test name
Test status
Simulation time 67505389 ps
CPU time 3.46 seconds
Started Jun 27 04:41:48 PM PDT 24
Finished Jun 27 04:41:57 PM PDT 24
Peak memory 232872 kb
Host smart-c389260d-e594-4a1d-891d-8a379b3f72e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044409162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1044409162
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1266772600
Short name T303
Test name
Test status
Simulation time 462350132 ps
CPU time 2.35 seconds
Started Jun 27 04:41:47 PM PDT 24
Finished Jun 27 04:41:55 PM PDT 24
Peak memory 223728 kb
Host smart-5c78e29e-1c22-4257-91c9-17afea202727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266772600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1266772600
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.412310083
Short name T947
Test name
Test status
Simulation time 34415231 ps
CPU time 1.09 seconds
Started Jun 27 04:41:48 PM PDT 24
Finished Jun 27 04:41:54 PM PDT 24
Peak memory 216680 kb
Host smart-15dfe5b9-8b8b-4b7c-bc9f-71dea5dbf5df
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412310083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.412310083
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2280116690
Short name T983
Test name
Test status
Simulation time 809538306 ps
CPU time 4.58 seconds
Started Jun 27 04:41:48 PM PDT 24
Finished Jun 27 04:41:58 PM PDT 24
Peak memory 224672 kb
Host smart-d52284e7-17cc-497d-8236-22f724bd3c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280116690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2280116690
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.25663953
Short name T5
Test name
Test status
Simulation time 92293292 ps
CPU time 2.55 seconds
Started Jun 27 04:41:49 PM PDT 24
Finished Jun 27 04:41:56 PM PDT 24
Peak memory 224708 kb
Host smart-1a8caebf-a074-4b90-b8d3-d4af724e9405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25663953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.25663953
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.697830314
Short name T505
Test name
Test status
Simulation time 79617797 ps
CPU time 3.8 seconds
Started Jun 27 04:41:48 PM PDT 24
Finished Jun 27 04:41:57 PM PDT 24
Peak memory 222856 kb
Host smart-6a05083e-0f8a-4254-9228-84f1f03201bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=697830314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.697830314
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.770101953
Short name T915
Test name
Test status
Simulation time 4142314136 ps
CPU time 91.17 seconds
Started Jun 27 04:41:42 PM PDT 24
Finished Jun 27 04:43:19 PM PDT 24
Peak memory 249412 kb
Host smart-7408c34a-7345-4176-aa56-24c5e3e8ad6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770101953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.770101953
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.477676608
Short name T624
Test name
Test status
Simulation time 33149274229 ps
CPU time 41.27 seconds
Started Jun 27 04:41:48 PM PDT 24
Finished Jun 27 04:42:35 PM PDT 24
Peak memory 216144 kb
Host smart-bbad477e-3129-4f85-bd06-129ffec6f572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477676608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.477676608
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2260338316
Short name T377
Test name
Test status
Simulation time 1968325625 ps
CPU time 3.33 seconds
Started Jun 27 04:41:48 PM PDT 24
Finished Jun 27 04:41:57 PM PDT 24
Peak memory 216116 kb
Host smart-57695d95-eaa8-47a0-b72b-ad423d4c0e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260338316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2260338316
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.535594984
Short name T459
Test name
Test status
Simulation time 139000870 ps
CPU time 1.68 seconds
Started Jun 27 04:41:48 PM PDT 24
Finished Jun 27 04:41:55 PM PDT 24
Peak memory 216068 kb
Host smart-4363bb20-707c-49a4-8482-fb8ffc7cd513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535594984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.535594984
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3948662233
Short name T312
Test name
Test status
Simulation time 42813746 ps
CPU time 0.69 seconds
Started Jun 27 04:41:48 PM PDT 24
Finished Jun 27 04:41:54 PM PDT 24
Peak memory 205452 kb
Host smart-270c6c9a-4844-447a-ac47-16080e1eebec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948662233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3948662233
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2843601074
Short name T703
Test name
Test status
Simulation time 73097345 ps
CPU time 2.43 seconds
Started Jun 27 04:41:38 PM PDT 24
Finished Jun 27 04:41:43 PM PDT 24
Peak memory 232304 kb
Host smart-9a077ca2-cfb7-43cb-b8ed-e57d9be95387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843601074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2843601074
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.51582728
Short name T650
Test name
Test status
Simulation time 47880266 ps
CPU time 0.71 seconds
Started Jun 27 04:41:46 PM PDT 24
Finished Jun 27 04:41:53 PM PDT 24
Peak memory 205140 kb
Host smart-628565a5-0038-45c1-b035-2042f249a73e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51582728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.51582728
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3045563670
Short name T424
Test name
Test status
Simulation time 4539891391 ps
CPU time 5.25 seconds
Started Jun 27 04:41:43 PM PDT 24
Finished Jun 27 04:41:54 PM PDT 24
Peak memory 232676 kb
Host smart-3c859fbd-b212-42bd-9877-4b8f46f79eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045563670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3045563670
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3065701450
Short name T873
Test name
Test status
Simulation time 151488397 ps
CPU time 0.77 seconds
Started Jun 27 04:41:36 PM PDT 24
Finished Jun 27 04:41:39 PM PDT 24
Peak memory 206820 kb
Host smart-89452f71-29ee-43f9-b17e-e6275265eb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065701450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3065701450
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2343213001
Short name T294
Test name
Test status
Simulation time 9635774090 ps
CPU time 59.59 seconds
Started Jun 27 04:41:45 PM PDT 24
Finished Jun 27 04:42:51 PM PDT 24
Peak memory 249072 kb
Host smart-99469ecf-8cdb-4bd5-aecb-b7b976838eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343213001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2343213001
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2734072391
Short name T681
Test name
Test status
Simulation time 58622117373 ps
CPU time 134.64 seconds
Started Jun 27 04:41:45 PM PDT 24
Finished Jun 27 04:44:06 PM PDT 24
Peak memory 249124 kb
Host smart-dfc54fec-0b1b-4c47-8dd4-d25fc30f11d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734072391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2734072391
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2074172601
Short name T279
Test name
Test status
Simulation time 2365052619 ps
CPU time 5.99 seconds
Started Jun 27 04:41:44 PM PDT 24
Finished Jun 27 04:41:57 PM PDT 24
Peak memory 224456 kb
Host smart-be5bf8cb-5a63-43a8-9649-b3f0cedc28d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074172601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2074172601
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.2441016526
Short name T169
Test name
Test status
Simulation time 103293216572 ps
CPU time 129.44 seconds
Started Jun 27 04:41:42 PM PDT 24
Finished Jun 27 04:43:55 PM PDT 24
Peak memory 248976 kb
Host smart-dfbb9d40-896f-4df4-8f6c-ca48d1767388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441016526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.2441016526
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2933821451
Short name T478
Test name
Test status
Simulation time 1239420770 ps
CPU time 12.79 seconds
Started Jun 27 04:41:45 PM PDT 24
Finished Jun 27 04:42:04 PM PDT 24
Peak memory 232524 kb
Host smart-7f03616a-7011-40a3-b2d1-83322b721b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933821451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2933821451
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2530168219
Short name T423
Test name
Test status
Simulation time 9089714794 ps
CPU time 27 seconds
Started Jun 27 04:41:42 PM PDT 24
Finished Jun 27 04:42:15 PM PDT 24
Peak memory 224416 kb
Host smart-51e0f978-12b5-4ec6-8c8c-fe46a7b4dd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530168219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2530168219
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.2673683691
Short name T1000
Test name
Test status
Simulation time 108688071 ps
CPU time 1.09 seconds
Started Jun 27 04:41:43 PM PDT 24
Finished Jun 27 04:41:49 PM PDT 24
Peak memory 216648 kb
Host smart-1d071af6-1aff-42fd-8079-33a4411116c3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673683691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.2673683691
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.669042785
Short name T610
Test name
Test status
Simulation time 218950867 ps
CPU time 2.54 seconds
Started Jun 27 04:41:37 PM PDT 24
Finished Jun 27 04:41:42 PM PDT 24
Peak memory 224280 kb
Host smart-05befe5d-d47d-45d7-a579-7072c57bed5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669042785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
669042785
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.240926553
Short name T602
Test name
Test status
Simulation time 3159311137 ps
CPU time 10.01 seconds
Started Jun 27 04:41:41 PM PDT 24
Finished Jun 27 04:41:54 PM PDT 24
Peak memory 232564 kb
Host smart-5b494cc3-338a-464d-8449-47fcee2507ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240926553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.240926553
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.4201753468
Short name T141
Test name
Test status
Simulation time 443076326 ps
CPU time 4.03 seconds
Started Jun 27 04:41:41 PM PDT 24
Finished Jun 27 04:41:48 PM PDT 24
Peak memory 220300 kb
Host smart-d4c86357-427a-46f2-8900-38a017a16371
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4201753468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.4201753468
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.228743684
Short name T944
Test name
Test status
Simulation time 52277774171 ps
CPU time 225.34 seconds
Started Jun 27 04:41:41 PM PDT 24
Finished Jun 27 04:45:31 PM PDT 24
Peak memory 251092 kb
Host smart-40161a25-d39e-4ddb-8f30-3c7196c8b5f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228743684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.228743684
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1830020495
Short name T721
Test name
Test status
Simulation time 2836183114 ps
CPU time 2.94 seconds
Started Jun 27 04:41:39 PM PDT 24
Finished Jun 27 04:41:45 PM PDT 24
Peak memory 216168 kb
Host smart-789b8905-5b2a-4b21-9f12-30d306108f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830020495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1830020495
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2839251596
Short name T755
Test name
Test status
Simulation time 396463572 ps
CPU time 1.81 seconds
Started Jun 27 04:41:42 PM PDT 24
Finished Jun 27 04:41:48 PM PDT 24
Peak memory 207840 kb
Host smart-09935e3a-4b8e-43a2-82a7-23695a93c90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839251596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2839251596
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2097825631
Short name T741
Test name
Test status
Simulation time 82358287 ps
CPU time 1.28 seconds
Started Jun 27 04:41:40 PM PDT 24
Finished Jun 27 04:41:45 PM PDT 24
Peak memory 216052 kb
Host smart-da81baa7-2034-4bf1-94b7-f93177d367b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097825631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2097825631
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3387148870
Short name T826
Test name
Test status
Simulation time 114049363 ps
CPU time 0.98 seconds
Started Jun 27 04:41:44 PM PDT 24
Finished Jun 27 04:41:51 PM PDT 24
Peak memory 205688 kb
Host smart-301b701d-a9b9-4544-95e2-fb6e92743e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387148870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3387148870
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2376976020
Short name T239
Test name
Test status
Simulation time 2149063383 ps
CPU time 4.5 seconds
Started Jun 27 04:41:41 PM PDT 24
Finished Jun 27 04:41:49 PM PDT 24
Peak memory 224460 kb
Host smart-0e878843-09b8-4c68-bc51-180f3b50bf22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376976020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2376976020
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3885185421
Short name T813
Test name
Test status
Simulation time 12308457 ps
CPU time 0.74 seconds
Started Jun 27 04:41:48 PM PDT 24
Finished Jun 27 04:41:54 PM PDT 24
Peak memory 205988 kb
Host smart-967cd16b-c442-4238-a011-1cedc8ed3bc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885185421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
885185421
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.644524640
Short name T662
Test name
Test status
Simulation time 2162305547 ps
CPU time 23.7 seconds
Started Jun 27 04:41:46 PM PDT 24
Finished Jun 27 04:42:17 PM PDT 24
Peak memory 232656 kb
Host smart-b8196d96-4276-4b6e-9ff0-106fbe1500b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644524640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.644524640
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3419383787
Short name T409
Test name
Test status
Simulation time 30091042 ps
CPU time 0.78 seconds
Started Jun 27 04:41:46 PM PDT 24
Finished Jun 27 04:41:53 PM PDT 24
Peak memory 205400 kb
Host smart-d323d2e6-3bd8-42b8-bcce-5f61c53c6123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419383787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3419383787
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2057065015
Short name T130
Test name
Test status
Simulation time 53386989876 ps
CPU time 122.7 seconds
Started Jun 27 04:41:45 PM PDT 24
Finished Jun 27 04:43:55 PM PDT 24
Peak memory 249684 kb
Host smart-d7c031fc-c987-4ba3-8c04-fe7fc7acc168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057065015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2057065015
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1558911546
Short name T157
Test name
Test status
Simulation time 22660727688 ps
CPU time 196.22 seconds
Started Jun 27 04:41:48 PM PDT 24
Finished Jun 27 04:45:09 PM PDT 24
Peak memory 252860 kb
Host smart-b7a9c537-6f18-412e-945c-b5491b40838b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558911546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1558911546
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3931653576
Short name T739
Test name
Test status
Simulation time 5771630439 ps
CPU time 116.47 seconds
Started Jun 27 04:41:47 PM PDT 24
Finished Jun 27 04:43:50 PM PDT 24
Peak memory 254708 kb
Host smart-c9727e9d-7b58-459f-89be-7ee12628208c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931653576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3931653576
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.77703581
Short name T142
Test name
Test status
Simulation time 849441202 ps
CPU time 7.1 seconds
Started Jun 27 04:41:48 PM PDT 24
Finished Jun 27 04:42:01 PM PDT 24
Peak memory 232540 kb
Host smart-7574a237-d896-47eb-8d99-09578a66f81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77703581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.77703581
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1548448560
Short name T740
Test name
Test status
Simulation time 5620656286 ps
CPU time 79.64 seconds
Started Jun 27 04:41:47 PM PDT 24
Finished Jun 27 04:43:13 PM PDT 24
Peak memory 257280 kb
Host smart-ecadab66-d358-4b1a-8834-1610be224d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548448560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1548448560
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3520068594
Short name T230
Test name
Test status
Simulation time 120810099 ps
CPU time 3.28 seconds
Started Jun 27 04:41:48 PM PDT 24
Finished Jun 27 04:41:57 PM PDT 24
Peak memory 232540 kb
Host smart-834b8cd7-0b92-427b-99c1-da9e51d7bc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520068594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3520068594
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1369807523
Short name T484
Test name
Test status
Simulation time 453036557 ps
CPU time 7.65 seconds
Started Jun 27 04:41:41 PM PDT 24
Finished Jun 27 04:41:53 PM PDT 24
Peak memory 224284 kb
Host smart-c512a5ec-b986-4518-86ef-bd9b551bef18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369807523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1369807523
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.225598533
Short name T33
Test name
Test status
Simulation time 56568864 ps
CPU time 1.04 seconds
Started Jun 27 04:41:46 PM PDT 24
Finished Jun 27 04:41:53 PM PDT 24
Peak memory 217948 kb
Host smart-35ccaad8-6efe-4bf1-9b3d-b897ede8e3cb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225598533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.spi_device_mem_parity.225598533
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3588817190
Short name T262
Test name
Test status
Simulation time 3705710478 ps
CPU time 10.74 seconds
Started Jun 27 04:41:42 PM PDT 24
Finished Jun 27 04:41:57 PM PDT 24
Peak memory 223844 kb
Host smart-ede52581-c762-45d8-a028-aded5826654f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588817190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3588817190
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.151298524
Short name T425
Test name
Test status
Simulation time 172753188 ps
CPU time 3.1 seconds
Started Jun 27 04:41:43 PM PDT 24
Finished Jun 27 04:41:52 PM PDT 24
Peak memory 232416 kb
Host smart-87bd5bfb-5fb6-43c4-9a90-86586268ae60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151298524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.151298524
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.322097193
Short name T898
Test name
Test status
Simulation time 119436027 ps
CPU time 3.78 seconds
Started Jun 27 04:41:48 PM PDT 24
Finished Jun 27 04:41:57 PM PDT 24
Peak memory 222884 kb
Host smart-62bf6cbf-8bdb-4302-a430-fc797f62ba07
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=322097193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.322097193
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3089014512
Short name T981
Test name
Test status
Simulation time 10114800097 ps
CPU time 28.16 seconds
Started Jun 27 04:41:46 PM PDT 24
Finished Jun 27 04:42:21 PM PDT 24
Peak memory 220156 kb
Host smart-2aceaa47-f64c-4c7f-b27a-2a6177ebfc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089014512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3089014512
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1982146517
Short name T317
Test name
Test status
Simulation time 4099208952 ps
CPU time 4.02 seconds
Started Jun 27 04:41:43 PM PDT 24
Finished Jun 27 04:41:54 PM PDT 24
Peak memory 216124 kb
Host smart-3f9fe327-9909-4642-abde-3df17327d16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982146517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1982146517
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3436044554
Short name T336
Test name
Test status
Simulation time 13104330 ps
CPU time 0.73 seconds
Started Jun 27 04:41:43 PM PDT 24
Finished Jun 27 04:41:51 PM PDT 24
Peak memory 205680 kb
Host smart-6cf69a81-6505-4f7c-9f67-15ae80b83b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436044554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3436044554
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3211323619
Short name T530
Test name
Test status
Simulation time 38956491 ps
CPU time 0.74 seconds
Started Jun 27 04:41:39 PM PDT 24
Finished Jun 27 04:41:43 PM PDT 24
Peak memory 205808 kb
Host smart-b9bf893b-2904-4b08-9177-5502af323eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211323619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3211323619
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3298362924
Short name T661
Test name
Test status
Simulation time 11001893641 ps
CPU time 15.89 seconds
Started Jun 27 04:41:48 PM PDT 24
Finished Jun 27 04:42:09 PM PDT 24
Peak memory 224464 kb
Host smart-12d722e6-3059-4619-9c73-ce5ce77fa11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298362924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3298362924
Directory /workspace/9.spi_device_upload/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%