Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2710633	1			T1	717		T2	2267		T3	878
all_values[1]	2710633	1			T1	717		T2	2267		T3	878
all_values[2]	2710633	1			T1	717		T2	2267		T3	878
all_values[3]	2710633	1			T1	717		T2	2267		T3	878
all_values[4]	2710633	1			T1	717		T2	2267		T3	878
all_values[5]	2710633	1			T1	717		T2	2267		T3	878
all_values[6]	2710633	1			T1	717		T2	2267		T3	878
all_values[7]	2710633	1			T1	717		T2	2267		T3	878

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21473057

1

T1

5736

T2

18101

T3

6952

auto[1]

212007

1

T2

35

T3

72

T16

81

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21658497

1

T1

5729

T2

18031

T3

6967

auto[1]

26567

1

T1

7

T2

105

T3

57

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2669620	1			T1	710		T2	2221		T3	866
all_values[0]	auto[0]	auto[1]	12350	1			T1	7		T2	43		T3	1
all_values[0]	auto[1]	auto[0]	28237	1			T2	1		T3	6		T16	9
all_values[0]	auto[1]	auto[1]	426	1			T2	2		T3	5		T16	5
all_values[1]	auto[0]	auto[0]	2677574	1			T1	717		T2	2243		T3	866
all_values[1]	auto[0]	auto[1]	8158	1			T2	19		T3	3		T24	50
all_values[1]	auto[1]	auto[0]	24681	1			T2	4		T3	5		T16	6
all_values[1]	auto[1]	auto[1]	220	1			T2	1		T3	4		T16	2
all_values[2]	auto[0]	auto[0]	2680158	1			T1	717		T2	2247		T3	866
all_values[2]	auto[0]	auto[1]	3454	1			T2	17		T3	2		T16	2
all_values[2]	auto[1]	auto[0]	26852	1			T2	1		T3	3		T16	4
all_values[2]	auto[1]	auto[1]	169	1			T2	2		T3	7		T16	4
all_values[3]	auto[0]	auto[0]	2681782	1			T1	717		T2	2261		T3	866
all_values[3]	auto[0]	auto[1]	171	1			T2	2		T3	1		T16	3
all_values[3]	auto[1]	auto[0]	28455	1			T2	1		T3	5		T16	6
all_values[3]	auto[1]	auto[1]	225	1			T2	3		T3	6		T16	7
all_values[4]	auto[0]	auto[0]	2688072	1			T1	717		T2	2260		T3	867
all_values[4]	auto[0]	auto[1]	168	1			T2	3		T3	3		T16	4
all_values[4]	auto[1]	auto[0]	22214	1			T2	2		T3	5		T16	9
all_values[4]	auto[1]	auto[1]	179	1			T2	2		T3	3		T16	1
all_values[5]	auto[0]	auto[0]	2684185	1			T1	717		T2	2260		T3	867
all_values[5]	auto[0]	auto[1]	171	1			T3	2		T16	4		T19	1
all_values[5]	auto[1]	auto[0]	26125	1			T2	5		T3	2		T16	5
all_values[5]	auto[1]	auto[1]	152	1			T2	2		T3	7		T16	2
all_values[6]	auto[0]	auto[0]	2683436	1			T1	717		T2	2260		T3	868
all_values[6]	auto[0]	auto[1]	184	1			T2	1		T3	2		T16	7
all_values[6]	auto[1]	auto[0]	26840	1			T2	3		T3	5		T16	9
all_values[6]	auto[1]	auto[1]	173	1			T2	3		T3	3		T16	1
all_values[7]	auto[0]	auto[0]	2683398	1			T1	717		T2	2261		T3	865
all_values[7]	auto[0]	auto[1]	176	1			T2	3		T3	7		T16	3
all_values[7]	auto[1]	auto[0]	26868	1			T2	1		T3	5		T16	3
all_values[7]	auto[1]	auto[1]	191	1			T2	2		T3	1		T16	8