Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	36074	1			T1	314		T2	304		T7	78
auto[SpiFlashAddrCfg]	7497	1			T1	28		T2	16		T7	52
auto[SpiFlashAddr3b]	9295	1			T1	41		T2	25		T7	45
auto[SpiFlashAddr4b]	7787	1			T1	44		T2	19		T7	45

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33278

1

T1

318

T2

210

T7

122

auto[1]

27375

1

T1

109

T2

154

T7

98

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32915

1

T1

225

T2

80

T7

120

auto[1]

27738

1

T1

202

T2

284

T7

100

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	40836	1			T1	344		T2	323		T7	109
values[1]	1120	1			T1	10		T2	5		T7	7
values[2]	1474	1			T1	6		T2	5		T7	8
values[3]	1420	1			T1	6		T2	5		T7	7
values[4]	1441	1			T1	8		T2	2		T7	5
values[5]	1450	1			T1	7		T2	2		T7	6
values[6]	1432	1			T1	5		T2	4		T7	8
values[7]	1457	1			T1	3		T2	3		T7	3
values[8]	10023	1			T1	38		T2	15		T7	67

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29208

1

T7

220

T9

131

T13

4

auto[1]

31445

1

T1

427

T2

364

T10

227

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

57262

1

T1

411

T2

350

T7

203

write

3391

1

T1

16

T2

14

T7

17

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19725

1

T1

86

T2

54

T7

105

valids[0x1]

40928

1

T1

341

T2

310

T7

115

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1613	1			T1	13		T2	2		T7	11
internal_process_ops[0x5a]	1531	1			T1	10		T2	5		T7	11
internal_process_ops[0x05]	21875	1			T1	238		T2	251		T7	10
internal_process_ops[0x35]	1605	1			T1	7		T2	6		T7	7
internal_process_ops[0x15]	1608	1			T1	9		T2	5		T7	8
internal_process_ops[0x03]	957	1			T1	2		T2	3		T7	6
internal_process_ops[0x0b]	1056	1			T2	1		T7	14		T9	2
internal_process_ops[0x3b]	1094	1			T1	6		T7	14		T9	1
internal_process_ops[0x6b]	1075	1			T1	1		T2	1		T7	8
internal_process_ops[0xbb]	1095	1			T1	1		T2	1		T7	8
internal_process_ops[0xeb]	1016	1			T1	2		T7	10		T9	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59037

1

T1

416

T2

356

T7

209

auto[1]

1616

1

T1

11

T2

8

T7

11

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58216

1

T1

416

T2

350

T7

207

auto[1]

2437

1

T1

11

T2

14

T7

13

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9135

1

T7

45

T9

67

T13

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5812

1

T7

27

T9

5

T24

21

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2015

1

T7

28

T9

6

T14

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1909

1

T7

21

T9

5

T24

16

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2524

1

T7

23

T9

15

T13

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2210

1

T7

18

T9

4

T24

17

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2065

1

T7

19

T9

10

T14

10

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1864

1

T7

22

T9

11

T24

13

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

111

1

T42

1

T39

1

T17

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

75

1

T7

1

T41

1

T33

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

104

1

T7

2

T37

2

T39

7

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

120

1

T7

3

T42

1

T38

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

110

1

T7

1

T37

3

T44

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

86

1

T7

1

T41

2

T42

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

114

1

T7

1

T24

6

T37

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

126

1

T9

1

T37

2

T40

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

141

1

T24

3

T41

1

T39

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

86

1

T7

1

T9

2

T24

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

113

1

T7

1

T9

4

T37

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

96

1

T7

2

T37

2

T40

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

126

1

T9

1

T44

2

T17

8

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

77

1

T7

3

T42

1

T39

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

79

1

T7

1

T24

2

T38

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

110

1

T37

5

T41

1

T42

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11082

1

T1

268

T2

174

T10

89

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

9205

1

T1

44

T2

127

T10

73

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1421

1

T1

14

T2

13

T10

9

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1351

1

T1

13

T2

1

T10

13

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1836

1

T1

15

T2

15

T10

8

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1842

1

T1

22

T2

9

T10

8

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1508

1

T1

16

T2

2

T10

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1483

1

T1

19

T2

9

T10

12

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

115

1

T10

2

T96

1

T74

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

122

1

T2

1

T10

2

T74

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

103

1

T1

2

T74

2

T60

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

90

1

T2

2

T96

2

T74

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

86

1

T1

1

T10

2

T96

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

89

1

T61

1

T27

1

T20

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

85

1

T2

2

T74

1

T60

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

105

1

T12

1

T96

1

T74

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

137

1

T10

3

T96

2

T74

5

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

105

1

T1

1

T2

1

T74

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

107

1

T10

2

T12

3

T74

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

98

1

T1

3

T60

3

T61

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

112

1

T12

1

T60

2

T61

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

114

1

T1

3

T2

4

T10

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

132

1

T1

2

T2

4

T61

6

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

117

1

T1

4

T12

1

T96

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3953	1			T7	34		T9	14		T15	2
auto[0]	values[0]	valids[0x1]	13911	1			T7	75		T9	72		T13	2
auto[0]	values[1]	valids[0x1]	596	1			T7	7		T9	6		T14	4
auto[0]	values[2]	valids[0x0]	556	1			T7	6		T9	3		T24	2
auto[0]	values[2]	valids[0x1]	302	1			T7	2		T24	1		T37	3
auto[0]	values[3]	valids[0x0]	550	1			T7	7		T24	7		T37	8
auto[0]	values[3]	valids[0x1]	256	1			T13	2		T24	3		T37	6
auto[0]	values[4]	valids[0x0]	550	1			T7	5		T9	1		T24	1
auto[0]	values[4]	valids[0x1]	265	1			T37	3		T40	2		T42	4
auto[0]	values[5]	valids[0x0]	542	1			T7	4		T9	2		T24	7
auto[0]	values[5]	valids[0x1]	313	1			T7	2		T9	2		T24	4
auto[0]	values[6]	valids[0x0]	515	1			T7	6		T9	3		T14	2
auto[0]	values[6]	valids[0x1]	289	1			T7	2		T9	1		T14	2
auto[0]	values[7]	valids[0x0]	539	1			T7	3		T9	5		T24	3
auto[0]	values[7]	valids[0x1]	286	1			T9	2		T24	1		T37	2
auto[0]	values[8]	valids[0x0]	3650	1			T7	40		T9	13		T14	4
auto[0]	values[8]	valids[0x1]	2135	1			T7	27		T9	7		T24	12
auto[1]	values[0]	valids[0x0]	4105	1			T1	40		T2	36		T10	22
auto[1]	values[0]	valids[0x1]	18867	1			T1	304		T2	287		T10	161
auto[1]	values[1]	valids[0x1]	524	1			T1	10		T2	5		T10	3
auto[1]	values[2]	valids[0x0]	374	1			T1	5		T2	2		T10	4
auto[1]	values[2]	valids[0x1]	242	1			T1	1		T2	3		T96	3
auto[1]	values[3]	valids[0x0]	372	1			T1	1		T2	5		T96	2
auto[1]	values[3]	valids[0x1]	242	1			T1	5		T12	2		T74	6
auto[1]	values[4]	valids[0x0]	388	1			T1	6		T10	1		T96	6
auto[1]	values[4]	valids[0x1]	238	1			T1	2		T2	2		T12	1
auto[1]	values[5]	valids[0x0]	367	1			T1	4		T2	1		T10	3
auto[1]	values[5]	valids[0x1]	228	1			T1	3		T2	1		T12	1
auto[1]	values[6]	valids[0x0]	372	1			T1	5		T2	4		T10	2
auto[1]	values[6]	valids[0x1]	256	1			T10	1		T12	9		T96	1
auto[1]	values[7]	valids[0x0]	389	1			T1	3		T2	2		T10	4
auto[1]	values[7]	valids[0x1]	243	1			T2	1		T12	2		T96	7
auto[1]	values[8]	valids[0x0]	2503	1			T1	22		T2	4		T10	22
auto[1]	values[8]	valids[0x1]	1735	1			T1	16		T2	11		T10	4