Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3289255

1

T1

6990

T2

7091

T3

1

auto[1]

34847

1

T1

227

T2

244

T7

139

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

874839

1

T1

57

T2

38

T3

1

auto[1]

2449263

1

T1

7160

T2

7297

T7

19098

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	721869	1			T1	2934		T2	656		T3	1
auto[524288:1048575]	383153	1			T1	4		T2	828		T7	4762
auto[1048576:1572863]	417692	1			T1	260		T2	1221		T7	2782
auto[1572864:2097151]	356818	1			T1	1096		T2	521		T7	3853
auto[2097152:2621439]	389590	1			T1	334		T2	3231		T7	2720
auto[2621440:3145727]	362187	1			T1	527		T2	290		T7	367
auto[3145728:3670015]	376482	1			T1	852		T7	3386		T9	1082
auto[3670016:4194303]	316311	1			T1	1210		T2	588		T7	460

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2484843

1

T1

7214

T2

7333

T3

1

auto[1]

839259

1

T1

3

T2

2

T7

12

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2909175

1

T1

6704

T2

6557

T3

1

auto[1]

414927

1

T1

513

T2

778

T7

973

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	197412	1			T1	2		T2	2		T3	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	460182	1			T1	2932		T2	642		T7	1206
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	97500	1			T1	4		T7	89		T9	3
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	228795	1			T2	769		T7	4383		T10	1231
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	139742	1			T1	4		T2	6		T7	40
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	224553	1			T1	256		T2	1209		T7	2740
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	78241	1			T1	11		T7	55		T9	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	218629	1			T1	1046		T2	1		T7	3112
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	85353	1			T1	4		T2	11		T7	26
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	242092	1			T1	270		T2	3151		T7	2691
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	72869	1			T1	2		T2	2		T7	49
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	228002	1			T1	496		T2	8		T7	257
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	105072	1			T1	5		T7	39		T9	8
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	224858	1			T1	576		T7	3335		T9	128
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	88409	1			T1	9		T2	1		T7	65
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	190682	1			T1	890		T2	514		T7	388
auto[0]	auto[1]	auto[0:524287]	auto[0]	1253	1			T24	1		T42	1		T96	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	57648	1			T24	512		T96	271		T38	1839
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	689	1			T7	27		T10	2		T37	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	51316	1			T7	256		T10	128		T12	256
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	746	1			T12	2		T37	4		T41	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	49388	1			T2	1		T12	5		T37	128
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	722	1			T2	1		T7	40		T10	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	54661	1			T2	516		T7	640		T12	259
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	695	1			T1	2		T12	2		T15	6
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	56285	1			T1	58		T12	4		T24	5
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	782	1			T1	1		T2	1		T7	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	56131	1			T1	1		T2	256		T10	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	679	1			T1	2		T9	7		T10	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	42059	1			T1	257		T9	904		T10	6
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	513	1			T37	2		T41	3		T96	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	33297	1			T1	162		T37	512		T41	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	577	1			T2	2		T7	6		T9	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	4028	1			T2	10		T7	39		T9	1
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	430	1			T2	1		T7	4		T10	5
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3820	1			T2	58		T10	97		T41	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	350	1			T2	1		T7	2		T10	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2050	1			T2	1		T10	5		T24	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	379	1			T1	3		T2	1		T7	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3433	1			T1	36		T2	2		T9	10
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	369	1			T2	3		T7	3		T24	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2873	1			T2	66		T37	56		T42	9
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	492	1			T2	3		T7	15		T10	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	3045	1			T2	20		T7	42		T10	8
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	486	1			T1	1		T7	3		T12	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1767	1			T1	8		T7	9		T12	19
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	339	1			T1	5		T2	2		T7	7
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2346	1			T1	144		T2	71		T9	2
auto[1]	auto[1]	auto[0:524287]	auto[0]	114	1			T96	1		T61	3		T166	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	655	1			T96	57		T64	22		T191	16
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	86	1			T7	3		T61	10		T63	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	517	1			T61	13		T63	14		T178	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	70	1			T2	1		T12	1		T41	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	793	1			T2	2		T41	2		T38	30
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	111	1			T7	3		T12	1		T96	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	642	1			T12	15		T96	29		T20	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	109	1			T61	7		T167	2		T64	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	1814	1			T167	4		T64	8		T205	14
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	72	1			T1	1		T60	3		T200	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	794	1			T1	26		T60	42		T200	9
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	103	1			T1	1		T9	4		T10	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	1458	1			T1	2		T9	31		T10	6
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	75	1			T41	1		T39	4		T59	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	650	1			T41	2		T39	19		T59	3

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2044853	1			T1	6504		T2	6316		T3	1
auto[0]	auto[0]	auto[1]	837538	1			T1	3		T10	4		T12	1
auto[0]	auto[1]	auto[0]	405829	1			T1	483		T2	775		T7	967
auto[0]	auto[1]	auto[1]	1035	1			T9	3		T10	1		T15	4
auto[1]	auto[0]	auto[0]	26209	1			T1	197		T2	239		T7	123
auto[1]	auto[0]	auto[1]	575	1			T2	2		T7	10		T9	3
auto[1]	auto[1]	auto[0]	7952	1			T1	30		T2	3		T7	4
auto[1]	auto[1]	auto[1]	111	1			T7	2		T9	2		T12	1