Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2710633	1			T1	717		T2	2267		T3	878
all_pins[1]	2710633	1			T1	717		T2	2267		T3	878
all_pins[2]	2710633	1			T1	717		T2	2267		T3	878
all_pins[3]	2710633	1			T1	717		T2	2267		T3	878
all_pins[4]	2710633	1			T1	717		T2	2267		T3	878
all_pins[5]	2710633	1			T1	717		T2	2267		T3	878
all_pins[6]	2710633	1			T1	717		T2	2267		T3	878
all_pins[7]	2710633	1			T1	717		T2	2267		T3	878

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21656829	1			T1	5736		T2	18119		T3	6988
values[0x1]	28235	1			T2	17		T3	36		T16	30
transitions[0x0=>0x1]	27208	1			T2	11		T3	25		T16	22
transitions[0x1=>0x0]	27218	1			T2	11		T3	25		T16	22

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2710176	1			T1	717		T2	2265		T3	873
all_pins[0]	values[0x1]	457	1			T2	2		T3	5		T16	5
all_pins[0]	transitions[0x0=>0x1]	374	1			T2	2		T3	4		T16	3
all_pins[0]	transitions[0x1=>0x0]	145	1			T2	1		T3	3		T19	1
all_pins[1]	values[0x0]	2710405	1			T1	717		T2	2266		T3	874
all_pins[1]	values[0x1]	228	1			T2	1		T3	4		T16	2
all_pins[1]	transitions[0x0=>0x1]	183	1			T2	1		T3	2		T16	1
all_pins[1]	transitions[0x1=>0x0]	127	1			T2	2		T3	5		T16	3
all_pins[2]	values[0x0]	2710461	1			T1	717		T2	2265		T3	871
all_pins[2]	values[0x1]	172	1			T2	2		T3	7		T16	4
all_pins[2]	transitions[0x0=>0x1]	123	1			T3	4		T16	2		T18	2
all_pins[2]	transitions[0x1=>0x0]	176	1			T2	1		T3	3		T16	5
all_pins[3]	values[0x0]	2710408	1			T1	717		T2	2264		T3	872
all_pins[3]	values[0x1]	225	1			T2	3		T3	6		T16	7
all_pins[3]	transitions[0x0=>0x1]	171	1			T2	3		T3	3		T16	6
all_pins[3]	transitions[0x1=>0x0]	125	1			T2	2		T18	2		T19	1
all_pins[4]	values[0x0]	2710454	1			T1	717		T2	2265		T3	875
all_pins[4]	values[0x1]	179	1			T2	2		T3	3		T16	1
all_pins[4]	transitions[0x0=>0x1]	142	1			T3	1		T16	1		T18	2
all_pins[4]	transitions[0x1=>0x0]	754	1			T3	5		T16	2		T18	207
all_pins[5]	values[0x0]	2709842	1			T1	717		T2	2265		T3	871
all_pins[5]	values[0x1]	791	1			T2	2		T3	7		T16	2
all_pins[5]	transitions[0x0=>0x1]	136	1			T2	2		T3	7		T16	2
all_pins[5]	transitions[0x1=>0x0]	25337	1			T2	3		T3	3		T16	1
all_pins[6]	values[0x0]	2684641	1			T1	717		T2	2264		T3	875
all_pins[6]	values[0x1]	25992	1			T2	3		T3	3		T16	1
all_pins[6]	transitions[0x0=>0x1]	25940	1			T2	2		T3	3		T16	1
all_pins[6]	transitions[0x1=>0x0]	139	1			T2	1		T3	1		T16	8
all_pins[7]	values[0x0]	2710442	1			T1	717		T2	2265		T3	877
all_pins[7]	values[0x1]	191	1			T2	2		T3	1		T16	8
all_pins[7]	transitions[0x0=>0x1]	139	1			T2	1		T3	1		T16	6
all_pins[7]	transitions[0x1=>0x0]	415	1			T2	1		T3	5		T16	3