Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16551

1

T7

122

T9

101

T13

4

auto[1]

12657

1

T7

98

T9

30

T24

75

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3723	1			T9	25		T24	20		T37	159
values[1]	3585	1			T7	20		T206	2		T37	60
values[2]	3178	1			T7	20		T37	20		T42	29
values[3]	3580	1			T7	40		T9	20		T24	20
values[4]	3880	1			T7	40		T14	16		T15	2
values[5]	4095	1			T7	20		T9	86		T13	4
values[6]	3285	1			T7	40		T37	52		T40	16
values[7]	3882	1			T7	40		T24	21		T37	54

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3961	1			T7	40		T9	45		T24	25
values[1]	3662	1			T7	20		T9	86		T37	67
values[2]	3557	1			T7	20		T24	40		T37	72
values[3]	3479	1			T37	40		T42	90		T38	92
values[4]	3611	1			T13	4		T14	16		T37	74
values[5]	3652	1			T7	80		T24	20		T206	2
values[6]	3656	1			T7	40		T24	49		T37	92
values[7]	3630	1			T7	20		T15	2		T24	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	239	1			T9	21		T41	13		T174	6
auto[0]	values[0]	values[1]	262	1			T37	56		T39	10		T17	11
auto[0]	values[0]	values[2]	336	1			T38	13		T62	19		T190	11
auto[0]	values[0]	values[3]	306	1			T38	13		T179	133		T117	14
auto[0]	values[0]	values[4]	434	1			T63	29		T62	9		T22	23
auto[0]	values[0]	values[5]	136	1			T167	11		T166	10		T175	10
auto[0]	values[0]	values[6]	274	1			T37	84		T160	26		T168	14
auto[0]	values[0]	values[7]	268	1			T24	9		T63	7		T58	16
auto[0]	values[1]	values[0]	281	1			T37	14		T38	11		T39	8
auto[0]	values[1]	values[1]	152	1			T207	2		T167	10		T208	6
auto[0]	values[1]	values[2]	238	1			T37	12		T42	14		T17	12
auto[0]	values[1]	values[3]	213	1			T17	15		T190	11		T145	11
auto[0]	values[1]	values[4]	351	1			T38	12		T167	8		T62	27
auto[0]	values[1]	values[5]	325	1			T7	16		T206	2		T117	24
auto[0]	values[1]	values[6]	215	1			T42	13		T173	10		T62	12
auto[0]	values[1]	values[7]	293	1			T33	14		T76	18		T182	10
auto[0]	values[2]	values[0]	253	1			T38	10		T39	12		T166	14
auto[0]	values[2]	values[1]	204	1			T169	17		T45	14		T209	54
auto[0]	values[2]	values[2]	232	1			T156	6		T189	2		T175	12
auto[0]	values[2]	values[3]	263	1			T37	16		T42	5		T17	12
auto[0]	values[2]	values[4]	219	1			T166	16		T155	15		T139	11
auto[0]	values[2]	values[5]	155	1			T7	10		T184	24		T210	4
auto[0]	values[2]	values[6]	252	1			T173	12		T211	4		T45	8
auto[0]	values[2]	values[7]	158	1			T117	13		T155	6		T196	14
auto[0]	values[3]	values[0]	361	1			T7	9		T9	12		T73	12
auto[0]	values[3]	values[1]	370	1			T42	40		T38	37		T39	13
auto[0]	values[3]	values[2]	179	1			T24	10		T165	13		T194	11
auto[0]	values[3]	values[3]	204	1			T38	33		T39	13		T17	10
auto[0]	values[3]	values[4]	194	1			T175	14		T28	10		T212	6
auto[0]	values[3]	values[5]	372	1			T7	13		T37	10		T41	17
auto[0]	values[3]	values[6]	212	1			T22	14		T213	9		T187	76
auto[0]	values[3]	values[7]	164	1			T37	7		T145	15		T156	15
auto[0]	values[4]	values[0]	221	1			T24	20		T167	13		T197	8
auto[0]	values[4]	values[1]	338	1			T7	6		T39	6		T17	12
auto[0]	values[4]	values[2]	189	1			T39	10		T171	18		T117	8
auto[0]	values[4]	values[3]	234	1			T42	10		T194	13		T176	11
auto[0]	values[4]	values[4]	266	1			T14	16		T37	13		T63	9
auto[0]	values[4]	values[5]	369	1			T38	14		T145	19		T175	13
auto[0]	values[4]	values[6]	426	1			T7	12		T24	7		T44	35
auto[0]	values[4]	values[7]	264	1			T15	2		T167	4		T62	54
auto[0]	values[5]	values[0]	318	1			T37	13		T17	9		T62	12
auto[0]	values[5]	values[1]	354	1			T9	68		T41	8		T214	6
auto[0]	values[5]	values[2]	272	1			T7	12		T24	13		T75	4
auto[0]	values[5]	values[3]	220	1			T38	10		T166	23		T203	16
auto[0]	values[5]	values[4]	246	1			T13	4		T117	16		T215	14
auto[0]	values[5]	values[5]	481	1			T24	13		T39	12		T17	7
auto[0]	values[5]	values[6]	224	1			T216	8		T156	12		T182	12
auto[0]	values[5]	values[7]	246	1			T72	8		T38	15		T217	4
auto[0]	values[6]	values[0]	260	1			T39	15		T218	14		T178	26
auto[0]	values[6]	values[1]	170	1			T202	4		T18	11		T219	10
auto[0]	values[6]	values[2]	205	1			T37	15		T22	11		T138	15
auto[0]	values[6]	values[3]	163	1			T42	17		T220	4		T156	12
auto[0]	values[6]	values[4]	155	1			T37	8		T167	9		T22	12
auto[0]	values[6]	values[5]	264	1			T7	12		T167	11		T165	14
auto[0]	values[6]	values[6]	287	1			T221	6		T176	6		T146	11
auto[0]	values[6]	values[7]	204	1			T7	9		T33	13		T167	22
auto[0]	values[7]	values[0]	277	1			T7	13		T17	21		T62	8
auto[0]	values[7]	values[1]	260	1			T167	13		T222	6		T223	14
auto[0]	values[7]	values[2]	320	1			T42	7		T39	20		T17	24
auto[0]	values[7]	values[3]	238	1			T37	12		T167	13		T63	23
auto[0]	values[7]	values[4]	310	1			T37	11		T42	11		T224	2
auto[0]	values[7]	values[5]	123	1			T155	8		T186	9		T28	29
auto[0]	values[7]	values[6]	230	1			T7	10		T24	7		T167	10
auto[0]	values[7]	values[7]	302	1			T38	47		T53	14		T145	17
auto[1]	values[0]	values[0]	225	1			T9	4		T41	11		T117	11
auto[1]	values[0]	values[1]	257	1			T37	11		T39	10		T17	70
auto[1]	values[0]	values[2]	167	1			T38	7		T62	24		T190	9
auto[1]	values[0]	values[3]	203	1			T38	7		T117	6		T155	13
auto[1]	values[0]	values[4]	233	1			T63	7		T62	11		T22	6
auto[1]	values[0]	values[5]	125	1			T167	13		T166	11		T175	10
auto[1]	values[0]	values[6]	107	1			T37	8		T155	10		T175	6
auto[1]	values[0]	values[7]	151	1			T24	11		T63	20		T177	10
auto[1]	values[1]	values[0]	189	1			T37	6		T38	9		T39	12
auto[1]	values[1]	values[1]	162	1			T167	16		T172	20		T196	24
auto[1]	values[1]	values[2]	239	1			T37	28		T42	8		T17	8
auto[1]	values[1]	values[3]	237	1			T17	8		T190	9		T145	12
auto[1]	values[1]	values[4]	235	1			T38	78		T167	13		T225	10
auto[1]	values[1]	values[5]	137	1			T7	4		T117	17		T45	10
auto[1]	values[1]	values[6]	189	1			T42	7		T173	10		T62	8
auto[1]	values[1]	values[7]	129	1			T33	12		T226	26		T182	10
auto[1]	values[2]	values[0]	221	1			T38	37		T39	8		T166	7
auto[1]	values[2]	values[1]	77	1			T169	5		T45	6		T209	12
auto[1]	values[2]	values[2]	280	1			T156	14		T175	8		T187	108
auto[1]	values[2]	values[3]	241	1			T37	4		T42	24		T17	8
auto[1]	values[2]	values[4]	86	1			T166	4		T155	5		T139	9
auto[1]	values[2]	values[5]	104	1			T7	10		T29	7		T227	14
auto[1]	values[2]	values[6]	196	1			T173	8		T56	10		T228	6
auto[1]	values[2]	values[7]	237	1			T117	7		T155	14		T196	6
auto[1]	values[3]	values[0]	244	1			T7	11		T9	8		T37	13
auto[1]	values[3]	values[1]	309	1			T42	7		T38	9		T39	7
auto[1]	values[3]	values[2]	235	1			T24	10		T165	7		T194	9
auto[1]	values[3]	values[3]	113	1			T38	12		T39	7		T17	35
auto[1]	values[3]	values[4]	91	1			T175	6		T28	10		T229	17
auto[1]	values[3]	values[5]	214	1			T7	7		T37	10		T41	8
auto[1]	values[3]	values[6]	213	1			T22	6		T230	22		T213	11
auto[1]	values[3]	values[7]	105	1			T37	32		T145	6		T156	5
auto[1]	values[4]	values[0]	235	1			T24	5		T167	13		T178	6
auto[1]	values[4]	values[1]	179	1			T7	14		T39	14		T17	9
auto[1]	values[4]	values[2]	174	1			T39	10		T117	12		T22	5
auto[1]	values[4]	values[3]	146	1			T42	10		T194	7		T176	9
auto[1]	values[4]	values[4]	168	1			T37	7		T63	45		T62	9
auto[1]	values[4]	values[5]	343	1			T38	6		T145	5		T175	7
auto[1]	values[4]	values[6]	117	1			T7	8		T24	21		T39	4
auto[1]	values[4]	values[7]	211	1			T167	20		T62	24		T182	8
auto[1]	values[5]	values[0]	287	1			T37	7		T17	11		T62	8
auto[1]	values[5]	values[1]	258	1			T9	18		T41	15		T178	20
auto[1]	values[5]	values[2]	102	1			T7	8		T24	7		T38	10
auto[1]	values[5]	values[3]	157	1			T38	17		T166	24		T196	8
auto[1]	values[5]	values[4]	187	1			T117	4		T156	7		T182	7
auto[1]	values[5]	values[5]	254	1			T24	7		T39	8		T17	13
auto[1]	values[5]	values[6]	155	1			T156	8		T182	8		T196	7
auto[1]	values[5]	values[7]	334	1			T38	109		T178	13		T156	3
auto[1]	values[6]	values[0]	137	1			T39	5		T178	33		T156	10
auto[1]	values[6]	values[1]	144	1			T18	9		T170	4		T231	6
auto[1]	values[6]	values[2]	137	1			T37	17		T22	9		T138	5
auto[1]	values[6]	values[3]	280	1			T42	24		T156	8		T176	10
auto[1]	values[6]	values[4]	140	1			T37	12		T167	11		T22	8
auto[1]	values[6]	values[5]	186	1			T7	8		T167	9		T165	6
auto[1]	values[6]	values[6]	231	1			T40	16		T176	53		T146	11
auto[1]	values[6]	values[7]	322	1			T7	11		T33	7		T167	19
auto[1]	values[7]	values[0]	213	1			T7	7		T17	23		T62	16
auto[1]	values[7]	values[1]	166	1			T232	8		T167	7		T22	8
auto[1]	values[7]	values[2]	252	1			T42	13		T39	20		T17	5
auto[1]	values[7]	values[3]	261	1			T37	8		T167	7		T63	13
auto[1]	values[7]	values[4]	296	1			T37	23		T42	9		T117	15
auto[1]	values[7]	values[5]	64	1			T155	12		T186	11		T28	13
auto[1]	values[7]	values[6]	328	1			T7	10		T24	14		T167	10
auto[1]	values[7]	values[7]	242	1			T38	4		T145	6		T233	9