Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	427	1			T7	7		T9	1		T24	2
auto[ReadAddrCrossIntoMailbox]	308	1			T7	6		T24	1		T37	7
auto[ReadAddrCrossOutOfMailbox]	299	1			T7	8		T37	8		T41	2
auto[ReadAddrCrossAllMailbox]	221	1			T7	3		T24	2		T37	4
auto[ReadAddrOutsideMailbox]	3557	1			T7	36		T9	12		T14	8

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2394

1

T7

23

T9

8

T14

4

auto[1]

2418

1

T7

37

T9

5

T14

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	741	1			T7	6		T9	1		T14	2
read_ops[0x0b]	798	1			T7	14		T9	2		T14	4
read_ops[0x3b]	839	1			T7	14		T9	1		T24	5
read_ops[0x6b]	826	1			T7	8		T9	2		T24	6
read_ops[0xbb]	853	1			T7	8		T9	6		T24	9
read_ops[0xeb]	755	1			T7	10		T9	1		T14	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T7	2		T63	2		T234	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T234	1		T138	1		T146	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T37	3		T182	1		T146	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T42	1		T39	1		T155	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T7	2		T37	1		T156	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T7	1		T37	1		T167	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T182	1		T169	1		T45	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T24	1		T42	1		T22	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	285	1			T7	1		T9	1		T14	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	280	1			T14	1		T24	3		T41	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T24	1		T37	1		T39	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T41	1		T38	1		T17	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T41	1		T17	2		T63	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T7	1		T37	1		T42	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T7	2		T17	1		T145	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T41	1		T33	1		T62	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T24	1		T37	1		T41	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T7	1		T17	1		T173	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	309	1			T7	5		T14	2		T37	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	302	1			T7	5		T9	2		T14	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	43	1			T24	1		T37	2		T39	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	49	1			T7	2		T9	1		T37	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T24	1		T41	2		T173	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T7	2		T38	2		T39	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T39	1		T167	1		T63	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T33	1		T194	1		T176	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T42	1		T22	1		T176	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T37	1		T42	1		T165	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	313	1			T7	3		T24	3		T41	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	293	1			T7	7		T37	6		T42	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T7	1		T37	1		T38	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T37	1		T41	1		T42	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	39	1			T7	1		T37	2		T42	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T38	1		T117	1		T166	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T42	1		T38	1		T39	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T37	1		T38	2		T194	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T42	2		T33	1		T182	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T38	1		T39	1		T63	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	264	1			T9	1		T24	2		T37	5
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	339	1			T7	6		T9	1		T24	4
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	47	1			T7	1		T38	3		T17	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T39	1		T58	1		T203	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T42	1		T39	1		T202	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T42	1		T202	1		T63	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T42	1		T63	2		T58	3
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	35	1			T17	2		T63	1		T58	3
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T166	1		T182	1		T146	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T7	1		T37	1		T39	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	287	1			T7	2		T9	6		T24	5
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	325	1			T7	4		T24	4		T37	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T37	2		T42	1		T17	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T7	1		T39	1		T17	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T7	2		T37	1		T42	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T42	1		T39	1		T117	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T37	1		T41	1		T42	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T7	3		T37	4		T42	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	29	1			T39	1		T17	2		T173	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T7	1		T37	1		T63	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	274	1			T7	1		T14	1		T24	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	286	1			T7	2		T9	1		T14	1