Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3342	1			T7	20		T14	16		T24	20
values[1]	3204	1			T7	40		T9	20		T37	87
values[2]	3548	1			T7	20		T13	4		T24	20
values[3]	3470	1			T7	20		T9	20		T15	2
values[4]	3840	1			T7	40		T9	66		T24	68
values[5]	4077	1			T7	20		T37	86		T42	47
values[6]	3832	1			T7	20		T9	25		T24	25
values[7]	3895	1			T7	40		T24	21		T37	152

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4162	1			T7	60		T14	16		T24	65
values[1]	3409	1			T7	20		T9	20		T24	21
values[2]	3784	1			T9	25		T13	4		T37	67
values[3]	3346	1			T7	60		T9	20		T37	54
values[4]	4138	1			T7	20		T24	20		T206	2
values[5]	3252	1			T7	40		T15	2		T73	12
values[6]	3570	1			T7	20		T37	72		T41	25
values[7]	3547	1			T9	66		T24	48		T37	112

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28432

1

T7

209

T9

128

T13

4

auto[1]

776

1

T7

11

T9

3

T24

3

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	461	1			T14	16		T24	20		T38	89
auto[0]	values[0]	values[1]	525	1			T37	20		T38	20		T17	45
auto[0]	values[0]	values[2]	384	1			T173	19		T117	23		T156	20
auto[0]	values[0]	values[3]	518	1			T7	18		T40	10		T41	23
auto[0]	values[0]	values[4]	360	1			T166	20		T155	20		T176	63
auto[0]	values[0]	values[5]	362	1			T37	18		T18	18		T62	23
auto[0]	values[0]	values[6]	398	1			T33	23		T38	27		T39	20
auto[0]	values[0]	values[7]	241	1			T39	20		T17	29		T222	6
auto[0]	values[1]	values[0]	438	1			T7	20		T167	20		T178	57
auto[0]	values[1]	values[1]	451	1			T9	20		T178	20		T176	20
auto[0]	values[1]	values[2]	416	1			T37	67		T166	20		T155	20
auto[0]	values[1]	values[3]	345	1			T7	19		T224	2		T63	26
auto[0]	values[1]	values[4]	651	1			T38	124		T160	26		T62	20
auto[0]	values[1]	values[5]	222	1			T182	20		T177	20		T235	20
auto[0]	values[1]	values[6]	209	1			T37	18		T62	20		T172	16
auto[0]	values[1]	values[7]	412	1			T167	20		T217	4		T117	20
auto[0]	values[2]	values[0]	585	1			T7	18		T42	20		T39	20
auto[0]	values[2]	values[1]	307	1			T38	45		T39	20		T236	6
auto[0]	values[2]	values[2]	483	1			T13	4		T167	20		T63	99
auto[0]	values[2]	values[3]	395	1			T37	20		T181	12		T139	20
auto[0]	values[2]	values[4]	639	1			T194	20		T22	27		T176	20
auto[0]	values[2]	values[5]	366	1			T39	20		T180	20		T174	6
auto[0]	values[2]	values[6]	290	1			T38	20		T45	25		T237	46
auto[0]	values[2]	values[7]	405	1			T24	20		T75	4		T39	19
auto[0]	values[3]	values[0]	522	1			T165	19		T166	27		T145	21
auto[0]	values[3]	values[1]	342	1			T44	35		T63	40		T165	20
auto[0]	values[3]	values[2]	334	1			T41	21		T38	50		T238	12
auto[0]	values[3]	values[3]	288	1			T9	20		T17	19		T63	77
auto[0]	values[3]	values[4]	398	1			T206	2		T167	68		T201	16
auto[0]	values[3]	values[5]	392	1			T7	18		T15	2		T73	12
auto[0]	values[3]	values[6]	444	1			T63	35		T62	23		T156	18
auto[0]	values[3]	values[7]	650	1			T42	29		T167	20		T62	20
auto[0]	values[4]	values[0]	348	1			T24	18		T37	39		T38	20
auto[0]	values[4]	values[1]	379	1			T7	20		T42	44		T214	6
auto[0]	values[4]	values[2]	751	1			T42	19		T234	6		T22	147
auto[0]	values[4]	values[3]	480	1			T42	15		T17	20		T63	53
auto[0]	values[4]	values[4]	592	1			T24	19		T37	19		T38	43
auto[0]	values[4]	values[5]	391	1			T7	18		T22	21		T145	24
auto[0]	values[4]	values[6]	391	1			T37	18		T39	20		T239	6
auto[0]	values[4]	values[7]	399	1			T9	64		T24	28		T166	40
auto[0]	values[5]	values[0]	497	1			T42	19		T190	19		T145	20
auto[0]	values[5]	values[1]	343	1			T17	79		T182	19		T45	21
auto[0]	values[5]	values[2]	326	1			T178	24		T146	22		T175	20
auto[0]	values[5]	values[3]	416	1			T37	34		T167	19		T155	19
auto[0]	values[5]	values[4]	598	1			T7	19		T42	26		T76	18
auto[0]	values[5]	values[5]	652	1			T33	18		T202	4		T179	133
auto[0]	values[5]	values[6]	638	1			T37	31		T166	25		T240	22
auto[0]	values[5]	values[7]	483	1			T37	17		T56	10		T221	6
auto[0]	values[6]	values[0]	865	1			T7	20		T24	25		T17	18
auto[0]	values[6]	values[1]	524	1			T17	20		T178	20		T22	29
auto[0]	values[6]	values[2]	394	1			T9	24		T39	19		T167	19
auto[0]	values[6]	values[3]	307	1			T241	8		T196	20		T213	40
auto[0]	values[6]	values[4]	340	1			T167	44		T178	39		T226	24
auto[0]	values[6]	values[5]	377	1			T63	20		T117	42		T215	14
auto[0]	values[6]	values[6]	526	1			T41	22		T42	20		T62	71
auto[0]	values[6]	values[7]	394	1			T72	8		T42	19		T117	20
auto[0]	values[7]	values[0]	326	1			T37	39		T218	14		T178	35
auto[0]	values[7]	values[1]	449	1			T24	21		T156	20		T213	20
auto[0]	values[7]	values[2]	605	1			T167	20		T197	8		T171	18
auto[0]	values[7]	values[3]	499	1			T7	19		T42	20		T39	20
auto[0]	values[7]	values[4]	463	1			T37	20		T38	20		T225	10
auto[0]	values[7]	values[5]	393	1			T41	22		T17	20		T207	2
auto[0]	values[7]	values[6]	565	1			T7	20		T38	67		T190	17
auto[0]	values[7]	values[7]	488	1			T37	89		T17	23		T232	6
auto[1]	values[0]	values[0]	12	1			T38	1		T39	1		T182	1
auto[1]	values[0]	values[1]	3	1			T186	1		T242	1		T243	1
auto[1]	values[0]	values[2]	8	1			T173	1		T117	1		T146	2
auto[1]	values[0]	values[3]	36	1			T7	2		T40	6		T41	1
auto[1]	values[0]	values[4]	7	1			T244	1		T118	1		T245	4
auto[1]	values[0]	values[5]	12	1			T37	2		T18	2		T235	1
auto[1]	values[0]	values[6]	13	1			T33	3		T156	1		T28	1
auto[1]	values[0]	values[7]	2	1			T246	2		-	-		-	-
auto[1]	values[1]	values[0]	18	1			T178	1		T22	3		T146	2
auto[1]	values[1]	values[1]	4	1			T246	1		T247	2		T248	1
auto[1]	values[1]	values[2]	4	1			T187	2		T249	1		T250	1
auto[1]	values[1]	values[3]	8	1			T7	1		T63	1		T231	1
auto[1]	values[1]	values[4]	11	1			T146	1		T175	1		T163	2
auto[1]	values[1]	values[5]	3	1			T251	3		-	-		-	-
auto[1]	values[1]	values[6]	8	1			T37	2		T172	4		T245	2
auto[1]	values[1]	values[7]	4	1			T167	1		T242	1		T251	1
auto[1]	values[2]	values[0]	16	1			T7	2		T209	1		T188	2
auto[1]	values[2]	values[1]	14	1			T38	1		T177	5		T252	4
auto[1]	values[2]	values[2]	9	1			T63	2		T62	2		T188	3
auto[1]	values[2]	values[3]	9	1			T237	2		T243	2		T253	1
auto[1]	values[2]	values[4]	12	1			T254	1		T231	3		T255	2
auto[1]	values[2]	values[5]	7	1			T256	3		T257	4		-	-
auto[1]	values[2]	values[6]	4	1			T237	2		T229	1		T243	1
auto[1]	values[2]	values[7]	7	1			T39	1		T146	1		T186	2
auto[1]	values[3]	values[0]	24	1			T165	1		T166	3		T138	3
auto[1]	values[3]	values[1]	8	1			T213	1		T187	1		T258	2
auto[1]	values[3]	values[2]	13	1			T41	4		T38	1		T190	1
auto[1]	values[3]	values[3]	6	1			T17	1		T63	2		T254	1
auto[1]	values[3]	values[4]	12	1			T167	2		T22	2		T182	1
auto[1]	values[3]	values[5]	14	1			T7	2		T63	1		T146	2
auto[1]	values[3]	values[6]	14	1			T63	1		T62	1		T156	2
auto[1]	values[3]	values[7]	9	1			T178	4		T145	1		T196	1
auto[1]	values[4]	values[0]	8	1			T24	2		T117	1		T237	2
auto[1]	values[4]	values[1]	17	1			T42	3		T62	1		T146	1
auto[1]	values[4]	values[2]	17	1			T42	2		T45	1		T259	2
auto[1]	values[4]	values[3]	11	1			T42	5		T63	1		T22	1
auto[1]	values[4]	values[4]	19	1			T24	1		T37	1		T38	2
auto[1]	values[4]	values[5]	14	1			T7	2		T182	4		T243	4
auto[1]	values[4]	values[6]	17	1			T37	2		T22	1		T187	2
auto[1]	values[4]	values[7]	6	1			T9	2		T166	2		T139	1
auto[1]	values[5]	values[0]	12	1			T42	1		T190	1		T145	1
auto[1]	values[5]	values[1]	14	1			T17	2		T182	1		T260	3
auto[1]	values[5]	values[2]	14	1			T146	2		T170	1		T186	1
auto[1]	values[5]	values[3]	8	1			T167	1		T155	1		T170	1
auto[1]	values[5]	values[4]	18	1			T7	1		T42	1		T167	3
auto[1]	values[5]	values[5]	21	1			T33	2		T155	1		T196	3
auto[1]	values[5]	values[6]	19	1			T37	1		T166	3		T22	2
auto[1]	values[5]	values[7]	18	1			T37	3		T22	2		T209	4
auto[1]	values[6]	values[0]	22	1			T17	2		T173	1		T63	2
auto[1]	values[6]	values[1]	12	1			T17	3		T176	1		T186	2
auto[1]	values[6]	values[2]	10	1			T9	1		T39	1		T167	1
auto[1]	values[6]	values[3]	6	1			T186	1		T28	2		T144	1
auto[1]	values[6]	values[4]	11	1			T167	1		T226	2		T196	1
auto[1]	values[6]	values[5]	14	1			T156	2		T229	4		T242	1
auto[1]	values[6]	values[6]	16	1			T41	3		T62	7		T187	2
auto[1]	values[6]	values[7]	14	1			T42	3		T163	3		T261	2
auto[1]	values[7]	values[0]	8	1			T37	1		T186	1		T164	3
auto[1]	values[7]	values[1]	17	1			T177	4		T262	2		T29	1
auto[1]	values[7]	values[2]	16	1			T22	1		T233	1		T45	1
auto[1]	values[7]	values[3]	14	1			T7	1		T170	2		T141	1
auto[1]	values[7]	values[4]	7	1			T178	1		T187	1		T188	1
auto[1]	values[7]	values[5]	12	1			T41	1		T117	4		T196	1
auto[1]	values[7]	values[6]	18	1			T190	3		T45	3		T170	1
auto[1]	values[7]	values[7]	15	1			T37	3		T17	1		T232	2