Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	732	1			T2	7		T3	14		T16	17
all_values[1]	732	1			T2	7		T3	14		T16	17
all_values[2]	732	1			T2	7		T3	14		T16	17
all_values[3]	732	1			T2	7		T3	14		T16	17
all_values[4]	732	1			T2	7		T3	14		T16	17
all_values[5]	732	1			T2	7		T3	14		T16	17
all_values[6]	732	1			T2	7		T3	14		T16	17
all_values[7]	732	1			T2	7		T3	14		T16	17

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3122

1

T2

31

T3

50

T16

65

auto[1]

2734

1

T2

25

T3

62

T16

71

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2294

1

T2

24

T3

45

T16

56

auto[1]

3562

1

T2

32

T3

67

T16

80

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3353

1

T2

33

T3

66

T16

82

auto[1]

2503

1

T2

23

T3

46

T16

54

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	140	1			T2	3		T3	4		T145	1
all_values[0]	auto[0]	auto[0]	auto[1]	78	1			T16	3		T18	2		T19	1
all_values[0]	auto[0]	auto[1]	auto[0]	130	1			T2	1		T3	2		T16	5
all_values[0]	auto[0]	auto[1]	auto[1]	70	1			T3	4		T16	3		T18	1
all_values[0]	auto[1]	auto[0]	auto[1]	168	1			T2	2		T3	1		T16	3
all_values[0]	auto[1]	auto[1]	auto[1]	146	1			T2	1		T3	3		T16	3
all_values[1]	auto[0]	auto[0]	auto[0]	145	1			T2	2		T3	2		T16	3
all_values[1]	auto[0]	auto[0]	auto[1]	76	1			T3	1		T16	2		T18	1
all_values[1]	auto[0]	auto[1]	auto[0]	116	1			T2	2		T3	4		T16	6
all_values[1]	auto[0]	auto[1]	auto[1]	90	1			T2	1		T3	3		T18	1
all_values[1]	auto[1]	auto[0]	auto[1]	164	1			T2	1		T3	2		T16	4
all_values[1]	auto[1]	auto[1]	auto[1]	141	1			T2	1		T3	2		T16	2
all_values[2]	auto[0]	auto[0]	auto[0]	175	1			T2	5		T3	4		T16	4
all_values[2]	auto[0]	auto[0]	auto[1]	58	1			T3	1		T62	1		T145	1
all_values[2]	auto[0]	auto[1]	auto[0]	132	1			T16	4		T19	5		T146	2
all_values[2]	auto[0]	auto[1]	auto[1]	60	1			T2	1		T3	3		T16	2
all_values[2]	auto[1]	auto[0]	auto[1]	176	1			T3	4		T16	4		T19	1
all_values[2]	auto[1]	auto[1]	auto[1]	131	1			T2	1		T3	2		T16	3
all_values[3]	auto[0]	auto[0]	auto[0]	127	1			T2	2		T3	2		T16	2
all_values[3]	auto[0]	auto[0]	auto[1]	64	1			T2	1		T16	3		T18	2
all_values[3]	auto[0]	auto[1]	auto[0]	107	1			T3	4		T16	3		T19	2
all_values[3]	auto[0]	auto[1]	auto[1]	98	1			T2	1		T3	2		T16	1
all_values[3]	auto[1]	auto[0]	auto[1]	164	1			T2	1		T16	2		T19	2
all_values[3]	auto[1]	auto[1]	auto[1]	172	1			T2	2		T3	6		T16	6
all_values[4]	auto[0]	auto[0]	auto[0]	154	1			T3	1		T16	4		T18	2
all_values[4]	auto[0]	auto[0]	auto[1]	82	1			T2	1		T3	1		T16	3
all_values[4]	auto[0]	auto[1]	auto[0]	128	1			T3	5		T16	4		T19	2
all_values[4]	auto[0]	auto[1]	auto[1]	70	1			T3	1		T18	1		T19	2
all_values[4]	auto[1]	auto[0]	auto[1]	173	1			T2	3		T3	5		T16	3
all_values[4]	auto[1]	auto[1]	auto[1]	125	1			T2	3		T3	1		T16	3
all_values[5]	auto[0]	auto[0]	auto[0]	220	1			T2	2		T3	4		T16	8
all_values[5]	auto[0]	auto[1]	auto[0]	189	1			T2	3		T3	1		T16	3
all_values[5]	auto[1]	auto[0]	auto[1]	190	1			T3	1		T16	4		T19	2
all_values[5]	auto[1]	auto[1]	auto[1]	133	1			T2	2		T3	8		T16	2
all_values[6]	auto[0]	auto[0]	auto[0]	153	1			T2	1		T3	5		T16	2
all_values[6]	auto[0]	auto[0]	auto[1]	85	1			T16	3		T62	2		T145	1
all_values[6]	auto[0]	auto[1]	auto[0]	111	1			T2	1		T3	2		T16	4
all_values[6]	auto[0]	auto[1]	auto[1]	80	1			T2	2		T3	1		T16	1
all_values[6]	auto[1]	auto[0]	auto[1]	169	1			T2	2		T3	3		T16	3
all_values[6]	auto[1]	auto[1]	auto[1]	134	1			T2	1		T3	3		T16	4
all_values[7]	auto[0]	auto[0]	auto[0]	144	1			T2	2		T3	3		T16	3
all_values[7]	auto[0]	auto[0]	auto[1]	62	1			T2	2		T3	2		T62	2
all_values[7]	auto[0]	auto[1]	auto[0]	123	1			T3	2		T16	1		T19	4
all_values[7]	auto[0]	auto[1]	auto[1]	86	1			T3	2		T16	5		T18	1
all_values[7]	auto[1]	auto[0]	auto[1]	155	1			T2	1		T3	4		T16	2
all_values[7]	auto[1]	auto[1]	auto[1]	162	1			T2	2		T3	1		T16	6

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal