Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1805

1

T1

1

T2

11

T3

2

auto[1]

1863

1

T2

9

T3

11

T4

11

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2075

1

T1

1

T2

17

T3

13

auto[1]

1593

1

T2

3

T6

8

T11

8

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2857

1

T1

1

T2

14

T3

12

auto[1]

811

1

T2

6

T3

1

T4

6

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	761	1			T2	5		T3	3		T4	3
valid[1]	724	1			T3	3		T4	2		T6	3
valid[2]	753	1			T2	5		T3	3		T4	6
valid[3]	711	1			T2	4		T3	1		T4	3
valid[4]	719	1			T1	1		T2	6		T3	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	142	1			T2	1		T37	1		T41	1
auto[0]	auto[0]	valid[0]	auto[1]	155	1			T2	1		T11	1		T23	2
auto[0]	auto[0]	valid[1]	auto[0]	112	1			T41	1		T33	3		T17	3
auto[0]	auto[0]	valid[1]	auto[1]	169	1			T6	1		T25	4		T71	1
auto[0]	auto[0]	valid[2]	auto[0]	122	1			T2	1		T3	1		T4	1
auto[0]	auto[0]	valid[2]	auto[1]	153	1			T11	1		T25	4		T71	1
auto[0]	auto[0]	valid[3]	auto[0]	107	1			T2	2		T4	1		T37	1
auto[0]	auto[0]	valid[3]	auto[1]	148	1			T6	1		T11	1		T42	1
auto[0]	auto[0]	valid[4]	auto[0]	139	1			T1	1		T2	2		T4	1
auto[0]	auto[0]	valid[4]	auto[1]	166	1			T2	1		T6	2		T71	1
auto[0]	auto[1]	valid[0]	auto[0]	119	1			T2	1		T3	3		T4	1
auto[0]	auto[1]	valid[0]	auto[1]	179	1			T2	1		T25	1		T71	1
auto[0]	auto[1]	valid[1]	auto[0]	136	1			T3	3		T4	2		T24	1
auto[0]	auto[1]	valid[1]	auto[1]	150	1			T6	2		T25	1		T71	2
auto[0]	auto[1]	valid[2]	auto[0]	141	1			T2	2		T3	2		T4	3
auto[0]	auto[1]	valid[2]	auto[1]	163	1			T11	1		T25	1		T42	1
auto[0]	auto[1]	valid[3]	auto[0]	131	1			T2	1		T3	1		T4	1
auto[0]	auto[1]	valid[3]	auto[1]	154	1			T11	2		T71	2		T42	1
auto[0]	auto[1]	valid[4]	auto[0]	115	1			T2	1		T3	2		T4	1
auto[0]	auto[1]	valid[4]	auto[1]	156	1			T6	2		T11	2		T42	1
auto[1]	auto[0]	valid[0]	auto[0]	84	1			T2	1		T4	1		T33	1
auto[1]	auto[0]	valid[1]	auto[0]	79	1			T41	1		T283	1		T167	1
auto[1]	auto[0]	valid[2]	auto[0]	83	1			T2	1		T4	1		T41	3
auto[1]	auto[0]	valid[3]	auto[0]	69	1			T24	1		T98	1		T167	1
auto[1]	auto[0]	valid[4]	auto[0]	77	1			T2	1		T3	1		T4	1
auto[1]	auto[1]	valid[0]	auto[0]	82	1			T4	1		T41	2		T42	1
auto[1]	auto[1]	valid[1]	auto[0]	78	1			T17	1		T98	2		T18	2
auto[1]	auto[1]	valid[2]	auto[0]	91	1			T2	1		T4	1		T41	1
auto[1]	auto[1]	valid[3]	auto[0]	102	1			T2	1		T4	1		T24	1
auto[1]	auto[1]	valid[4]	auto[0]	66	1			T2	1		T41	1		T42	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal