Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50497

1

T1

39

T2

415

T3

351

auto[1]

17098

1

T2

48

T6

8

T11

8

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49214

1

T1

26

T2

317

T3

250

auto[1]

18381

1

T1

13

T2

146

T3

101

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34573	1			T1	24		T2	238		T3	176
others[1]	5718	1			T1	3		T2	27		T3	31
others[2]	5742	1			T1	3		T2	34		T3	31
others[3]	6447	1			T1	4		T2	51		T3	34
interest[1]	3779	1			T2	29		T3	23		T4	10
interest[4]	22592	1			T1	10		T2	161		T3	116
interest[64]	11336	1			T1	5		T2	84		T3	56

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16455	1			T1	13		T2	135		T3	126
auto[0]	auto[0]	others[1]	2722	1			T1	2		T2	17		T3	22
auto[0]	auto[0]	others[2]	2716	1			T1	3		T2	18		T3	22
auto[0]	auto[0]	others[3]	3071	1			T1	4		T2	32		T3	23
auto[0]	auto[0]	interest[1]	1780	1			T2	19		T3	17		T4	8
auto[0]	auto[0]	interest[4]	10766	1			T1	5		T2	93		T3	85
auto[0]	auto[0]	interest[64]	5372	1			T1	4		T2	48		T3	40
auto[0]	auto[1]	others[0]	8810	1			T2	30		T6	8		T11	8
auto[0]	auto[1]	others[1]	1422	1			T2	1		T42	4		T69	50
auto[0]	auto[1]	others[2]	1425	1			T2	6		T42	7		T69	28
auto[0]	auto[1]	others[3]	1600	1			T2	3		T42	11		T69	48
auto[0]	auto[1]	interest[1]	976	1			T2	1		T42	5		T69	25
auto[0]	auto[1]	interest[4]	5802	1			T2	19		T6	8		T11	8
auto[0]	auto[1]	interest[64]	2865	1			T2	7		T42	19		T69	75
auto[1]	auto[0]	others[0]	9308	1			T1	11		T2	73		T3	50
auto[1]	auto[0]	others[1]	1574	1			T1	1		T2	9		T3	9
auto[1]	auto[0]	others[2]	1601	1			T2	10		T3	9		T4	2
auto[1]	auto[0]	others[3]	1776	1			T2	16		T3	11		T4	9
auto[1]	auto[0]	interest[1]	1023	1			T2	9		T3	6		T4	2
auto[1]	auto[0]	interest[4]	6024	1			T1	5		T2	49		T3	31
auto[1]	auto[0]	interest[64]	3099	1			T1	1		T2	29		T3	16

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal